| /external/pcre/dist2/src/sljit/ |
| D | sljitNativeMIPS_64.c | 85 ins = (shift == 32) ? DSLL32 : DSLL; in load_immediate()
179 FAIL_IF(push_inst(compiler, DSLL32 | T(src2) | D(dst) | SH_IMM(24), DR(dst))); in emit_single_op()
194 FAIL_IF(push_inst(compiler, DSLL32 | T(src2) | D(dst) | SH_IMM(16), DR(dst))); in emit_single_op()
206 FAIL_IF(push_inst(compiler, DSLL32 | T(src2) | D(dst) | SH_IMM(0), DR(dst))); in emit_single_op()
290 …FAIL_IF(push_inst(compiler, SELECT_OP(DSLL32, SLL) | TA(OTHER_FLAG) | D(TMP_REG1) | SH_IMM(31), DR… in emit_single_op()
423 …FAIL_IF(push_inst(compiler, SELECT_OP(DSLL32, SLL) | TA(OTHER_FLAG) | D(TMP_REG1) | SH_IMM(31), DR… in emit_single_op()
491 EMIT_SHIFT(DSLL, DSLL32, SLL, DSLLV, SLLV); in emit_single_op()
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| D | sljitNativeMIPS_common.c | 142 #define DSLL32 (HI(0) | LO(60)) macro
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| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| D | Mips64InstrInfo.td | 119 def DSLL32 : LogicR_shift_rotate_imm64<0x3c, 0x00, "dsll32", shl, imm32_63>;
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| /external/v8/src/mips64/ |
| D | constants-mips64.h | 545 DSLL32 = ((7U << 3) + 4), enumerator
1320 FunctionFieldToBitNumber(DSLL) | FunctionFieldToBitNumber(DSLL32) |
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| D | disasm-mips64.cc | 1454 case DSLL32: in DecodeTypeRegisterSPECIAL()
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| D | assembler-mips64.cc | 2218 GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa & 0x1F, DSLL32); in dsll32()
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| D | simulator-mips64.cc | 3696 case DSLL32: in DecodeTypeRegisterSPECIAL()
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| /external/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 2499 TOut.emitRRI(Mips::DSLL32, DstReg, DstReg, 0, IDLoc, STI); in loadAndAddSymbolAddress()
3111 TOut.emitRRI(Mips::DSLL32, ATReg, ATReg, 0x1f, IDLoc, STI); in expandDiv()
3633 FirstShift = Mips::DSLL32; in expandDRotationImm()
3637 FirstShift = Mips::DSLL32; in expandDRotationImm()
3644 SecondShift = Mips::DSLL32; in expandDRotationImm()
3648 SecondShift = Mips::DSLL32; in expandDRotationImm()
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| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsMCCodeEmitter.cpp | 70 Inst.setOpcode(Mips::DSLL32); in LowerLargeShift()
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| D | MipsTargetStreamer.cpp | 203 emitRRI(Mips::DSLL32, DstReg, SrcReg, ShiftAmount - 32, IDLoc, STI); in emitDSLL()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsMCCodeEmitter.cpp | 78 Inst.setOpcode(Mips::DSLL32); in LowerLargeShift()
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| D | MipsTargetStreamer.cpp | 235 emitRRI(Mips::DSLL32, DstReg, SrcReg, ShiftAmount - 32, IDLoc, STI); in emitDSLL()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsSEISelDAGToDAG.cpp | 1272 Mips::DSLL32, DL, MVT::i64, SDValue(HiRes, 0), in trySelect()
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| D | Mips64InstrInfo.td | 173 def DSLL32 : shift_rotate_imm<"dsll32", uimm5, GPR64Opnd, II_DSLL32>,
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 3088 TOut.emitRRI(Mips::DSLL32, DstReg, DstReg, 0, IDLoc, STI); in loadAndAddSymbolAddress()
4653 FirstShift = Mips::DSLL32; in expandDRotationImm()
4657 FirstShift = Mips::DSLL32; in expandDRotationImm()
4664 SecondShift = Mips::DSLL32; in expandDRotationImm()
4668 SecondShift = Mips::DSLL32; in expandDRotationImm()
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| /external/llvm/lib/Target/Mips/ |
| D | Mips64InstrInfo.td | 155 def DSLL32 : StdMMR6Rel, shift_rotate_imm<"dsll32", uimm5, GPR64Opnd,
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| /external/capstone/arch/Mips/ |
| D | MipsGenAsmWriter.inc | 634 1107312817U, // DSLL32
2348 0U, // DSLL32
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| D | MipsGenDisassemblerTables.inc | 4160 /* 318 */ MCD_OPC_Decode, 233, 4, 232, 1, // Opcode: DSLL32
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
| D | MipsGenMCCodeEmitter.inc | 1293 UINT64_C(60), // DSLL32
4673 case Mips::DSLL32:
9019 Feature_HasStdEnc | Feature_HasMips3 | Feature_NotInMicroMips | 0, // DSLL32 = 1280
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| D | MipsGenAsmWriter.inc | 2508 268452087U, // DSLL32
5139 4U, // DSLL32
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| D | MipsGenAsmMatcher.inc | 6107 …{ 3844 /* dsll32 */, Mips::DSLL32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1, Fe…
6108 …{ 3844 /* dsll32 */, Mips::DSLL32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2, Fe…
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| D | MipsGenInstrInfo.inc | 1295 DSLL32 = 1280,
5340 …odeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #1280 = DSLL32
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| D | MipsGenDisassemblerTables.inc | 6888 /* 435 */ MCD::OPC_Decode, 128, 10, 236, 2, // Opcode: DSLL32
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