| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | TargetCallingConv.h | 29 unsigned IsZExt : 1; ///< Zero extended
54 : IsZExt(0), IsSExt(0), IsInReg(0), IsSRet(0), IsByVal(0), IsNest(0), in ArgFlagsTy()
63 bool isZExt() const { return IsZExt; } in isZExt()
64 void setZExt() { IsZExt = 1; } in setZExt()
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| D | MachineFrameInfo.h | 480 void setObjectZExt(int ObjectIdx, bool IsZExt) { in setObjectZExt() argument
483 Objects[ObjectIdx+NumFixedObjects].isZExt = IsZExt; in setObjectZExt()
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| D | TargetLowering.h | 181 bool IsZExt : 1; variable
193 : IsSExt(false), IsZExt(false), IsInReg(false), IsSRet(false), in ArgListEntry()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 204 bool WantResult = true, bool IsZExt = false);
224 bool emitCmp(const Value *LHS, const Value *RHS, bool IsZExt);
225 bool emitICmp(MVT RetVT, const Value *LHS, const Value *RHS, bool IsZExt);
238 bool IsZExt = false);
242 bool IsZExt = false);
266 uint64_t Imm, bool IsZExt = true);
270 uint64_t Imm, bool IsZExt = true);
274 uint64_t Imm, bool IsZExt = false);
316 bool IsZExt = isa<ZExtInst>(I); in isIntExtFree() local
323 if ((IsZExt && Arg->hasZExtAttr()) || (!IsZExt && Arg->hasSExtAttr())) in isIntExtFree()
[all …]
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| D | AArch64ISelLowering.cpp | 2383 Entry.IsZExt = false; in LowerFSINCOS()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 160 bool WantResult = true, bool IsZExt = false);
180 bool emitCmp(const Value *LHS, const Value *RHS, bool IsZExt);
181 bool emitICmp(MVT RetVT, const Value *LHS, const Value *RHS, bool IsZExt);
192 bool IsZExt = false);
196 bool IsZExt = false);
220 uint64_t Imm, bool IsZExt = true);
224 uint64_t Imm, bool IsZExt = true);
228 uint64_t Imm, bool IsZExt = false);
270 bool IsZExt = isa<ZExtInst>(I); in isIntExtFree() local
277 if ((IsZExt && Arg->hasZExtAttr()) || (!IsZExt && Arg->hasSExtAttr())) in isIntExtFree()
[all …]
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCFastISel.cpp | 158 const TargetRegisterClass *RC, bool IsZExt = true,
165 unsigned DestReg, bool IsZExt);
464 bool IsZExt, unsigned FP64LoadOpc) { in PPCEmitLoad() argument
492 Opc = (IsZExt ? in PPCEmitLoad()
497 Opc = (IsZExt ? in PPCEmitLoad()
814 bool IsZExt, unsigned DestReg) { in PPCEmitCmp() argument
837 Imm = (IsZExt) ? (long)CIVal.getZExtValue() : (long)CIVal.getSExtValue(); in PPCEmitCmp()
838 if ((IsZExt && isUInt<16>(Imm)) || (!IsZExt && isInt<16>(Imm))) in PPCEmitCmp()
860 CmpOpc = IsZExt ? PPC::CMPLW : PPC::CMPW; in PPCEmitCmp()
862 CmpOpc = IsZExt ? PPC::CMPLWI : PPC::CMPWI; in PPCEmitCmp()
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCFastISel.cpp | 159 const TargetRegisterClass *RC, bool IsZExt = true,
166 unsigned DestReg, bool IsZExt);
467 bool IsZExt, unsigned FP64LoadOpc) { in PPCEmitLoad() argument
496 Opc = (IsZExt ? (Is32BitInt ? PPC::LHZ : PPC::LHZ8) in PPCEmitLoad()
500 Opc = (IsZExt ? (Is32BitInt ? PPC::LWZ : PPC::LWZ8) in PPCEmitLoad()
833 bool IsZExt, unsigned DestReg, in PPCEmitCmp() argument
858 Imm = (IsZExt) ? (long)CIVal.getZExtValue() : (long)CIVal.getSExtValue(); in PPCEmitCmp()
859 if ((IsZExt && isUInt<16>(Imm)) || (!IsZExt && isInt<16>(Imm))) in PPCEmitCmp()
909 CmpOpc = IsZExt ? PPC::CMPLW : PPC::CMPW; in PPCEmitCmp()
911 CmpOpc = IsZExt ? PPC::CMPLWI : PPC::CMPWI; in PPCEmitCmp()
[all …]
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| /external/llvm/include/llvm/CodeGen/ |
| D | MachineFrameInfo.h | 443 void setObjectZExt(int ObjectIdx, bool IsZExt) { in setObjectZExt() argument
446 Objects[ObjectIdx+NumFixedObjects].isZExt = IsZExt; in setObjectZExt()
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| D | FastISel.h | 37 bool IsZExt : 1; member
49 : Val(nullptr), Ty(nullptr), IsSExt(false), IsZExt(false), in ArgListEntry()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsFastISel.cpp | 142 bool IsZExt);
1505 bool IsZExt = Outs[0].Flags.isZExt(); in selectRet() local
1506 SrcReg = emitIntExt(RVVT, SrcReg, DestVT, IsZExt); in selectRet()
1641 unsigned DestReg, bool IsZExt) { in emitIntExt() argument
1649 if (IsZExt) in emitIntExt()
1728 bool IsZExt = Opcode == Instruction::LShr; in selectShift() local
1729 if (!emitIntExt(Op0MVT, Op0Reg, MVT::i32, TempReg, IsZExt)) in selectShift()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsFastISel.cpp | 188 bool IsZExt);
1729 bool IsZExt = Outs[0].Flags.isZExt(); in selectRet() local
1730 SrcReg = emitIntExt(RVVT, SrcReg, DestVT, IsZExt); in selectRet()
1867 unsigned DestReg, bool IsZExt) { in emitIntExt() argument
1875 if (IsZExt) in emitIntExt()
1954 bool IsZExt = Opcode == Instruction::LShr; in selectShift() local
1955 if (!emitIntExt(Op0MVT, Op0Reg, MVT::i32, TempReg, IsZExt)) in selectShift()
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| /external/llvm/lib/Analysis/ |
| D | BasicAliasAnalysis.cpp | 1192 bool IsZExt = DecompGEP1.VarIndices[i].ZExtBits > 0 || isa<ZExtInst>(V); in aliasGEP() local
1193 SignKnownZero |= IsZExt; in aliasGEP()
1194 SignKnownOne &= !IsZExt; in aliasGEP()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Analysis/ |
| D | BasicAliasAnalysis.cpp | 1394 bool IsZExt = DecompGEP1.VarIndices[i].ZExtBits > 0 || isa<ZExtInst>(V); in aliasGEP() local
1395 SignKnownZero |= IsZExt; in aliasGEP()
1396 SignKnownOne &= !IsZExt; in aliasGEP()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeDAG.cpp | 1973 Entry.IsZExt = !TLI.shouldSignExtendTypeInLibCall(ArgVT, isSigned); in ExpandLibCall()
2034 Entry.IsZExt = !isSigned; in ExpandLibCall()
2072 Entry.IsZExt = !isSigned; in ExpandChainLibCall()
2165 Entry.IsZExt = !isSigned; in ExpandDivRemLibCall()
2174 Entry.IsZExt = !isSigned; in ExpandDivRemLibCall()
2259 Entry.IsZExt = false; in ExpandSinCosLibCall()
2267 Entry.IsZExt = false; in ExpandSinCosLibCall()
2275 Entry.IsZExt = false; in ExpandSinCosLibCall()
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| D | LegalizeTypes.cpp | 1042 Entry.IsZExt = !isSigned; in ExpandChainLibCall()
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| D | FastISel.cpp | 1171 if (Arg.IsZExt) in lowerCallTo()
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| D | LegalizeIntegerTypes.cpp | 2759 Entry.IsZExt = false; in ExpandIntRes_XMULO()
2767 Entry.IsZExt = false; in ExpandIntRes_XMULO()
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| D | TargetLowering.cpp | 104 IsZExt = CS->paramHasAttr(ArgIdx, Attribute::ZExt); in setAttributes()
131 Entry.IsZExt = !shouldSignExtendTypeInLibCall(Op.getValueType(), isSigned); in makeLibCall()
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| D | SelectionDAGBuilder.cpp | 8367 Entry.IsZExt = false; in LowerCallTo()
8445 if (Args[i].IsZExt) in LowerCallTo()
8507 else if (Args[i].IsZExt) in LowerCallTo()
8528 CLI.RetZExt == Args[i].IsZExt)) in LowerCallTo()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | FastISel.cpp | 84 IsZExt = CS->paramHasAttr(AttrIdx, Attribute::ZExt); in setAttributes()
954 if (Arg.IsZExt) in lowerCallTo()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AVR/ |
| D | AVRISelLowering.cpp | 368 Entry.IsZExt = !IsSigned; in LowerDivRem()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 7801 Entry.IsZExt = false; in LowerFSINCOS()
7811 Entry.IsZExt = false; in LowerFSINCOS()
8028 Entry.IsZExt = true; in LowerFPOWI()
8033 Entry.IsZExt = true; in LowerFPOWI()
13938 Entry.IsZExt = !isSigned; in getDivRemArgList()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 22871 Entry.IsZExt = false; in LowerWin64_i128OP()
24917 Entry.IsZExt = false; in LowerFSINCOS()
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