| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMSubtarget.cpp | 60 , PostRAScheduler(false) in ARMSubtarget()
122 PostRAScheduler = true; in ARMSubtarget()
218 return PostRAScheduler && OptLevel >= CodeGenOpt::Default; in enablePostRAScheduler()
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| D | ARMSubtarget.h | 87 bool PostRAScheduler; variable
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| /external/llvm/lib/CodeGen/ |
| D | PostRASchedulerList.cpp | 80 class PostRAScheduler : public MachineFunctionPass { class
86 PostRAScheduler() : MachineFunctionPass(ID) {} in PostRAScheduler() function in __anonccb3ce330111::PostRAScheduler
112 char PostRAScheduler::ID = 0;
201 char &llvm::PostRASchedulerID = PostRAScheduler::ID;
203 INITIALIZE_PASS(PostRAScheduler, "post-RA-sched",
266 bool PostRAScheduler::enablePostRAScheduler( in enablePostRAScheduler()
282 bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) { in runOnMachineFunction()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | PostRASchedulerList.cpp | 80 class PostRAScheduler : public MachineFunctionPass { class
86 PostRAScheduler() : MachineFunctionPass(ID) {} in PostRAScheduler() function in __anon572c728b0111::PostRAScheduler
112 char PostRAScheduler::ID = 0;
201 char &llvm::PostRASchedulerID = PostRAScheduler::ID;
203 INITIALIZE_PASS(PostRAScheduler, DEBUG_TYPE,
266 bool PostRAScheduler::enablePostRAScheduler( in enablePostRAScheduler()
282 bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) { in runOnMachineFunction()
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| D | TargetSubtargetInfo.cpp | 63 return getSchedModel().PostRAScheduler; in enablePostRAScheduler()
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | PostRASchedulerList.cpp | 81 class PostRAScheduler : public MachineFunctionPass { class
89 PostRAScheduler(CodeGenOpt::Level ol) : in PostRAScheduler() function in __anoneee000df0111::PostRAScheduler
108 char PostRAScheduler::ID = 0;
207 bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) { in runOnMachineFunction()
711 return new PostRAScheduler(OptLevel); in createPostRAScheduler()
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| /external/llvm/lib/Target/ |
| D | TargetSubtargetInfo.cpp | 49 return getSchedModel().PostRAScheduler; in enablePostRAScheduler()
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| /external/llvm/include/llvm/MC/ |
| D | MCSchedule.h | 183 bool PostRAScheduler; // default value is false member
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| /external/llvm/lib/Target/Lanai/ |
| D | LanaiSchedule.td | 46 let PostRAScheduler = 0;
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/ |
| D | LanaiSchedule.td | 46 let PostRAScheduler = 0;
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/MC/ |
| D | MCSchedule.h | 303 bool PostRAScheduler; // default value is false member
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| /external/llvm/lib/Target/X86/ |
| D | X86Schedule.td | 639 // and disables PostRAScheduler.
645 let PostRAScheduler = 0;
651 // Define a model with the PostRAScheduler enabled.
653 let PostRAScheduler = 1;
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| D | X86ScheduleSLM.td | 22 let PostRAScheduler = 1;
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| D | X86ScheduleBtVer2.td | 24 let PostRAScheduler = 1;
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| D | X86ScheduleAtom.td | 546 let PostRAScheduler = 1;
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| D | X86.td | 282 // Enable the PostRAScheduler for SSE2 and SSE3 class cpus.
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SISchedule.td | 51 let PostRAScheduler = 1;
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | SISchedule.td | 55 let PostRAScheduler = 1;
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86Schedule.td | 646 // and disables PostRAScheduler.
652 let PostRAScheduler = 0;
658 // Define a model with the PostRAScheduler enabled.
660 let PostRAScheduler = 1;
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| D | X86ScheduleSLM.td | 22 let PostRAScheduler = 1;
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| D | X86ScheduleBtVer2.td | 24 let PostRAScheduler = 1;
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| /external/llvm/utils/TableGen/ |
| D | SubtargetEmitter.cpp | 1169 bool PostRAScheduler = in EmitProcessorModels() local
1172 OS << " " << (PostRAScheduler ? "true" : "false") << ", // " in EmitProcessorModels()
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| /external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/ |
| D | SubtargetEmitter.cpp | 1367 bool PostRAScheduler = in EmitProcessorModels() local
1370 OS << " " << (PostRAScheduler ? "true" : "false") << ", // " in EmitProcessorModels()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64SchedThunderX.td | 26 let PostRAScheduler = 1; // Use PostRA scheduler.
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| /external/llvm/include/llvm/Target/ |
| D | TargetSchedule.td | 91 bit PostRAScheduler = 0; // Enable Post RegAlloc Scheduler pass.
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