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Searched refs:SUBREG_TO_REG (Results 1 – 25 of 130) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/GlobalISel/
Dselect-cmp.mir103 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETEr]], %subreg.sub_8bit
104 ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def $eflags
134 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETEr]], %subreg.sub_8bit
135 ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def $eflags
165 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETEr]], %subreg.sub_8bit
166 ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def $eflags
196 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETEr]], %subreg.sub_8bit
197 ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def $eflags
227 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETNEr]], %subreg.sub_8bit
228 ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def $eflags
[all …]
Dselect-ext-x86-64.mir41 ; ALL: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.sub_8bit
42 ; ALL: [[AND64ri8_:%[0-9]+]]:gr64 = AND64ri8 [[SUBREG_TO_REG]], 1, implicit-def $eflags
114 ; ALL: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.sub_8bit
115 ; ALL: $rax = COPY [[SUBREG_TO_REG]]
139 ; ALL: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.sub_8bit
140 ; ALL: $rax = COPY [[SUBREG_TO_REG]]
164 ; ALL: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.sub_16bit
165 ; ALL: $rax = COPY [[SUBREG_TO_REG]]
189 ; ALL: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.sub_32bit
190 ; ALL: $rax = COPY [[SUBREG_TO_REG]]
Dx86_64-select-zext.mir168 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.sub_32bit
169 ; CHECK: [[AND64ri8_:%[0-9]+]]:gr64 = AND64ri8 [[SUBREG_TO_REG]], 1, implicit-def $eflags
261 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.sub_32bit
262 ; CHECK: [[AND64ri32_:%[0-9]+]]:gr64 = AND64ri32 [[SUBREG_TO_REG]], 255, implicit-def $eflags
323 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.sub_32bit
324 ; CHECK: [[AND64ri32_:%[0-9]+]]:gr64 = AND64ri32 [[SUBREG_TO_REG]], 65535, implicit-def $eflags
351 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.sub_32bit
352 ; CHECK: $rax = COPY [[SUBREG_TO_REG]]
Dselect-ext.mir108 # ALL_NEXT: %3:gr16 = SUBREG_TO_REG 0, %1, %subreg.sub_8bit
147 # ALL_NEXT: %3:gr32 = SUBREG_TO_REG 0, %1, %subreg.sub_8bit
322 # ALL-NEXT: %2:gr16 = SUBREG_TO_REG 0, %1, %subreg.sub_8bit
357 # ALL-NEXT: %2:gr32 = SUBREG_TO_REG 0, %1, %subreg.sub_8bit
392 # ALL-NEXT: %2:gr16 = SUBREG_TO_REG 0, %1, %subreg.sub_8bit
456 # ALL-NEXT: %2:gr32 = SUBREG_TO_REG 0, %1, %subreg.sub_16bit
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/GlobalISel/
Dselect-int-ext.mir36 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[COPY]], %subreg.sub_32
37 ; CHECK: $x0 = COPY [[SUBREG_TO_REG]]
81 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.sub_32
82 ; CHECK: [[UBFMXri:%[0-9]+]]:gpr64 = UBFMXri [[SUBREG_TO_REG]], 0, 31
175 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.sub_32
176 ; CHECK: [[SBFMXri:%[0-9]+]]:gpr64 = SBFMXri [[SUBREG_TO_REG]], 0, 31
Dselect-insert-extract.mir16 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.sub_32
17 ; CHECK: [[BFMXri:%[0-9]+]]:gpr64 = BFMXri [[DEF]], [[SUBREG_TO_REG]], 0, 31
18 ; CHECK: [[SUBREG_TO_REG1:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.sub_32
Dfp16-copy-gpr.mir51 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[COPY]], %subreg.hsub
52 ; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY [[SUBREG_TO_REG]]
54 ; CHECK: [[SUBREG_TO_REG1:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[COPY1]], %subreg.hsub
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
Dpeephole.mir7 # are no SUBREG_TO_REG users.
33 ; CHECK: %6:gr64 = SUBREG_TO_REG %5, 0
38 %6 = SUBREG_TO_REG %5, 0, %subreg.sub_32bit
DMachineSink-SubReg.ll1 ; PR28852: Check machine code sinking is not stopped by SUBREG_TO_REG.
/external/llvm/lib/Target/X86/
DX86InstrExtension.td166 // 64-bit zero-extension patterns use SUBREG_TO_REG and an operation writing a
169 (SUBREG_TO_REG (i64 0), (MOVZX32rr8 GR8:$src), sub_32bit)>;
171 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>;
174 (SUBREG_TO_REG (i64 0), (MOVZX32rr16 GR16:$src), sub_32bit)>;
176 (SUBREG_TO_REG (i64 0), (MOVZX32rm16 addr:$src), sub_32bit)>;
179 // SUBREG_TO_REG to utilize implicit zero-extension, however this isn't possible
184 (SUBREG_TO_REG (i64 0), (MOV32rr GR32:$src), sub_32bit)>;
186 (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src), sub_32bit)>;
DX86InstrCompiler.td270 def : Pat<(i64 0), (SUBREG_TO_REG (i64 0), (MOV32r0), sub_32bit)> {
302 // use MOV32ri with a SUBREG_TO_REG to represent the zero-extension, however
315 (SUBREG_TO_REG (i64 0), (MOV32ri64 mov64imm32:$src), sub_32bit)>;
1247 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>;
1264 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>;
1266 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>;
1268 (SUBREG_TO_REG (i64 0), (MOVZX32rm16 addr:$src), sub_32bit)>;
1270 (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src), sub_32bit)>;
1283 (SUBREG_TO_REG (i64 0), (MOVZX32rr8 GR8 :$src), sub_32bit)>;
1285 (SUBREG_TO_REG (i64 0), (MOVZX32rr16 GR16 :$src), sub_32bit)>;
[all …]
DX86InstrAVX512.td1338 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1339 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1345 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1346 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1549 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1550 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1554 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1555 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1808 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1809 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
[all …]
/external/llvm/lib/Target/AArch64/
DAArch64InstrAtomics.td222 (SUBREG_TO_REG (i64 0), (LDXRB GPR64sp:$addr), sub_32)>;
224 (SUBREG_TO_REG (i64 0), (LDXRH GPR64sp:$addr), sub_32)>;
226 (SUBREG_TO_REG (i64 0), (LDXRW GPR64sp:$addr), sub_32)>;
230 (SUBREG_TO_REG (i64 0), (LDXRB GPR64sp:$addr), sub_32)>;
232 (SUBREG_TO_REG (i64 0), (LDXRH GPR64sp:$addr), sub_32)>;
234 (SUBREG_TO_REG (i64 0), (LDXRW GPR64sp:$addr), sub_32)>;
255 (SUBREG_TO_REG (i64 0), (LDAXRB GPR64sp:$addr), sub_32)>;
257 (SUBREG_TO_REG (i64 0), (LDAXRH GPR64sp:$addr), sub_32)>;
259 (SUBREG_TO_REG (i64 0), (LDAXRW GPR64sp:$addr), sub_32)>;
263 (SUBREG_TO_REG (i64 0), (LDAXRB GPR64sp:$addr), sub_32)>;
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86InstrExtension.td184 // 64-bit zero-extension patterns use SUBREG_TO_REG and an operation writing a
187 (SUBREG_TO_REG (i64 0), (MOVZX32rr8 GR8:$src), sub_32bit)>;
189 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>;
192 (SUBREG_TO_REG (i64 0), (MOVZX32rr16 GR16:$src), sub_32bit)>;
194 (SUBREG_TO_REG (i64 0), (MOVZX32rm16 addr:$src), sub_32bit)>;
197 // SUBREG_TO_REG to utilize implicit zero-extension, however this isn't possible
202 (SUBREG_TO_REG (i64 0), (MOV32rr GR32:$src), sub_32bit)>;
204 (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src), sub_32bit)>;
DX86InstrCompiler.td285 def : Pat<(i64 0), (SUBREG_TO_REG (i64 0), (MOV32r0), sub_32bit)>;
318 // use MOV32ri with a SUBREG_TO_REG to represent the zero-extension, however
331 (SUBREG_TO_REG (i64 0), (MOV32ri64 mov64imm32:$src), sub_32bit)>;
1232 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>;
1249 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>;
1251 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>;
1253 (SUBREG_TO_REG (i64 0), (MOVZX32rm16 addr:$src), sub_32bit)>;
1255 (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src), sub_32bit)>;
1268 (SUBREG_TO_REG (i64 0), (MOVZX32rr8 GR8 :$src), sub_32bit)>;
1270 (SUBREG_TO_REG (i64 0), (MOVZX32rr16 GR16 :$src), sub_32bit)>;
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64InstrAtomics.td223 (SUBREG_TO_REG (i64 0), (LDXRB GPR64sp:$addr), sub_32)>;
225 (SUBREG_TO_REG (i64 0), (LDXRH GPR64sp:$addr), sub_32)>;
227 (SUBREG_TO_REG (i64 0), (LDXRW GPR64sp:$addr), sub_32)>;
231 (SUBREG_TO_REG (i64 0), (LDXRB GPR64sp:$addr), sub_32)>;
233 (SUBREG_TO_REG (i64 0), (LDXRH GPR64sp:$addr), sub_32)>;
235 (SUBREG_TO_REG (i64 0), (LDXRW GPR64sp:$addr), sub_32)>;
256 (SUBREG_TO_REG (i64 0), (LDAXRB GPR64sp:$addr), sub_32)>;
258 (SUBREG_TO_REG (i64 0), (LDAXRH GPR64sp:$addr), sub_32)>;
260 (SUBREG_TO_REG (i64 0), (LDAXRW GPR64sp:$addr), sub_32)>;
264 (SUBREG_TO_REG (i64 0), (LDAXRB GPR64sp:$addr), sub_32)>;
[all …]
/external/swiftshader/third_party/LLVM/include/llvm/Target/
DTargetOpcodes.h58 SUBREG_TO_REG = 9, enumerator
/external/llvm/lib/Target/Mips/
DMips64r6InstrInfo.td178 (SUBREG_TO_REG (i64 0), (SLTi64 i64:$cond, (Plus1 imm:$imm)),
181 (SUBREG_TO_REG (i64 0), (SLTi64 i64:$cond, (Plus1 imm:$imm)),
187 (SUBREG_TO_REG (i64 0), (SLTiu64 i64:$cond, (Plus1 imm:$imm)),
190 (SUBREG_TO_REG (i64 0), (SLTiu64 i64:$cond, (Plus1 imm:$imm)),
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMips64r6InstrInfo.td229 (SUBREG_TO_REG (i64 0), (SLTi64 i64:$cond, (Plus1 imm:$imm)),
232 (SUBREG_TO_REG (i64 0), (SLTi64 i64:$cond, (Plus1 imm:$imm)),
238 (SUBREG_TO_REG (i64 0), (SLTiu64 i64:$cond, (Plus1 imm:$imm)),
241 (SUBREG_TO_REG (i64 0), (SLTiu64 i64:$cond, (Plus1 imm:$imm)),
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/BPF/
DBPFInstrInfo.td712 (SUBREG_TO_REG (i64 0), (LDB32 ADDRri:$src), sub_32)>;
714 (SUBREG_TO_REG (i64 0), (LDH32 ADDRri:$src), sub_32)>;
716 (SUBREG_TO_REG (i64 0), (LDW32 ADDRri:$src), sub_32)>;
718 (SUBREG_TO_REG (i64 0), (LDB32 ADDRri:$src), sub_32)>;
720 (SUBREG_TO_REG (i64 0), (LDH32 ADDRri:$src), sub_32)>;
722 (SUBREG_TO_REG (i64 0), (LDW32 ADDRri:$src), sub_32)>;
DBPFMIPeephole.cpp170 BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(BPF::SUBREG_TO_REG), DstReg) in eliminateZExtSeq()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCVSXCopy.cpp112 TII->get(TargetOpcode::SUBREG_TO_REG), NewVReg) in processBlock()
/external/llvm/lib/Target/PowerPC/
DPPCVSXCopy.cpp117 TII->get(TargetOpcode::SUBREG_TO_REG), NewVReg) in processBlock()
/external/llvm/lib/CodeGen/
DExpandPostRAPseudos.cpp211 case TargetOpcode::SUBREG_TO_REG: in runOnMachineFunction()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DExpandPostRAPseudos.cpp209 case TargetOpcode::SUBREG_TO_REG: in runOnMachineFunction()

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