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Searched refs:ccm (Results 1 – 25 of 111) sorted by relevance

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/external/u-boot/arch/arm/mach-sunxi/
Dclock_sun9i.c23 struct sunxi_ccm_reg * const ccm = in clock_init_safe() local
38 C0_CFG_APB0_CLK_DIV_RATIO(2), &ccm->c0_cfg); in clock_init_safe()
42 &ccm->ahb0_cfg); in clock_init_safe()
45 &ccm->ahb1_cfg); in clock_init_safe()
48 &ccm->ahb2_cfg); in clock_init_safe()
51 &ccm->apb0_cfg); in clock_init_safe()
55 &ccm->gtbus_cfg); in clock_init_safe()
58 &ccm->cci400_cfg); in clock_init_safe()
61 setbits_le32(&ccm->ahb_reset1_cfg, (1 << 24)); in clock_init_safe()
62 setbits_le32(&ccm->apb1_gate, (1 << 24)); in clock_init_safe()
[all …]
Dclock_sun6i.c21 struct sunxi_ccm_reg * const ccm = in clock_init_safe() local
39 writel(GENMASK(12, 0), &ccm->pll_lock_ctrl); in clock_init_safe()
44 writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg); in clock_init_safe()
45 while (!(readl(&ccm->pll6_cfg) & CCM_PLL6_CTRL_LOCK)) in clock_init_safe()
48 writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div); in clock_init_safe()
50 writel(MBUS_CLK_DEFAULT, &ccm->mbus0_clk_cfg); in clock_init_safe()
52 writel(MBUS_CLK_DEFAULT, &ccm->mbus1_clk_cfg); in clock_init_safe()
55 setbits_le32(&ccm->sata_pll_cfg, CCM_SATA_PLL_DEFAULT); in clock_init_safe()
56 setbits_le32(&ccm->ahb_reset0_cfg, 0x1 << AHB_GATE_OFFSET_SATA); in clock_init_safe()
57 setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_SATA); in clock_init_safe()
[all …]
Dclock_sun8i_a83t.c21 struct sunxi_ccm_reg * const ccm = in clock_init_safe() local
26 writel(PLL8_CFG_DEFAULT, &ccm->pll8_cfg); in clock_init_safe()
27 writel(readl(&ccm->pll8_cfg) | (0x1 << 31), &ccm->pll8_cfg); in clock_init_safe()
28 while (!(readl(&ccm->pll_stable_status) & (1 << 8))) {} in clock_init_safe()
31 writel(0x0, &ccm->cci400_cfg); in clock_init_safe()
33 writel(CCM_CCI400_CLK_SEL_HSIC, &ccm->cci400_cfg); in clock_init_safe()
37 clrsetbits_le32(&ccm->ahb1_apb1_div, AHB1_CLK_SRC_MASK, in clock_init_safe()
39 writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg); in clock_init_safe()
40 while (!(readl(&ccm->pll_stable_status) & (1 << 6))) {} in clock_init_safe()
42 writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div); in clock_init_safe()
[all …]
Dclock_sun4i.c21 struct sunxi_ccm_reg * const ccm = in clock_init_safe() local
29 &ccm->cpu_ahb_apb0_cfg); in clock_init_safe()
30 writel(PLL1_CFG_DEFAULT, &ccm->pll1_cfg); in clock_init_safe()
36 &ccm->cpu_ahb_apb0_cfg); in clock_init_safe()
38 setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_DMA); in clock_init_safe()
40 writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg); in clock_init_safe()
42 setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_SATA); in clock_init_safe()
43 setbits_le32(&ccm->pll6_cfg, 0x1 << CCM_PLL6_CTRL_SATA_EN_SHIFT); in clock_init_safe()
50 struct sunxi_ccm_reg *const ccm = in clock_init_uart() local
57 &ccm->apb1_clk_div_cfg); in clock_init_uart()
[all …]
/external/u-boot/arch/arm/cpu/arm1136/mx35/
Dgeneric.c133 struct ccm_regs *ccm = in get_mcu_main_clk() local
135 arm_div = get_arm_div(readl(&ccm->pdr0), &fi, &fd); in get_mcu_main_clk()
136 fi *= decode_pll(readl(&ccm->mpctl), MXC_HCLK); in get_mcu_main_clk()
143 struct ccm_regs *ccm = in get_ipg_clk() local
145 u32 pdr0 = readl(&ccm->pdr0); in get_ipg_clk()
153 struct ccm_regs *ccm = in get_ipg_per_clk() local
155 u32 pdr0 = readl(&ccm->pdr0); in get_ipg_per_clk()
156 u32 pdr4 = readl(&ccm->pdr4); in get_ipg_per_clk()
174 struct ccm_regs *ccm = in imx_get_uartclk() local
176 u32 pdr4 = readl(&ccm->pdr4); in imx_get_uartclk()
[all …]
/external/u-boot/arch/arm/cpu/arm926ejs/mx25/
Dgeneric.c54 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; in imx_get_mpllclk() local
57 return imx_decode_pll(readl(&ccm->mpctl), fref); in imx_get_mpllclk()
62 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; in imx_get_upllclk() local
65 return imx_decode_pll(readl(&ccm->upctl), fref); in imx_get_upllclk()
70 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; in imx_get_armclk() local
71 ulong cctl = readl(&ccm->cctl); in imx_get_armclk()
86 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; in imx_get_ahbclk() local
87 ulong cctl = readl(&ccm->cctl); in imx_get_ahbclk()
104 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; in imx_get_perclk() local
105 ulong fref = readl(&ccm->mcr) & (1 << clk) ? imx_get_upllclk() : in imx_get_perclk()
[all …]
/external/u-boot/board/aristainetos/
Daristainetos-v2.c406 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in enable_lvds() local
411 reg = readl(&ccm->analog_pll_video); in enable_lvds()
413 writel(reg, &ccm->analog_pll_video); in enable_lvds()
420 writel(reg, &ccm->analog_pll_video); in enable_lvds()
423 &ccm->analog_pll_video_num); in enable_lvds()
425 &ccm->analog_pll_video_denom); in enable_lvds()
428 writel(reg, &ccm->analog_pll_video); in enable_lvds()
431 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK) in enable_lvds()
436 reg = readl(&ccm->analog_pll_video); in enable_lvds()
439 writel(reg, &ccm->analog_pll_video); in enable_lvds()
[all …]
/external/u-boot/board/toradex/colibri_vf/
Dcolibri_vf.c385 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR; in clock_init() local
389 clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK, in clock_init()
392 setbits_le32(&ccm->ccgr0, CCM_CCGR0_DSPI1_CTRL_MASK); in clock_init()
394 clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK, in clock_init()
396 clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK, in clock_init()
400 clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK, in clock_init()
402 clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK, in clock_init()
405 clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK, in clock_init()
407 clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK, in clock_init()
409 clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK, in clock_init()
[all …]
/external/u-boot/board/freescale/vf610twr/
Dvf610twr.c270 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR; in clock_init() local
273 clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK, in clock_init()
275 clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK, in clock_init()
277 clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK, in clock_init()
282 clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK, in clock_init()
284 clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK, in clock_init()
287 clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK, in clock_init()
289 clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK, in clock_init()
291 clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK, in clock_init()
293 clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK, in clock_init()
[all …]
/external/u-boot/board/CarMediaLab/flea3/
Dflea3.c134 struct ccm_regs *ccm = in board_early_init_f() local
142 writel(CCM_CCMR_CONFIG, &ccm->ccmr); in board_early_init_f()
144 writel(CCM_MPLL_532_HZ, &ccm->mpctl); in board_early_init_f()
145 writel(CCM_PPLL_300_HZ, &ccm->ppctl); in board_early_init_f()
148 writel(0x00001000, &ccm->pdr0); in board_early_init_f()
154 writel(readl(&ccm->cgr0) | in board_early_init_f()
158 &ccm->cgr0); in board_early_init_f()
160 writel(readl(&ccm->cgr1) | in board_early_init_f()
168 &ccm->cgr1); in board_early_init_f()
171 __raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr); in board_early_init_f()
/external/u-boot/board/ccv/xpress/
Dspl.c81 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in ccgr_init() local
83 writel(0xFFFFFFFF, &ccm->CCGR0); in ccgr_init()
84 writel(0xFFFFFFFF, &ccm->CCGR1); in ccgr_init()
85 writel(0xFFFFFFFF, &ccm->CCGR2); in ccgr_init()
86 writel(0xFFFFFFFF, &ccm->CCGR3); in ccgr_init()
87 writel(0xFFFFFFFF, &ccm->CCGR4); in ccgr_init()
88 writel(0xFFFFFFFF, &ccm->CCGR5); in ccgr_init()
89 writel(0xFFFFFFFF, &ccm->CCGR6); in ccgr_init()
90 writel(0xFFFFFFFF, &ccm->CCGR7); in ccgr_init()
/external/u-boot/arch/m68k/cpu/mcf5445x/
Dspeed.c31 ccm_t *ccm = (ccm_t *)MMAP_CCM; in clock_enter_limp() local
45 clrsetbits_be16(&ccm->cdr, 0x0f00, CCM_CDR_LPDIV(i)); in clock_enter_limp()
49 setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP); in clock_enter_limp()
58 ccm_t *ccm = (ccm_t *)MMAP_CCM; in clock_exit_limp() local
62 clrbits_be16(&ccm->misccr, CCM_MISCCR_LIMP); in clock_exit_limp()
72 ccm_t *ccm = (ccm_t *)MMAP_CCM; in setup_5441x_clocks() local
76 bootmod_ccr = (in_be16(&ccm->ccr) & CCM_CCR_BOOTMOD) >> 14; in setup_5441x_clocks()
104 setbits_be16(&ccm->misccr2, 0x02); in setup_5441x_clocks()
117 if (in_be16(&ccm->misccr2) & 2) /* fsys/4 */ in setup_5441x_clocks()
129 ccm_t *ccm = (ccm_t *)MMAP_CCM; in setup_5445x_clocks() local
[all …]
/external/u-boot/arch/arm/cpu/armv7/vf610/
Dgeneric.c26 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR; in enable_ocotp_clk() local
29 reg = readl(&ccm->ccgr6); in enable_ocotp_clk()
34 writel(reg, &ccm->ccgr6); in enable_ocotp_clk()
40 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR; in get_mcu_main_clk() local
45 ccm_ccsr = readl(&ccm->ccsr); in get_mcu_main_clk()
49 ccm_cacrr = readl(&ccm->cacrr); in get_mcu_main_clk()
104 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR; in get_bus_clk() local
107 ccm_cacrr = readl(&ccm->cacrr); in get_bus_clk()
118 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR; in get_ipg_clk() local
121 ccm_cacrr = readl(&ccm->cacrr); in get_ipg_clk()
[all …]
/external/u-boot/board/barco/platinum/
Dplatinum.h66 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in ccgr_init() local
68 writel(0x00C03F3F, &ccm->CCGR0); in ccgr_init()
69 writel(0x0030FC03, &ccm->CCGR1); in ccgr_init()
70 writel(0x0FFFC000, &ccm->CCGR2); in ccgr_init()
71 writel(0x3FF00000, &ccm->CCGR3); in ccgr_init()
72 writel(0xFFFFF300, &ccm->CCGR4); /* enable NAND/GPMI/BCH clks */ in ccgr_init()
73 writel(0x0F0000C3, &ccm->CCGR5); in ccgr_init()
74 writel(0x000003FF, &ccm->CCGR6); in ccgr_init()
/external/u-boot/board/solidrun/mx6cuboxi/
Dmx6cuboxi.c293 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in setup_display() local
301 setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN); in setup_display()
303 reg = readl(&ccm->analog_pll_video); in setup_display()
308 writel(reg, &ccm->analog_pll_video); in setup_display()
310 writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num); in setup_display()
311 writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom); in setup_display()
314 writel(reg, &ccm->analog_pll_video); in setup_display()
317 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK) in setup_display()
324 reg = readl(&ccm->analog_pll_video); in setup_display()
327 writel(reg, &ccm->analog_pll_video); in setup_display()
[all …]
/external/u-boot/board/engicam/common/
Dspl.c368 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in ccgr_init() local
371 writel(0x00003F3F, &ccm->CCGR0); in ccgr_init()
372 writel(0x0030FC00, &ccm->CCGR1); in ccgr_init()
373 writel(0x000FC000, &ccm->CCGR2); in ccgr_init()
374 writel(0x3F300000, &ccm->CCGR3); in ccgr_init()
375 writel(0xFF00F300, &ccm->CCGR4); in ccgr_init()
376 writel(0x0F0000C3, &ccm->CCGR5); in ccgr_init()
377 writel(0x000003CC, &ccm->CCGR6); in ccgr_init()
379 writel(0x00c03f3f, &ccm->CCGR0); in ccgr_init()
380 writel(0xfcffff00, &ccm->CCGR1); in ccgr_init()
[all …]
/external/u-boot/board/tbs/tbs2910/
Dtbs2910.c304 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in setup_display() local
312 reg = readl(&ccm->analog_pll_video); in setup_display()
314 writel(reg, &ccm->analog_pll_video); in setup_display()
320 writel(reg, &ccm->analog_pll_video); in setup_display()
322 writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num); in setup_display()
323 writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom); in setup_display()
326 writel(reg, &ccm->analog_pll_video); in setup_display()
329 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK) in setup_display()
334 reg = readl(&ccm->analog_pll_video); in setup_display()
337 writel(reg, &ccm->analog_pll_video); in setup_display()
[all …]
/external/u-boot/arch/arm/mach-imx/mx6/
Dlitesom.c149 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in ccgr_init() local
151 writel(0xFFFFFFFF, &ccm->CCGR0); in ccgr_init()
152 writel(0xFFFFFFFF, &ccm->CCGR1); in ccgr_init()
153 writel(0xFFFFFFFF, &ccm->CCGR2); in ccgr_init()
154 writel(0xFFFFFFFF, &ccm->CCGR3); in ccgr_init()
155 writel(0xFFFFFFFF, &ccm->CCGR4); in ccgr_init()
156 writel(0xFFFFFFFF, &ccm->CCGR5); in ccgr_init()
157 writel(0xFFFFFFFF, &ccm->CCGR6); in ccgr_init()
158 writel(0xFFFFFFFF, &ccm->CCGR7); in ccgr_init()
Dopos6ul.c222 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in ccgr_init() local
224 writel(0xFFFFFFFF, &ccm->CCGR0); in ccgr_init()
225 writel(0xFFFFFFFF, &ccm->CCGR1); in ccgr_init()
226 writel(0xFFFFFFFF, &ccm->CCGR2); in ccgr_init()
227 writel(0xFFFFFFFF, &ccm->CCGR3); in ccgr_init()
228 writel(0xFFFFFFFF, &ccm->CCGR4); in ccgr_init()
229 writel(0xFFFFFFFF, &ccm->CCGR5); in ccgr_init()
230 writel(0xFFFFFFFF, &ccm->CCGR6); in ccgr_init()
231 writel(0xFFFFFFFF, &ccm->CCGR7); in ccgr_init()
/external/u-boot/arch/m68k/cpu/mcf532x/
Dspeed.c52 ccm_t *ccm = (ccm_t *)(MMAP_CCM); in get_sys_clock() local
57 if (in_be16(&ccm->misccr) & CCM_MISCCR_LIMP) { in get_sys_clock()
58 divider = in_be16(&ccm->cdr) & CCM_CDR_LPDIV(0xF); in get_sys_clock()
90 ccm_t *ccm = (ccm_t *)(MMAP_CCM); in clock_limp() local
100 temp = (in_be16(&ccm->cdr) & CCM_CDR_SSIDIV(0xFF)); in clock_limp()
103 out_be16(&ccm->cdr, CCM_CDR_LPDIV(div) | CCM_CDR_SSIDIV(temp)); in clock_limp()
105 setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP); in clock_limp()
113 ccm_t *ccm = (ccm_t *)(MMAP_CCM); in clock_exit_limp() local
117 clrbits_be16(&ccm->misccr, CCM_MISCCR_LIMP); in clock_exit_limp()
120 while (!(in_be16(&ccm->misccr) & CCM_MISCCR_PLL_LOCK)) in clock_exit_limp()
/external/u-boot/drivers/video/sunxi/
Dsunxi_display.c91 struct sunxi_ccm_reg * const ccm = in sunxi_hdmi_hpd_detect() local
101 clrsetbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_PLL_MASK, in sunxi_hdmi_hpd_detect()
106 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI); in sunxi_hdmi_hpd_detect()
108 setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI); in sunxi_hdmi_hpd_detect()
111 setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE); in sunxi_hdmi_hpd_detect()
126 struct sunxi_ccm_reg * const ccm = in sunxi_hdmi_shutdown() local
132 clrbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE); in sunxi_hdmi_shutdown()
133 clrbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI); in sunxi_hdmi_shutdown()
135 clrbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI); in sunxi_hdmi_shutdown()
214 struct sunxi_ccm_reg * const ccm = in sunxi_hdmi_edid_get_mode() local
[all …]
Dsunxi_dw_hdmi.c245 struct sunxi_ccm_reg * const ccm = in sunxi_dw_hdmi_lcdc_init() local
254 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD0); in sunxi_dw_hdmi_lcdc_init()
257 setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_LCD0); in sunxi_dw_hdmi_lcdc_init()
259 &ccm->lcd0_clk_cfg); in sunxi_dw_hdmi_lcdc_init()
264 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD1); in sunxi_dw_hdmi_lcdc_init()
267 setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_LCD1); in sunxi_dw_hdmi_lcdc_init()
269 &ccm->lcd1_clk_cfg); in sunxi_dw_hdmi_lcdc_init()
329 struct sunxi_ccm_reg * const ccm = in sunxi_dw_hdmi_probe() local
337 clrsetbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_PLL_MASK, in sunxi_dw_hdmi_probe()
341 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI); in sunxi_dw_hdmi_probe()
[all …]
/external/u-boot/board/bticino/mamoj/
Dspl.c140 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in ccgr_init() local
142 writel(0x00003f3f, &ccm->CCGR0); in ccgr_init()
143 writel(0x0030fc00, &ccm->CCGR1); in ccgr_init()
144 writel(0x000fc000, &ccm->CCGR2); in ccgr_init()
145 writel(0x3f300000, &ccm->CCGR3); in ccgr_init()
146 writel(0xff00f300, &ccm->CCGR4); in ccgr_init()
147 writel(0x0f0000c3, &ccm->CCGR5); in ccgr_init()
148 writel(0x000003cc, &ccm->CCGR6); in ccgr_init()
/external/u-boot/board/sunxi/
Dgmac.c12 struct sunxi_ccm_reg *const ccm = local
17 setbits_le32(&ccm->ahb_reset0_cfg, 0x1 << AHB_RESET_OFFSET_GMAC);
18 setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_GMAC);
20 setbits_le32(&ccm->ahb_gate1, 0x1 << AHB_GATE_OFFSET_GMAC);
25 setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII |
27 setbits_le32(&ccm->gmac_clk_cfg,
30 setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_MII |
/external/u-boot/arch/m68k/cpu/mcf5227x/
Dspeed.c31 ccm_t *ccm = (ccm_t *)MMAP_CCM; in clock_enter_limp() local
44 clrsetbits_be16(&ccm->cdr, 0x0f00, CCM_CDR_LPDIV(i)); in clock_enter_limp()
47 setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP); in clock_enter_limp()
56 ccm_t *ccm = (ccm_t *)MMAP_CCM; in clock_exit_limp() local
60 clrbits_be16(&ccm->misccr, CCM_MISCCR_LIMP); in clock_exit_limp()
73 ccm_t *ccm = (ccm_t *)MMAP_CCM; in get_clocks() local
107 if ((in_be16(&ccm->ccr) & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) { in get_clocks()

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