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Searched refs:constrainOperandRegClass (Results 1 – 17 of 17) sorted by relevance

/external/llvm/lib/Target/ARM/
DARMFastISel.cpp286 Op0 = constrainOperandRegClass(II, Op0, 1); in fastEmitInst_r()
309 Op0 = constrainOperandRegClass(II, Op0, 1); in fastEmitInst_rr()
310 Op1 = constrainOperandRegClass(II, Op1, 2); in fastEmitInst_rr()
337 Op0 = constrainOperandRegClass(II, Op0, 1); in fastEmitInst_ri()
364 Op0 = constrainOperandRegClass(II, Op0, 1); in fastEmitInst_rri()
365 Op1 = constrainOperandRegClass(II, Op1, 2); in fastEmitInst_rri()
532 ResultReg = constrainOperandRegClass(TII.get(ARM::LDRcp), ResultReg, 0); in ARMMaterializeInt()
605 DestReg = constrainOperandRegClass(TII.get(ARM::LDRcp), DestReg, 0); in ARMMaterializeGV()
681 ResultReg = constrainOperandRegClass(TII.get(Opc), ResultReg, 0); in fastMaterializeAlloca()
1068 SrcReg = constrainOperandRegClass(TII.get(Opc), SrcReg, 1); in ARMEmitStore()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMFastISel.cpp312 Op0 = constrainOperandRegClass(II, Op0, 1); in fastEmitInst_r()
335 Op0 = constrainOperandRegClass(II, Op0, 1); in fastEmitInst_rr()
336 Op1 = constrainOperandRegClass(II, Op1, 2); in fastEmitInst_rr()
363 Op0 = constrainOperandRegClass(II, Op0, 1); in fastEmitInst_ri()
527 ResultReg = constrainOperandRegClass(TII.get(ARM::LDRcp), ResultReg, 0); in ARMMaterializeInt()
604 DestReg = constrainOperandRegClass(TII.get(ARM::LDRcp), DestReg, 0); in ARMMaterializeGV()
680 ResultReg = constrainOperandRegClass(TII.get(Opc), ResultReg, 0); in fastMaterializeAlloca()
1068 SrcReg = constrainOperandRegClass(TII.get(Opc), SrcReg, 1); in ARMEmitStore()
1141 SrcReg = constrainOperandRegClass(TII.get(StrOpc), SrcReg, 0); in ARMEmitStore()
1279 OpReg = constrainOperandRegClass(TII.get(TstOpc), OpReg, 0); in SelectBranch()
[all …]
DARMCallLowering.cpp527 MIB->getOperand(0).setReg(constrainOperandRegClass( in lowerCall()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/GlobalISel/
DUtils.cpp47 unsigned llvm::constrainOperandRegClass( in constrainOperandRegClass() function in llvm
121 MO.setReg(constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, I.getDesc(), in constrainSelectedInstRegOperands()
/external/llvm/lib/CodeGen/SelectionDAG/
DFastISel.cpp1789 unsigned FastISel::constrainOperandRegClass(const MCInstrDesc &II, unsigned Op, in constrainOperandRegClass() function in FastISel
1821 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_r()
1843 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rr()
1844 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1); in fastEmitInst_rr()
1868 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rrr()
1869 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1); in fastEmitInst_rrr()
1870 Op2 = constrainOperandRegClass(II, Op2, II.getNumDefs() + 2); in fastEmitInst_rrr()
1894 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_ri()
1917 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rii()
1961 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rri()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/GlobalISel/
DUtils.h57 unsigned constrainOperandRegClass(const MachineFunction &MF,
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/
DFastISel.cpp1982 unsigned FastISel::constrainOperandRegClass(const MCInstrDesc &II, unsigned Op, in constrainOperandRegClass() function in FastISel
2014 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_r()
2036 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rr()
2037 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1); in fastEmitInst_rr()
2061 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rrr()
2062 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1); in fastEmitInst_rrr()
2063 Op2 = constrainOperandRegClass(II, Op2, II.getNumDefs() + 2); in fastEmitInst_rrr()
2087 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_ri()
2110 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rii()
2154 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rri()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64FastISel.cpp1108 constrainOperandRegClass(II, Addr.getReg(), II.getNumDefs()+Idx)); in addLoadStoreOperands()
1110 constrainOperandRegClass(II, Addr.getOffsetReg(), II.getNumDefs()+Idx+1)); in addLoadStoreOperands()
1311 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_rr()
1312 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1); in emitAddSub_rr()
1356 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_ri()
1398 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_rs()
1399 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1); in emitAddSub_rs()
1443 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_rx()
1444 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1); in emitAddSub_rx()
2067 SrcReg = constrainOperandRegClass(II, SrcReg, 0); in emitStoreRelease()
[all …]
DAArch64CallLowering.cpp384 MIB->getOperand(0).setReg(constrainOperandRegClass( in lowerCall()
/external/llvm/lib/Target/AArch64/
DAArch64FastISel.cpp1062 constrainOperandRegClass(II, Addr.getReg(), II.getNumDefs()+Idx)); in addLoadStoreOperands()
1064 constrainOperandRegClass(II, Addr.getOffsetReg(), II.getNumDefs()+Idx+1)); in addLoadStoreOperands()
1261 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_rr()
1262 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1); in emitAddSub_rr()
1306 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_ri()
1346 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_rs()
1347 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1); in emitAddSub_rs()
1389 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_rx()
1390 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1); in emitAddSub_rx()
2060 SrcReg = constrainOperandRegClass(II, SrcReg, II.getNumDefs()); in emitStore()
[all …]
/external/llvm/include/llvm/CodeGen/
DFastISel.h476 unsigned constrainOperandRegClass(const MCInstrDesc &II, unsigned Op,
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/
DFastISel.h477 unsigned constrainOperandRegClass(const MCInstrDesc &II, unsigned Op,
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86CallLowering.cpp439 MIB->getOperand(0).setReg(constrainOperandRegClass( in lowerCall()
DX86FastISel.cpp230 AM.IndexReg = constrainOperandRegClass(MIB->getDesc(), AM.IndexReg, in addFullAddress()
660 ValReg = constrainOperandRegClass(Desc, ValReg, Desc.getNumOperands() - 1); in X86FastEmitStore()
4004 unsigned IndexReg = constrainOperandRegClass(Result->getDesc(), in tryToFoldLoadIntoMI()
4025 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rrrr()
4026 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1); in fastEmitInst_rrrr()
4027 Op2 = constrainOperandRegClass(II, Op2, II.getNumDefs() + 2); in fastEmitInst_rrrr()
4028 Op3 = constrainOperandRegClass(II, Op3, II.getNumDefs() + 3); in fastEmitInst_rrrr()
/external/llvm/lib/Target/Mips/
DMipsFastISel.cpp1879 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rr()
1880 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1); in fastEmitInst_rr()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMipsFastISel.cpp2107 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rr()
2108 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1); in fastEmitInst_rr()
/external/llvm/lib/Target/X86/
DX86FastISel.cpp258 AM.IndexReg = constrainOperandRegClass(MIB->getDesc(), AM.IndexReg, in addFullAddress()
639 ValReg = constrainOperandRegClass(Desc, ValReg, Desc.getNumOperands() - 1); in X86FastEmitStore()
3768 unsigned IndexReg = constrainOperandRegClass(Result->getDesc(), in tryToFoldLoadIntoMI()