| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | Mips16InstrFormats.td | 429 // <|EXTEND|imm10:5|imm15:11|op|0|0|0|0|0|0|imm4:0>
480 // <|EXTEND|imm10:5|imm15:11|op|rx|0|0|0|imm4:0>
504 // <|EXTEND|imm10:5|imm15:11|op|rx|ry|imm4:0>
529 // <|EXTEND|imm10:4|imm14:11|RRI-A|rx|ry|f|imm3:0>
582 // <|EXTEND|imm10:5|imm15:11|I8|funct|0|imm4:0>
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| D | MipsInstrFormats.td | 618 bits<10> imm10;
625 let Inst{15-6} = imm10;
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| D | Mips64InstrInfo.td | 455 InstSE<(outs GPR64Opnd:$rt), (ins GPR64Opnd:$rs, simm10_64:$imm10),
456 !strconcat(opstr, "\t$rt, $rs, $imm10"),
458 immSExt10_64:$imm10)))],
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| /external/llvm/lib/Target/Mips/ |
| D | Mips16InstrFormats.td | 429 // <|EXTEND|imm10:5|imm15:11|op|0|0|0|0|0|0|imm4:0>
480 // <|EXTEND|imm10:5|imm15:11|op|rx|0|0|0|imm4:0>
504 // <|EXTEND|imm10:5|imm15:11|op|rx|ry|imm4:0>
529 // <|EXTEND|imm10:4|imm14:11|RRI-A|rx|ry|f|imm3:0>
582 // <|EXTEND|imm10:5|imm15:11|I8|funct|0|imm4:0>
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| D | MipsInstrFormats.td | 609 bits<10> imm10;
616 let Inst{15-6} = imm10;
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| D | Mips64InstrInfo.td | 378 InstSE<(outs GPR64Opnd:$rt), (ins GPR64Opnd:$rs, simm10_64:$imm10),
379 !strconcat(opstr, "\t$rt, $rs, $imm10"),
381 immSExt10_64:$imm10)))],
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/ |
| D | LanaiInstrInfo.td | 114 def imm10 : Operand<i32>, PatLeaf<(imm), [{
227 let MIOperandInfo = (ops GPR:$base, imm10:$offset, AluOp:$Opcode);
566 let imm10 = src{9-0};
665 let imm10 = dst{9-0};
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| D | LanaiInstrFormats.td | 510 bits<10> imm10;
521 let Inst{9 - 0} = imm10;
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| /external/llvm/lib/Target/Lanai/ |
| D | LanaiInstrInfo.td | 113 def imm10 : Operand<i32>, PatLeaf<(imm), [{
229 let MIOperandInfo = (ops GPR:$base, imm10:$offset, AluOp:$Opcode);
568 let imm10 = src{9-0};
667 let imm10 = dst{9-0};
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| D | LanaiInstrFormats.td | 510 bits<10> imm10;
521 let Inst{9 - 0} = imm10;
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| /external/v8/src/mips/ |
| D | assembler-mips.h | 1141 void ldi_b(MSARegister wd, int32_t imm10);
1142 void ldi_h(MSARegister wd, int32_t imm10);
1143 void ldi_w(MSARegister wd, int32_t imm10);
1144 void ldi_d(MSARegister wd, int32_t imm10);
2067 int32_t imm10, MSARegister wd);
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| D | assembler-mips.cc | 1370 int32_t imm10, MSARegister wd) { in GenInstrMsaI10() argument
1372 DCHECK(wd.is_valid() && is_int10(imm10)); in GenInstrMsaI10()
1373 Instr instr = MSA | operation | df | ((imm10 & kImm10Mask) << kWsShift) | in GenInstrMsaI10()
3293 void Assembler::name(MSARegister wd, int32_t imm10) { \ in MSA_LD_ST_LIST()
3294 GenInstrMsaI10(LDI, format, imm10, wd); \ in MSA_LD_ST_LIST()
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| /external/v8/src/mips64/ |
| D | assembler-mips64.h | 1213 void ldi_b(MSARegister wd, int32_t imm10);
1214 void ldi_h(MSARegister wd, int32_t imm10);
1215 void ldi_w(MSARegister wd, int32_t imm10);
1216 void ldi_d(MSARegister wd, int32_t imm10);
2132 int32_t imm10, MSARegister wd);
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| D | assembler-mips64.cc | 1334 int32_t imm10, MSARegister wd) { in GenInstrMsaI10() argument
1336 DCHECK(wd.is_valid() && is_int10(imm10)); in GenInstrMsaI10()
1337 Instr instr = MSA | operation | df | ((imm10 & kImm10Mask) << kWsShift) | in GenInstrMsaI10()
3610 void Assembler::name(MSARegister wd, int32_t imm10) { \ in MSA_LD_ST_LIST()
3611 GenInstrMsaI10(LDI, format, imm10, wd); \ in MSA_LD_ST_LIST()
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| /external/capstone/arch/ARM/ |
| D | ARMDisassembler.c | 2234 unsigned imm10 = fieldFromInstruction_4(Insn, 16, 10); in DecodeT2BInstruction() local
2236 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11; in DecodeT2BInstruction()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/Disassembler/ |
| D | ARMDisassembler.cpp | 2274 unsigned imm10 = fieldFromInstruction(Insn, 16, 10); in DecodeT2BInstruction() local
2276 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11; in DecodeT2BInstruction()
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| /external/llvm/lib/Target/ARM/Disassembler/ |
| D | ARMDisassembler.cpp | 2275 unsigned imm10 = fieldFromInstruction(Insn, 16, 10); in DecodeT2BInstruction() local
2277 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11; in DecodeT2BInstruction()
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
| D | MipsGenDAGISel.inc | 15521 /* 28462*/ OPC_RecordChild1, // #1 = $imm10
15537 …GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] })<<P:Predicate_immSExt10_64>>:$imm10, SETEQ:{ *:[Other]…
15538 // Dst: (SEQi:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] }):$imm10)
15548 …GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] })<<P:Predicate_immSExt10_64>>:$imm10, SETNE:{ *:[Other]…
15549 // Dst: (SNEi:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] }):$imm10)
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| D | MipsGenMCCodeEmitter.inc | 5442 // op: imm10
|