Home
last modified time | relevance | path

Searched refs:imm16 (Results 1 – 25 of 75) sorted by relevance

123

/external/u-boot/arch/arm/include/asm/
Dopcodes-virt.h11 #define __HVC(imm16) __inst_arm_thumb32( \ argument
12 0xE1400070 | (((imm16) & 0xFFF0) << 4) | ((imm16) & 0x000F), \
13 0xF7E08000 | (((imm16) & 0xF000) << 4) | ((imm16) & 0x0FFF) \
/external/vixl/test/aarch32/config/
Dcond-rd-operand-imm16-t32.json28 // MNEMONIC{<c>}.W <Rd>, #<imm16>
32 "Mov", // MOV{<c>}{<q>} <Rd>, #<imm16> ; T3
33 "Movt", // MOVT{<c>}{<q>} <Rd>, #<imm16> ; T1
34 "Movw" // MOVW{<c>}{<q>} <Rd>, #<imm16> ; T3
84 "Mov", // MOV{<c>}{<q>} <Rd>, #<imm16> ; T3
85 "Movt" // MOVT{<c>}{<q>} <Rd>, #<imm16> ; T1
/external/v8/src/s390/
Dassembler-s390.cc432 int16_t imm16 = SIGN_EXT_IMM16((instr & kImm16Mask)); in target_at() local
433 imm16 <<= 1; // immediate is in # of halfwords in target_at()
434 if (imm16 == 0) return kEndOfChain; in target_at()
435 return pos + imm16; in target_at()
447 int16_t imm16 = SIGN_EXT_IMM16((instr & kImm16Mask)); in target_at() local
448 imm16 <<= 1; // immediate is in # of halfwords in target_at()
449 if (imm16 == 0) return kEndOfChain; in target_at()
450 return pos + imm16; in target_at()
470 int16_t imm16 = target_pos - pos; in target_at_put() local
472 DCHECK(is_int16(imm16)); in target_at_put()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMips16InstrFormats.td436 bits<16> imm16;
441 let Inst{26-21} = imm16{10-5};
442 let Inst{20-16} = imm16{15-11};
445 let Inst{4-0} = imm16{4-0};
487 bits<16> imm16;
493 let Inst{26-21} = imm16{10-5};
494 let Inst{20-16} = imm16{15-11};
498 let Inst{4-0} = imm16{4-0};
512 bits<16> imm16;
518 let Inst{26-21} = imm16{10-5};
[all …]
DMipsInstrFormats.td184 bits<16> imm16;
190 let Inst{15-0} = imm16;
199 bits<16> imm16;
205 let Inst{15-0} = imm16;
243 bits<16> imm16;
250 let Inst{15-0} = imm16;
271 bits<16> imm16;
278 let Inst{15-0} = imm16;
354 bits<16> imm16;
361 let Inst{15-0} = imm16;
[all …]
DMips16InstrInfo.td55 FI16<op, (outs), (ins brtarget:$imm16),
56 !strconcat(asmstr, "\t$imm16 # 16 bit inst"), [], itin>;
152 FEXT_I16<eop, (outs), (ins brtarget:$imm16),
153 !strconcat(asmstr, "\t$imm16"),[], itin>;
1362 Mips16Pat<(OpNode bb:$imm16), (I bb:$imm16)> {
1400 Mips16Pat<(cond_op CPU16Regs:$rx, imm_type:$imm16),
1401 (I CPU16Regs:$rx, imm_type:$imm16)>;
1429 <(brcond (i32 (seteq CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1430 (BteqzT8CmpX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1448 <(brcond (i32 (setgt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
[all …]
DMicroMipsInstrFormats.td314 bits<16> imm16;
321 let Inst{15-0} = imm16;
327 bits<16> imm16;
334 let Inst{15-0} = imm16;
339 bits<16> imm16;
346 let Inst{15-0} = imm16;
693 bits<16> imm16;
700 let Inst{15-0} = imm16;
/external/llvm/lib/Target/Mips/
DMips16InstrFormats.td436 bits<16> imm16;
441 let Inst{26-21} = imm16{10-5};
442 let Inst{20-16} = imm16{15-11};
445 let Inst{4-0} = imm16{4-0};
487 bits<16> imm16;
493 let Inst{26-21} = imm16{10-5};
494 let Inst{20-16} = imm16{15-11};
498 let Inst{4-0} = imm16{4-0};
512 bits<16> imm16;
518 let Inst{26-21} = imm16{10-5};
[all …]
DMipsInstrFormats.td177 bits<16> imm16;
183 let Inst{15-0} = imm16;
192 bits<16> imm16;
198 let Inst{15-0} = imm16;
236 bits<16> imm16;
243 let Inst{15-0} = imm16;
264 bits<16> imm16;
271 let Inst{15-0} = imm16;
347 bits<16> imm16;
354 let Inst{15-0} = imm16;
[all …]
DMips16InstrInfo.td55 FI16<op, (outs), (ins brtarget:$imm16),
56 !strconcat(asmstr, "\t$imm16 # 16 bit inst"), [], itin>;
152 FEXT_I16<eop, (outs), (ins brtarget:$imm16),
153 !strconcat(asmstr, "\t$imm16"),[], itin>;
1356 Mips16Pat<(OpNode bb:$imm16), (I bb:$imm16)> {
1394 Mips16Pat<(cond_op CPU16Regs:$rx, imm_type:$imm16),
1395 (I CPU16Regs:$rx, imm_type:$imm16)>;
1431 <(brcond (i32 (seteq CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1432 (BteqzT8CmpX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1450 <(brcond (i32 (setgt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
[all …]
DMicroMipsInstrFormats.td301 bits<16> imm16;
308 let Inst{15-0} = imm16;
314 bits<16> imm16;
321 let Inst{15-0} = imm16;
326 bits<16> imm16;
333 let Inst{15-0} = imm16;
668 bits<16> imm16;
675 let Inst{15-0} = imm16;
DMicroMips64r6InstrFormats.td124 bits<16> imm16;
131 let Inst{15-0} = imm16;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/
DLanaiInstrInfo.td278 def LO : InstRI<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, LoExt:$imm16),
279 !strconcat(AsmStr, "\t$Rs1, $imm16, $Rd"),
282 def HI : InstRI<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, HiExt:$imm16),
283 !strconcat(AsmStr, "\t$Rs1, $imm16, $Rd"),
302 [(set GPR:$Rd, (OpNode GPR:$Rs1, LoExt:$imm16))],
303 [(set GPR:$Rd, (OpNode GPR:$Rs1, HiExt:$imm16))]>;
409 def MOVHI : InstRI<0b000, (outs GPR:$Rd), (ins i32hi16:$imm16),
410 "mov\t$imm16, $Rd",
411 [(set GPR:$Rd, i32hi16:$imm16)]>;
413 def : InstAlias<"mov $imm16, $dst", (ADD_I_LO GPR:$dst, R0, i32lo16z:$imm16)>;
[all …]
DLanaiInstrFormats.td95 bits<16> imm16;
103 let Inst{15 - 0} = imm16;
203 bits<16> imm16;
214 let Inst{15 - 0} = imm16;
360 bits<16> imm16;
367 let Inst{15 - 0} = imm16;
/external/llvm/lib/Target/Lanai/
DLanaiInstrInfo.td280 def LO : InstRI<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, LoExt:$imm16),
281 !strconcat(AsmStr, "\t$Rs1, $imm16, $Rd"),
284 def HI : InstRI<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, HiExt:$imm16),
285 !strconcat(AsmStr, "\t$Rs1, $imm16, $Rd"),
304 [(set GPR:$Rd, (OpNode GPR:$Rs1, LoExt:$imm16))],
305 [(set GPR:$Rd, (OpNode GPR:$Rs1, HiExt:$imm16))]>;
411 def MOVHI : InstRI<0b000, (outs GPR:$Rd), (ins i32hi16:$imm16),
412 "mov\t$imm16, $Rd",
413 [(set GPR:$Rd, i32hi16:$imm16)]>;
415 def : InstAlias<"mov $imm16, $dst", (ADD_I_LO GPR:$dst, R0, i32lo16z:$imm16)>;
[all …]
DLanaiInstrFormats.td95 bits<16> imm16;
103 let Inst{15 - 0} = imm16;
203 bits<16> imm16;
214 let Inst{15 - 0} = imm16;
360 bits<16> imm16;
367 let Inst{15 - 0} = imm16;
/external/v8/src/ppc/
Dassembler-ppc.cc485 int imm16 = target_pos - pos; in target_at_put() local
486 CHECK(is_int16(imm16) && (imm16 & (kAAMask | kLKMask)) == 0); in target_at_put()
487 if (imm16 == kInstrSize && !(instr & kLKMask)) { in target_at_put()
492 instr |= (imm16 & kImm16Mask); in target_at_put()
744 int imm16 = branch_offset; in bc() local
745 CHECK(is_int16(imm16) && (imm16 & (kAAMask | kLKMask)) == 0); in bc()
746 emit(BCX | bo | condition_bit * B16 | (imm16 & kImm16Mask) | lk); in bc()
954 intptr_t imm16 = src2.immediate(); in cmpi() local
960 DCHECK(is_int16(imm16)); in cmpi()
962 imm16 &= kImm16Mask; in cmpi()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/Mips/
DMipsInstrFormats.td109 bits<16> imm16;
115 let Inst{15-0} = imm16;
124 bits<16> imm16;
130 let Inst{15-0} = imm16;
194 bits<16> imm16;
200 let Inst{15-0} = imm16;
DMipsInstrInfo.td286 FI<op, (outs RC:$rt), (ins RC:$rs, Od:$imm16),
287 !strconcat(instr_asm, "\t$rt, $rs, $imm16"),
288 [(set RC:$rt, (OpNode RC:$rs, imm_type:$imm16))], IIAlu>;
292 FI<op, (outs RC:$rt), (ins RC:$rs, Od:$imm16),
293 !strconcat(instr_asm, "\t$rt, $rs, $imm16"), [], IIAlu>;
334 FI<op, (outs CPURegs:$rt), (ins uimm16:$imm16),
335 !strconcat(instr_asm, "\t$rt, $imm16"), [], IIAlu> {
402 CBranchBase<op, (outs), (ins RC:$rs, RC:$rt, brtarget:$imm16),
403 !strconcat(instr_asm, "\t$rs, $rt, $imm16"),
404 [(brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$imm16)], IIBranch> {
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/
DSparcInstr64Bit.td351 def napt : F2_4<cond, 0, 1, (outs), (ins I64Regs:$rs1, bprtarget16:$imm16),
352 !strconcat(OpcStr, " $rs1, $imm16"), []>;
353 def apt : F2_4<cond, 1, 1, (outs), (ins I64Regs:$rs1, bprtarget16:$imm16),
354 !strconcat(OpcStr, ",a $rs1, $imm16"), []>;
355 def napn : F2_4<cond, 0, 0, (outs), (ins I64Regs:$rs1, bprtarget16:$imm16),
356 !strconcat(OpcStr, ",pn $rs1, $imm16"), []>;
357 def apn : F2_4<cond, 1, 0, (outs), (ins I64Regs:$rs1, bprtarget16:$imm16),
358 !strconcat(OpcStr, ",a,pn $rs1, $imm16"), []>;
362 def : InstAlias<!strconcat(OpcStr, ",pt $rs1, $imm16"),
363 (NAPT I64Regs:$rs1, bprtarget16:$imm16), 0>;
[all …]
/external/llvm/lib/Target/Sparc/
DSparcInstr64Bit.td351 def napt : F2_4<cond, 0, 1, (outs), (ins I64Regs:$rs1, bprtarget16:$imm16),
352 !strconcat(OpcStr, " $rs1, $imm16"), []>;
353 def apt : F2_4<cond, 1, 1, (outs), (ins I64Regs:$rs1, bprtarget16:$imm16),
354 !strconcat(OpcStr, ",a $rs1, $imm16"), []>;
355 def napn : F2_4<cond, 0, 0, (outs), (ins I64Regs:$rs1, bprtarget16:$imm16),
356 !strconcat(OpcStr, ",pn $rs1, $imm16"), []>;
357 def apn : F2_4<cond, 1, 0, (outs), (ins I64Regs:$rs1, bprtarget16:$imm16),
358 !strconcat(OpcStr, ",a,pn $rs1, $imm16"), []>;
362 def : InstAlias<!strconcat(OpcStr, ",pt $rs1, $imm16"),
363 (NAPT I64Regs:$rs1, bprtarget16:$imm16), 0>;
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/
DMBlazeInstrFormats.td48 // imm16 - 16-bit immediate value.
114 bits<16> imm16;
118 let Inst{16-31} = imm16;
156 let imm16 = rimm16;
/external/syzkaller/pkg/ifuzz/
Dpseudo.go192 gen.imm16(uint16(off))
196 gen.imm16(sel)
297 func (gen *generator) imm16(v uint16) { func
366 gen.imm16(v)
/external/v8/src/ia32/
Dassembler-ia32.cc898 void Assembler::cmpw(Operand op, Immediate imm16) { in cmpw() argument
899 DCHECK(imm16.is_int16() || imm16.is_uint16()); in cmpw()
904 emit_w(imm16); in cmpw()
1357 void Assembler::test_w(Register reg, Immediate imm16) { in test_w() argument
1358 DCHECK(imm16.is_int16() || imm16.is_uint16()); in test_w()
1362 emit_w(imm16); in test_w()
1367 emit_w(imm16); in test_w()
1378 void Assembler::test_w(Operand op, Immediate imm16) { in test_w() argument
1379 DCHECK(imm16.is_int16() || imm16.is_uint16()); in test_w()
1381 test_w(op.reg(), imm16); in test_w()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/Blackfin/
DREADME.txt84 | Ksh | imm16 | |
144 | P+imm16 | | | | | | * | * |
163 | P+imm16 | | | | | * |

123