| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenAsmWriter.inc | 12885 MI->getOperand(1).isReg() &&
12895 MI->getOperand(1).isReg() &&
12897 MI->getOperand(2).isReg() &&
12907 MI->getOperand(1).isReg() &&
12909 MI->getOperand(2).isReg() &&
12916 MI->getOperand(0).isReg() &&
12918 MI->getOperand(1).isReg() &&
12920 MI->getOperand(2).isReg() &&
12932 MI->getOperand(1).isReg() &&
12934 MI->getOperand(2).isReg() &&
[all …]
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| D | AArch64GenAsmWriter1.inc | 13573 MI->getOperand(1).isReg() &&
13583 MI->getOperand(1).isReg() &&
13585 MI->getOperand(2).isReg() &&
13595 MI->getOperand(1).isReg() &&
13597 MI->getOperand(2).isReg() &&
13604 MI->getOperand(0).isReg() &&
13606 MI->getOperand(1).isReg() &&
13608 MI->getOperand(2).isReg() &&
13620 MI->getOperand(1).isReg() &&
13622 MI->getOperand(2).isReg() &&
[all …]
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| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | MachineOperand.h | 191 bool isReg() const { return OpKind == MO_Register; } in isReg() function
222 assert(isReg() && "This is not a register operand!"); in getReg()
227 assert(isReg() && "Wrong MachineOperand accessor"); in getSubReg()
232 assert(isReg() && "Wrong MachineOperand accessor"); in isUse()
237 assert(isReg() && "Wrong MachineOperand accessor"); in isDef()
242 assert(isReg() && "Wrong MachineOperand accessor"); in isImplicit()
247 assert(isReg() && "Wrong MachineOperand accessor"); in isDead()
252 assert(isReg() && "Wrong MachineOperand accessor"); in isKill()
257 assert(isReg() && "Wrong MachineOperand accessor"); in isUndef()
262 assert(isReg() && "Wrong MachineOperand accessor"); in isEarlyClobber()
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/InstPrinter/ |
| D | MipsInstPrinter.cpp | 32 static bool isReg(const MCInst &MI, unsigned OpNo) { in isReg() function
33 assert(MI.getOperand(OpNo).isReg() && "Register operand expected."); in isReg()
128 if (Op.isReg()) { in printOperand()
226 return (isReg<Mips::ZERO>(MI, 0) && isReg<Mips::ZERO>(MI, 1) && in printAlias()
228 (isReg<Mips::ZERO>(MI, 1) && printAlias("beqz", MI, 0, 2, OS)); in printAlias()
231 return isReg<Mips::ZERO_64>(MI, 1) && printAlias("beqz", MI, 0, 2, OS); in printAlias()
235 return isReg<Mips::ZERO>(MI, 1) && printAlias("bnez", MI, 0, 2, OS); in printAlias()
238 return isReg<Mips::ZERO_64>(MI, 1) && printAlias("bnez", MI, 0, 2, OS); in printAlias()
241 return isReg<Mips::ZERO>(MI, 0) && printAlias("bal", MI, 1, OS); in printAlias()
244 return isReg<Mips::FCC0>(MI, 0) && printAlias("bc1t", MI, 1, OS); in printAlias()
[all …]
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| /external/llvm/lib/Target/Mips/InstPrinter/ |
| D | MipsInstPrinter.cpp | 32 static bool isReg(const MCInst &MI, unsigned OpNo) { in isReg() function
33 assert(MI.getOperand(OpNo).isReg() && "Register operand expected."); in isReg()
128 if (Op.isReg()) { in printOperand()
232 return (isReg<Mips::ZERO>(MI, 0) && isReg<Mips::ZERO>(MI, 1) && in printAlias()
234 (isReg<Mips::ZERO>(MI, 1) && printAlias("beqz", MI, 0, 2, OS)); in printAlias()
237 return isReg<Mips::ZERO_64>(MI, 1) && printAlias("beqz", MI, 0, 2, OS); in printAlias()
240 return isReg<Mips::ZERO>(MI, 1) && printAlias("bnez", MI, 0, 2, OS); in printAlias()
243 return isReg<Mips::ZERO_64>(MI, 1) && printAlias("bnez", MI, 0, 2, OS); in printAlias()
246 return isReg<Mips::ZERO>(MI, 0) && printAlias("bal", MI, 1, OS); in printAlias()
249 return isReg<Mips::FCC0>(MI, 0) && printAlias("bc1t", MI, 1, OS); in printAlias()
[all …]
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| /external/llvm/include/llvm/CodeGen/ |
| D | MachineOperand.h | 192 return isReg() ? 0 : SubReg_TargetFlags; in getTargetFlags()
195 assert(!isReg() && "Register operands can't have target flags"); in setTargetFlags()
200 assert(!isReg() && "Register operands can't have target flags"); in addTargetFlag()
230 bool isReg() const { return OpKind == MO_Register; } in isReg() function
268 assert(isReg() && "This is not a register operand!"); in getReg()
273 assert(isReg() && "Wrong MachineOperand accessor"); in getSubReg()
278 assert(isReg() && "Wrong MachineOperand accessor"); in isUse()
283 assert(isReg() && "Wrong MachineOperand accessor"); in isDef()
288 assert(isReg() && "Wrong MachineOperand accessor"); in isImplicit()
293 assert(isReg() && "Wrong MachineOperand accessor"); in isDead()
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | MachineOperand.h | 216 return isReg() ? 0 : SubReg_TargetFlags; in getTargetFlags()
219 assert(!isReg() && "Register operands can't have target flags"); in setTargetFlags()
224 assert(!isReg() && "Register operands can't have target flags"); in addTargetFlag()
311 bool isReg() const { return OpKind == MO_Register; } in isReg() function
350 assert(isReg() && "This is not a register operand!"); in getReg()
355 assert(isReg() && "Wrong MachineOperand accessor"); in getSubReg()
360 assert(isReg() && "Wrong MachineOperand accessor"); in isUse()
365 assert(isReg() && "Wrong MachineOperand accessor"); in isDef()
370 assert(isReg() && "Wrong MachineOperand accessor"); in isImplicit()
375 assert(isReg() && "Wrong MachineOperand accessor"); in isDead()
[all …]
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| /external/capstone/arch/Mips/ |
| D | MipsInstPrinter.c | 105 static bool isReg(MCInst *MI, unsigned OpNo, unsigned R) in isReg() function
346 if (isReg(MI, 0, Mips_ZERO) && isReg(MI, 1, Mips_ZERO)) in printAlias()
348 if (isReg(MI, 1, Mips_ZERO)) in printAlias()
353 if (isReg(MI, 0, Mips_ZERO) && isReg(MI, 1, Mips_ZERO)) in printAlias()
358 if (isReg(MI, 1, Mips_ZERO_64)) in printAlias()
363 if (isReg(MI, 1, Mips_ZERO)) in printAlias()
368 if (isReg(MI, 1, Mips_ZERO)) in printAlias()
373 if (isReg(MI, 1, Mips_ZERO_64)) in printAlias()
378 if (isReg(MI, 0, Mips_ZERO)) in printAlias()
383 if (isReg(MI, 0, Mips_FCC0)) in printAlias()
[all …]
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| /external/llvm/lib/Target/Lanai/MCTargetDesc/ |
| D | LanaiMCCodeEmitter.cpp | 115 if (MCOp.isReg()) in getMachineOpValue()
149 (Op2.isReg() && Op2.getReg() != Lanai::R0) || (Op2.isExpr()))) in adjustPqBits()
153 assert(Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg() && in adjustPqBits()
157 (Op2.isReg() && Op2.getReg() != Lanai::R0))) in adjustPqBits()
196 assert(Op1.isReg() && "First operand is not register."); in getRiMemoryOpValue()
228 assert(Op1.isReg() && "First operand is not register."); in getRrMemoryOpValue()
230 assert(Op2.isReg() && "Second operand is not register."); in getRrMemoryOpValue()
267 assert(Op1.isReg() && "First operand is not register."); in getSplsOpValue()
295 if (MCOp.isReg() || MCOp.isImm()) in getCallTargetOpValue()
308 if (MCOp.isReg() || MCOp.isImm()) in getBranchTargetOpValue()
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | MachineInstr.cpp | 53 assert(isReg() && "Can only add reg operand to use lists"); in AddRegOperandToRegInfo()
144 if (isReg() && getParent() && getParent()->getParent() && in ChangeToImmediate()
160 if (isReg()) { in ChangeToRegister()
572 assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) && in ~MachineInstr()
592 if (Operands[i].isReg()) in RemoveRegOperandsFromUseLists()
602 if (Operands[i].isReg()) in AddRegOperandsToUseLists()
614 bool isImpReg = Op.isReg() && Op.isImplicit(); in addOperand()
632 while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) { in addOperand()
649 if (Operands[i].isReg()) in addOperand()
660 if (Operands[i].isReg()) in addOperand()
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/MCTargetDesc/ |
| D | LanaiMCCodeEmitter.cpp | 113 if (MCOp.isReg()) in getMachineOpValue()
147 (Op2.isReg() && Op2.getReg() != Lanai::R0) || (Op2.isExpr()))) in adjustPqBits()
151 assert(Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg() && in adjustPqBits()
155 (Op2.isReg() && Op2.getReg() != Lanai::R0))) in adjustPqBits()
194 assert(Op1.isReg() && "First operand is not register."); in getRiMemoryOpValue()
226 assert(Op1.isReg() && "First operand is not register."); in getRrMemoryOpValue()
228 assert(Op2.isReg() && "Second operand is not register."); in getRrMemoryOpValue()
265 assert(Op1.isReg() && "First operand is not register."); in getSplsOpValue()
293 if (MCOp.isReg() || MCOp.isImm()) in getBranchTargetOpValue()
|
| /external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| D | PPCMCCodeEmitter.cpp | 157 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getDirectBrEncoding()
169 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getCondBrEncoding()
182 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getAbsDirectBrEncoding()
195 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getAbsCondBrEncoding()
207 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getImm16Encoding()
220 assert(MI.getOperand(OpNo+1).isReg()); in getMemRIEncoding()
239 assert(MI.getOperand(OpNo+1).isReg()); in getMemRIXEncoding()
257 assert(MI.getOperand(OpNo+1).isReg()); in getMemRIX16Encoding()
272 assert(MI.getOperand(OpNo+1).isReg()); in getSPE8DisEncoding()
288 assert(MI.getOperand(OpNo+1).isReg()); in getSPE4DisEncoding()
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| D | PPCMCCodeEmitter.cpp | 164 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getDirectBrEncoding()
176 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getCondBrEncoding()
189 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getAbsDirectBrEncoding()
202 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getAbsCondBrEncoding()
214 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getImm16Encoding()
227 assert(MI.getOperand(OpNo+1).isReg()); in getMemRIEncoding()
245 assert(MI.getOperand(OpNo+1).isReg()); in getMemRIXEncoding()
263 assert(MI.getOperand(OpNo+1).isReg()); in getMemRIX16Encoding()
279 assert(MI.getOperand(OpNo+1).isReg()); in getSPE8DisEncoding()
294 assert(MI.getOperand(OpNo+1).isReg()); in getSPE4DisEncoding()
[all …]
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIFoldOperands.cpp | 62 assert(FoldOp->isReg()); in FoldCandidate()
103 assert(Old.isReg()); in updateOperand()
175 if (CanCommute && (!MI->getOperand(CommuteIdx0).isReg() || in tryAddToFoldList()
176 !MI->getOperand(CommuteIdx1).isReg())) in tryAddToFoldList()
200 if (UseOp.isReg() && ((UseOp.getSubReg() && OpToFold.isReg()) || in foldOperand()
323 if (!FoldingImm && !OpToFold.isReg()) in runOnMachineFunction()
333 if (OpToFold.isReg() && in runOnMachineFunction()
344 if (Dst.isReg() && in runOnMachineFunction()
372 assert(Fold.OpToFold && Fold.OpToFold->isReg()); in runOnMachineFunction()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | MachineInstr.cpp | 163 if (MO.isReg()) in RemoveRegOperandsFromUseLists()
172 if (MO.isReg()) in AddRegOperandsToUseLists()
219 bool isImpReg = Op.isReg() && Op.isImplicit(); in addOperand()
221 while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) { in addOperand()
266 if (NewMO->isReg()) { in addOperand()
301 if (Operands[i].isReg()) in RemoveOperand()
306 if (MRI && Operands[OpNo].isReg()) in RemoveOperand()
440 if (!MO.isReg()) { in isIdenticalTo()
507 if (!MO.isReg() || !MO.isDef()) in eraseFromParentAndMarkDBGValuesForRemoval()
534 if (MO.isReg() && MO.isImplicit()) in getNumExplicitOperands()
[all …]
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| D | MIRCanonicalizerPass.cpp | 86 bool isReg() const { return type == RSE_Reg; } in isReg() function in TypedVReg
92 assert(this->isReg() && "Expected a virtual or physical register."); in getReg()
187 if (!MO.isReg()) in rescheduleCanonically()
207 if (!MO.isReg() || !TargetRegisterInfo::isVirtualRegister(MO.getReg())) in rescheduleCanonically()
219 if (II->getOperand(i).isReg()) { in rescheduleCanonically()
333 if (!MI->getOperand(0).isReg()) in propagateLocalCopies()
335 if (!MI->getOperand(1).isReg()) in propagateLocalCopies()
375 if (MI->getNumOperands() > 0 && MI->getOperand(0).isReg()) { in populateCandidates()
415 assert(TReg.isReg() && "Expected vreg or physreg."); in doCandidateWalk()
426 return TR.isReg() && TR.getReg() == Reg; in doCandidateWalk()
[all …]
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
| D | MipsGenAsmWriter.inc | 7307 MI->getOperand(0).isReg() &&
7316 MI->getOperand(0).isReg() &&
7325 MI->getOperand(0).isReg() &&
7327 MI->getOperand(1).isReg() &&
7438 MI->getOperand(1).isReg() &&
7440 MI->getOperand(2).isReg() &&
7450 MI->getOperand(1).isReg() &&
7452 MI->getOperand(2).isReg() &&
7462 MI->getOperand(1).isReg() &&
7464 MI->getOperand(2).isReg() &&
[all …]
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| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/MCTargetDesc/ |
| D | PPCMCCodeEmitter.cpp | 89 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups); in getDirectBrEncoding()
100 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups); in getCondBrEncoding()
111 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups); in getHA16Encoding()
122 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups); in getLO16Encoding()
134 assert(MI.getOperand(OpNo+1).isReg()); in getMemRIEncoding()
152 assert(MI.getOperand(OpNo+1).isReg()); in getMemRIXEncoding()
179 if (MO.isReg()) { in getMachineOpValue()
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| /external/llvm/lib/CodeGen/ |
| D | MachineInstr.cpp | 100 assert(isReg() && "Wrong MachineOperand accessor"); in setIsDef()
120 if (!isReg() || !isOnRegUseList()) in removeRegFromUses()
135 assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm"); in ChangeToImmediate()
144 assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm"); in ChangeToFPImmediate()
153 assert((!isReg() || !isTied()) && in ChangeToES()
165 assert((!isReg() || !isTied()) && in ChangeToMCSymbol()
187 bool WasReg = isReg(); in ChangeToRegister()
732 if (MO.isReg()) in RemoveRegOperandsFromUseLists()
741 if (MO.isReg()) in AddRegOperandsToUseLists()
788 bool isImpReg = Op.isReg() && Op.isImplicit(); in addOperand()
[all …]
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonVLIWPacketizer.cpp | 118 if (!MO.isReg() || !MO.isDef()) in hasWriteToReadDep()
286 if (MO.isReg() && MO.isUse() && (MO.getReg() == DepReg)) in isCallDependent()
354 if (MO.isReg() && MO.getReg() == MI->getOperand(0).getReg()) in cleanUpDotCur()
397 if (MO.isReg() && MO.getReg() == DestReg) in canPromoteToDotCur()
463 if (MO.isReg() && MO.isDef()) in getPostIncrementOperand()
467 if (MO.isReg() && MO.isUse() && DefRegsSet.count(MO.getReg())) in getPostIncrementOperand()
473 assert(Op1.isReg() && "Post increment operand has be to a register."); in getPostIncrementOperand()
479 assert(Op0.isReg() && "Post increment operand has be to a register."); in getPostIncrementOperand()
538 if (Val.isReg() && Val.getReg() != DepReg) in canPromoteToNewValueStore()
591 if (!MO.isReg()) in canPromoteToNewValueStore()
[all …]
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| D | HexagonExpandCondsets.cpp | 351 if (!Op.isReg() || !Op.isUse() || Op.getReg() != Reg) in updateKillFlags()
412 if (!Op.isReg() || !Op.isDef()) in updateDeadsInRange()
519 if (Op.isReg() && Op.isDef() && DefRegs.count(Op)) in updateDeadsInRange()
580 if (SO.isReg()) { in getCondTfrOpcode()
662 bool SameReg = (MS1.isReg() && DR == MS1.getReg()) || in split()
663 (MS2.isReg() && DR == MS2.getReg()); in split()
670 if ((MS1.isReg() && NewSR == MS1.getSubReg()) || in split()
671 (MS2.isReg() && NewSR == MS2.getSubReg())) in split()
695 if (Op.isReg()) in split()
726 if (!Op.isReg() || !Op.isDef()) in isPredicable()
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | SIShrinkInstructions.cpp | 87 if (!Src1->isReg() || !TRI.isVGPR(MRI, Src1->getReg())) in canShrink()
95 if (!Src2->isReg() || !TRI.isVGPR(MRI, Src2->getReg()) || in canShrink()
106 if (Src1 && (!Src1->isReg() || !TRI.isVGPR(MRI, Src1->getReg()) || in canShrink()
131 if (Src0.isReg()) { in foldImmediates()
238 if ((MO.isReg() && MO.isImplicit()) || MO.isRegMask()) in copyExtraImplicitOps()
246 if (!MI.getOperand(0).isReg()) in shrinkScalarCompare()
360 if (!Src0->isReg() && Src1->isReg()) { in runOnMachineFunction()
369 Src0->isReg()) { in runOnMachineFunction()
375 if (Src0->isReg() && Src0->getReg() == Dest->getReg()) { in runOnMachineFunction()
452 if (!Src2->isReg()) in runOnMachineFunction()
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| D | SIFoldOperands.cpp | 51 assert(FoldOp->isReg()); in FoldCandidate()
64 bool isReg() const { in isReg() function
160 assert(Old.isReg()); in updateOperand()
281 if (CanCommute && (!MI->getOperand(CommuteIdx0).isReg() || in tryAddToFoldList()
282 !MI->getOperand(CommuteIdx1).isReg())) in tryAddToFoldList()
323 if (UseOp.isReg() && OpToFold.isReg()) { in foldOperand()
510 if (Op.isReg()) { in getImmOrMaterializedImm()
646 mutateCopyOp(*MI, TII->get(Src0->isReg() ? (unsigned)AMDGPU::COPY in tryFoldInst()
749 if (Fold.isReg()) { in foldInstOperand()
750 assert(Fold.OpToFold && Fold.OpToFold->isReg()); in foldInstOperand()
[all …]
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| D | SIOptimizeExecMasking.cpp | 66 if (Src.isReg() && Src.getReg() == AMDGPU::EXEC) in isCopyFromExec()
80 if (Dst.isReg() && Dst.getReg() == AMDGPU::EXEC && MI.getOperand(1).isReg()) in isCopyToExec()
104 if (Src1.isReg() && Src1.getReg() == AMDGPU::EXEC) in isLogicalOpOnExec()
107 if (Src2.isReg() && Src2.getReg() == AMDGPU::EXEC) in isLogicalOpOnExec()
333 if (Src0.isReg() && Src0.getReg() == CopyFromExec) { in runOnMachineFunction()
335 } else if (Src1.isReg() && Src1.getReg() == CopyFromExec) { in runOnMachineFunction()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/ |
| D | LanaiDelaySlotFiller.cpp | 109 assert(RI->getOpcode() == Lanai::LDW_RI && RI->getOperand(0).isReg() && in runOnMachineBasicBlock()
111 RI->getOperand(1).isReg() && in runOnMachineBasicBlock()
116 RI->getOperand(0).isReg() && in runOnMachineBasicBlock()
118 RI->getOperand(1).isReg() && in runOnMachineBasicBlock()
208 if (!MO.isReg() || !(Reg = MO.getReg())) in delayHasHazard()
237 if (!MO.isReg() || !(Reg = MO.getReg())) in insertDefsUses()
|