| /external/v8/src/compiler/mips64/ |
| D | instruction-scheduler-mips64.cc | 334 DMULT = 4, enumerator
501 latency = Latency::DMULT + Latency::MFLO; in DmulLatency()
540 latency = Latency::DMULT + Latency::MFHI; in DMulhLatency()
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| /external/pcre/dist2/src/sljit/ |
| D | sljitNativeMIPS_64.c | 465 FAIL_IF(push_inst(compiler, DMULT | S(src1) | T(src2), MOVABLE_INS)); in emit_single_op()
468 FAIL_IF(push_inst(compiler, SELECT_OP(DMULT, MULT) | S(src1) | T(src2), MOVABLE_INS)); in emit_single_op()
472 FAIL_IF(push_inst(compiler, SELECT_OP(DMULT, MULT) | S(src1) | T(src2), MOVABLE_INS)); in emit_single_op()
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| D | sljitNativeMIPS_common.c | 139 #define DMULT (HI(0) | LO(28)) macro
1079 …FAIL_IF(push_inst(compiler, (op == SLJIT_LMUL_UW ? DMULTU : DMULT) | S(SLJIT_R0) | T(SLJIT_R1), MO… in sljit_emit_op0()
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| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| D | MipsISelDAGToDAG.cpp | 283 (Ty == MVT::i32 ? Mips::MULT : Mips::DMULT)); in Select()
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| D | Mips64InstrInfo.td | 166 def DMULT : Mul64<0x1c, "dmult", IIImul>;
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| /external/v8/src/mips64/ |
| D | constants-mips64.h | 512 DMULT = ((3U << 3) + 4), enumerator
1329 FunctionFieldToBitNumber(MULT) | FunctionFieldToBitNumber(DMULT) |
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| D | assembler-mips64.cc | 2024 GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, DMULT); in dmult()
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| D | simulator-mips64.cc | 3881 case DMULT: // DMULT == D_MUL_MUH. in DecodeTypeRegisterSPECIAL()
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| /external/llvm/lib/Target/Mips/ |
| D | Mips64InstrInfo.td | 252 def DMULT : Mult<"dmult", II_DMULT, GPR64Opnd, [HI0_64, LO0_64]>,
257 def PseudoDMULT : MultDivPseudo<DMULT, ACC128, GPR64Opnd, MipsMult,
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | Mips64InstrInfo.td | 298 def DMULT : Mult<"dmult", II_DMULT, GPR64Opnd, [HI0_64, LO0_64]>,
303 def PseudoDMULT : MultDivPseudo<DMULT, ACC128, GPR64Opnd, MipsMult,
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
| D | MipsGenMCPseudoLowering.inc | 479 TmpInst.setOpcode(Mips::DMULT);
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| D | MipsGenMCCodeEmitter.inc | 1231 UINT64_C(28), // DMULT
5178 case Mips::DMULT:
8957 …_HasMips3 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMicroMips | 0, // DMULT = 1218
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| D | MipsGenAsmWriter.inc | 2446 24011U, // DMULT
5077 0U, // DMULT
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| D | MipsGenInstrInfo.inc | 1233 DMULT = 1218,
5278 …Commutable), 0x1ULL, nullptr, ImplicitList12, OperandInfo103, -1 ,nullptr }, // Inst #1218 = DMULT
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| D | MipsGenDisassemblerTables.inc | 6840 /* 181 */ MCD::OPC_Decode, 194, 9, 235, 2, // Opcode: DMULT
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| D | MipsGenAsmMatcher.inc | 6021 …{ 3394 /* dmult */, Mips::DMULT, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Featur…
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| /external/capstone/arch/Mips/ |
| D | MipsGenAsmWriter.inc | 588 23209U, // DMULT
2302 0U, // DMULT
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| D | MipsGenDisassemblerTables.inc | 4112 /* 95 */ MCD_OPC_Decode, 187, 4, 231, 1, // Opcode: DMULT
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 4723 TOut.emitRR(Inst.getOpcode() == Mips::MULImmMacro ? Mips::MULT : Mips::DMULT, in expandMulImm()
4743 TOut.emitRR(Inst.getOpcode() == Mips::MULOMacro ? Mips::MULT : Mips::DMULT, in expandMulO()
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