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Searched refs:MicroOpBufferSize (Results 1 – 25 of 60) sorted by relevance

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/external/llvm/include/llvm/MC/
DMCSchedule.h156 unsigned MicroOpBufferSize; member
206 bool isOutOfOrder() const { return MicroOpBufferSize > 1; } in isOutOfOrder()
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/MC/
DMCSchedule.h276 unsigned MicroOpBufferSize; member
336 bool isOutOfOrder() const { return MicroOpBufferSize > 1; } in isOutOfOrder()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DSISchedule.td50 // MicroOpBufferSize = 1 means that instructions will always be added
53 let MicroOpBufferSize = 1;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMScheduleM3.td16 let MicroOpBufferSize = 0; // In-order
/external/swiftshader/third_party/llvm-7.0/llvm/tools/llvm-mca/
DRetireControlUnit.cpp26 AvailableSlots(SM.MicroOpBufferSize), MaxRetirePerCycle(0) { in RetireControlUnit()
/external/llvm/include/llvm/CodeGen/
DTargetSchedule.h149 unsigned getMicroOpBufferSize() const { return SchedModel.MicroOpBufferSize; } in getMicroOpBufferSize()
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/
DTargetSchedule.h158 unsigned getMicroOpBufferSize() const { return SchedModel.MicroOpBufferSize; } in getMicroOpBufferSize()
/external/llvm/lib/Target/Lanai/
DLanaiSchedule.td49 let MicroOpBufferSize = 0;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/
DLanaiSchedule.td49 let MicroOpBufferSize = 0;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64SchedFalkor.td21 let MicroOpBufferSize = 128; // Out-of-order with temporary unified issue buffer.
DAArch64SchedKryo.td22 let MicroOpBufferSize = 128; // Out-of-order with temporary unified issue buffer
DAArch64SchedThunderX.td23 let MicroOpBufferSize = 0; // ThunderX T88/T81/T83 are in-order.
DAArch64SchedA53.td20 let MicroOpBufferSize = 0; // Explicitly set to zero since A53 is in-order.
/external/llvm/lib/Target/AArch64/
DAArch64SchedKryo.td22 let MicroOpBufferSize = 128; // Out-of-order with temporary unified issue buffer
DAArch64SchedA53.td20 let MicroOpBufferSize = 0; // Explicitly set to zero since A53 is in-order.
DAArch64SchedM1.td22 let MicroOpBufferSize = 96; // ROB size.
/external/llvm/lib/Target/X86/
DX86ScheduleSLM.td19 let MicroOpBufferSize = 32; // Based on the reorder buffer.
DX86SchedSandyBridge.td20 let MicroOpBufferSize = 168; // Based on the reorder buffer.
DX86Schedule.td628 // MicroOpBufferSize > 1 indicates that RAW dependencies can be
642 let MicroOpBufferSize = 32;
DX86ScheduleBtVer2.td20 let MicroOpBufferSize = 64; // Retire Control Unit
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Target/
DTargetSchedule.td81 int MicroOpBufferSize = -1; // Max micro-ops that can be buffered.
158 // MicroOpBufferSize, which should be the minimum size of either the
523 // field MicroOpBufferSize in SchedModel if the reorder buffer size is unknown.
/external/llvm/include/llvm/Target/
DTargetSchedule.td81 int MicroOpBufferSize = -1; // Max micro-ops that can be buffered.
152 // MicroOpBufferSize, which should be the minimum size of either the
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86Schedule.td635 // MicroOpBufferSize > 1 indicates that RAW dependencies can be
649 let MicroOpBufferSize = 32;
DX86ScheduleSLM.td19 let MicroOpBufferSize = 32; // Based on the reorder buffer.
/external/llvm/lib/Target/Mips/
DMipsScheduleP5600.td12 int MicroOpBufferSize = 48; // min(48, 48, 64)

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