| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/ |
| D | neon-or-combine.ll | 6 ; (or (and B, A), (and C, ~A)) => (VBSL A, B, C)
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| /external/llvm/test/CodeGen/AArch64/ |
| D | neon-or-combine.ll | 6 ; (or (and B, A), (and C, ~A)) => (VBSL A, B, C)
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMISelLowering.h | 188 VBSL, enumerator
|
| D | ARMInstrNEON.td | 112 def NEONvbsl : SDNode<"ARMISD::VBSL",
3885 // VBSL : Vector Bitwise Select
3909 // like VBSL but with: "vbif $dst, $src3, $src1", "$src2 = $dst",
3923 // like VBSL but with: "vbit $dst, $src2, $src1", "$src3 = $dst",
|
| D | ARMISelLowering.cpp | 921 case ARMISD::VBSL: return "ARMISD::VBSL"; in getTargetNodeName()
6759 SDValue Result = DAG.getNode(ARMISD::VBSL, dl, CanonicalVT, in PerformORCombine()
|
| /external/arm-neon-tests/ |
| D | ref-rvct-neon-nofp16.txt | 1477 VBSL/VBSLQ output:
1478 VBSL/VBSLQ:0:result_int8x8 [] = { fffffff2, fffffff2, fffffff2, fffffff2, fffffff6, fffffff6, fffff…
1479 VBSL/VBSLQ:1:result_int16x4 [] = { fffffff0, fffffff0, fffffff2, fffffff2, }
1480 VBSL/VBSLQ:2:result_int32x2 [] = { fffffff0, fffffff0, }
1481 VBSL/VBSLQ:3:result_int64x1 [] = { fffffffffffffffd, }
1482 VBSL/VBSLQ:4:result_uint8x8 [] = { f3, f3, f3, f3, f7, f7, f7, f7, }
1483 VBSL/VBSLQ:5:result_uint16x4 [] = { fff0, fff0, fff2, fff2, }
1484 VBSL/VBSLQ:6:result_uint32x2 [] = { fffffff0, fffffff0, }
1485 VBSL/VBSLQ:7:result_uint64x1 [] = { fffffff1, }
1486 VBSL/VBSLQ:8:result_poly8x8 [] = { f3, f3, f3, f3, f7, f7, f7, f7, }
[all …]
|
| D | ref-rvct-neon.txt | 1569 VBSL/VBSLQ output:
1570 VBSL/VBSLQ:0:result_int8x8 [] = { fffffff2, fffffff2, fffffff2, fffffff2, fffffff6, fffffff6, fffff…
1571 VBSL/VBSLQ:1:result_int16x4 [] = { fffffff0, fffffff0, fffffff2, fffffff2, }
1572 VBSL/VBSLQ:2:result_int32x2 [] = { fffffff0, fffffff0, }
1573 VBSL/VBSLQ:3:result_int64x1 [] = { fffffffffffffffd, }
1574 VBSL/VBSLQ:4:result_uint8x8 [] = { f3, f3, f3, f3, f7, f7, f7, f7, }
1575 VBSL/VBSLQ:5:result_uint16x4 [] = { fff0, fff0, fff2, fff2, }
1576 VBSL/VBSLQ:6:result_uint32x2 [] = { fffffff0, fffffff0, }
1577 VBSL/VBSLQ:7:result_uint64x1 [] = { fffffff1, }
1578 VBSL/VBSLQ:8:result_poly8x8 [] = { f3, f3, f3, f3, f7, f7, f7, f7, }
[all …]
|
| D | ref-rvct-all.txt | 1569 VBSL/VBSLQ output:
1570 VBSL/VBSLQ:0:result_int8x8 [] = { fffffff2, fffffff2, fffffff2, fffffff2, fffffff6, fffffff6, fffff…
1571 VBSL/VBSLQ:1:result_int16x4 [] = { fffffff0, fffffff0, fffffff2, fffffff2, }
1572 VBSL/VBSLQ:2:result_int32x2 [] = { fffffff0, fffffff0, }
1573 VBSL/VBSLQ:3:result_int64x1 [] = { fffffffffffffffd, }
1574 VBSL/VBSLQ:4:result_uint8x8 [] = { f3, f3, f3, f3, f7, f7, f7, f7, }
1575 VBSL/VBSLQ:5:result_uint16x4 [] = { fff0, fff0, fff2, fff2, }
1576 VBSL/VBSLQ:6:result_uint32x2 [] = { fffffff0, fffffff0, }
1577 VBSL/VBSLQ:7:result_uint64x1 [] = { fffffff1, }
1578 VBSL/VBSLQ:8:result_poly8x8 [] = { f3, f3, f3, f3, f7, f7, f7, f7, }
[all …]
|
| D | expected_input4gcc-nofp16.txt | 1384 VBSL/VBSLQ output:
|
| D | expected_input4gcc.txt | 1476 VBSL/VBSLQ output:
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 186 VBSL, enumerator
|
| D | ARMScheduleSwift.td | 546 "VBIT", "VBSL", "VSLI", "VSRI", "VCLS", "VCLZ", "VCNT")>;
|
| D | ARMInstrNEON.td | 555 def NEONvbsl : SDNode<"ARMISD::VBSL",
5009 // VBSL : Vector Bitwise Select
5085 // like VBSL but with: "vbif $dst, $src3, $src1", "$src2 = $dst",
5099 // like VBSL but with: "vbit $dst, $src2, $src1", "$src3 = $dst",
8110 // VBIF, VBIT, and VBSL allow, but do not require, a type suffix.
|
| D | ARMScheduleA9.td | 2402 // VADD/VAND/VORR/VEOR/VBIC/VORN/VBIT/VBIF/VBSL
|
| D | ARMISelLowering.cpp | 1225 case ARMISD::VBSL: return "ARMISD::VBSL"; in getTargetNodeName()
9333 SDValue Result = DAG.getNode(ARMISD::VBSL, dl, CanonicalVT, in PerformORCombine()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 230 VBSL, enumerator
|
| D | ARMScheduleR52.td | 791 def : InstRW<[R52WriteFPALU_F3, R52Read_F1, R52Read_F2, R52Read_F2], (instregex "(VBIF|VBIT|VBSL)d"…
792 def : InstRW<[R52Write2FPALU_F3, R52Read_F1, R52Read_F2, R52Read_F2], (instregex "(VBIF|VBIT|VBSL)q…
|
| D | ARMScheduleSwift.td | 563 "VBIT", "VBSL", "VSLI", "VSRI", "VCLS", "VCLZ", "VCNT")>;
|
| D | ARMScheduleA57.td | 1201 def : InstRW<[A57Write_3cyc_1V], (instregex "VBIF", "VBIT", "VBSL")>;
|
| D | ARMInstrNEON.td | 545 def NEONvbsl : SDNode<"ARMISD::VBSL",
5283 // VBSL : Vector Bitwise Select
5359 // like VBSL but with: "vbif $dst, $src3, $src1", "$src2 = $dst",
5373 // like VBSL but with: "vbit $dst, $src2, $src1", "$src3 = $dst",
8474 // VBIF, VBIT, and VBSL allow, but do not require, a type suffix.
|
| D | ARMScheduleA9.td | 2426 // VADD/VAND/VORR/VEOR/VBIC/VORN/VBIT/VBIF/VBSL
|
| D | ARMISelLowering.cpp | 1366 case ARMISD::VBSL: return "ARMISD::VBSL"; in getTargetNodeName()
11065 SDValue Result = DAG.getNode(ARMISD::VBSL, dl, CanonicalVT, in PerformORCombine()
|
| /external/v8/src/arm/ |
| D | assembler-arm.cc | 4192 enum BinaryBitwiseOp { VAND, VBIC, VBIF, VBIT, VBSL, VEOR, VORR, VORN }; enumerator
4208 case VBSL: in EncodeNeonBinaryBitwiseOp()
4252 emit(EncodeNeonBinaryBitwiseOp(VBSL, NEON_Q, dst.code(), src1.code(), in vbsl()
|
| /external/clang/include/clang/Basic/ |
| D | arm_neon.td | 808 def VBSL : SInst<"vbsl", "dudd",
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/ |
| D | ARMGenDAGISel.inc | 38619 /* 85224*/ /*SwitchOpcode*/ 47, TARGET_VAL(ARMISD::VBSL),// ->85274
|