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Searched refs:getInstr (Results 1 – 25 of 98) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonSubtarget.cpp147 MachineInstr &MI1 = *SU.getInstr(); in apply()
156 MachineInstr &MI2 = *SI.getSUnit()->getInstr(); in apply()
184 if (Inst1.getInstr()->getOpcode() != Hexagon::A2_tfrpi) in shouldTFRICallBind()
188 unsigned Type = HII.getType(*Inst2.getInstr()); in shouldTFRICallBind()
208 if (DAG->SUnits[su].getInstr()->isCall()) in apply()
211 else if (DAG->SUnits[su].getInstr()->isCompare() && LastSequentialCall) in apply()
232 const MachineInstr *MI = DAG->SUnits[su].getInstr(); in apply()
275 MachineInstr &L0 = *S0.getInstr(); in apply()
288 MachineInstr &L1 = *S1.getInstr(); in apply()
322 MachineInstr *SrcInst = Src->getInstr(); in adjustSchedDependency()
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DHexagonMachineScheduler.cpp75 if (QII.mayBeCurLoad(*SUd->getInstr())) in hasDependence()
78 if (QII.canExecuteInBundle(*SUd->getInstr(), *SUu->getInstr())) in hasDependence()
99 if (!SU || !SU->getInstr()) in isResourceAvailable()
104 switch (SU->getInstr()->getOpcode()) { in isResourceAvailable()
106 if (!ResourcesModel->canReserveResources(*SU->getInstr())) in isResourceAvailable()
119 MachineBasicBlock *MBB = SU->getInstr()->getParent(); in isResourceAvailable()
157 switch (SU->getInstr()->getOpcode()) { in reserveResources()
159 ResourcesModel->reserveResources(*SU->getInstr()); in reserveResources()
180 LLVM_DEBUG(Packet[i]->getInstr()->dump()); in reserveResources()
308 assert(SU->getInstr() && "Scheduled SUnit must have instr"); in releaseBottomNode()
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DHexagonHazardRecognizer.cpp41 MachineInstr *MI = SU->getInstr(); in getHazardType()
104 if (UsesLoad && SU->isInstr() && SU->getInstr()->mayLoad()) in ShouldPreferAnother()
110 MachineInstr *MI = SU->getInstr(); in EmitInstruction()
161 TII->mayBeNewStore(*S.getSUnit()->getInstr()) && in EmitInstruction()
162 Resources->canReserveResources(*S.getSUnit()->getInstr())) { in EmitInstruction()
DHexagonVLIWPacketizer.cpp413 if (PacketSU->getInstr()->isInlineAsm()) in canPromoteToDotCur()
507 assert(SUI->getInstr() && SUJ->getInstr()); in updateOffset()
508 MachineInstr &MI = *SUI->getInstr(); in updateOffset()
509 MachineInstr &MJ = *SUJ->getInstr(); in updateOffset()
664 if (PacketSU->getInstr()->mayStore()) in canPromoteToNewValueStore()
750 MachineInstr &TempMI = *TempSU->getInstr(); in canPromoteToNewValueStore()
763 if (MO.isReg() && TempSU->getInstr()->modifiesRegister(MO.getReg(), HRI)) in canPromoteToNewValueStore()
817 MachineInstr &PacketMI = *PacketSU->getInstr(); in canPromoteToNewValue()
854 const MachineInstr &PI = *PacketSU->getInstr(); in canPromoteToDotNew()
1312 assert(SUI->getInstr() && SUJ->getInstr()); in isLegalToPacketizeTogether()
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DHexagonISelLoweringHVX.cpp405 SDValue HalfV0 = getInstr(Hexagon::V6_vd0, dl, VecTy, {}, DAG); in buildHvxVectorReg()
406 SDValue HalfV1 = getInstr(Hexagon::V6_vd0, dl, VecTy, {}, DAG); in buildHvxVectorReg()
455 SDValue Q = getInstr(Hexagon::V6_pred_scalar2, dl, BoolTy, in createHvxPrefixPred()
625 return getInstr(Hexagon::C2_cmpgtui, dl, MVT::i1, {ExtB, Zero}, DAG); in extractHvxElementPred()
794 return getInstr(Hexagon::A4_vcmpbgtui, dl, ResTy, in extractHvxSubvectorPred()
918 SDValue Q = getInstr(Hexagon::V6_pred_scalar2, dl, BoolTy, in insertHvxSubvectorPred()
920 ByteVec = getInstr(Hexagon::V6_vmux, dl, ByteTy, {Q, ByteSub, ByteVec}, DAG); in insertHvxSubvectorPred()
1215 SDValue M = getInstr(MpyOpc, dl, ExtTy, {Vs, Vt}, DAG); in LowerHvxMul()
1230 return getInstr(Hexagon::V6_vmpyih, dl, ResTy, {Vs, Vt}, DAG); in LowerHvxMul()
1237 SDValue T0 = getInstr(Hexagon::V6_vmpyiowh, dl, ResTy, {Vs, Vt}, DAG); in LowerHvxMul()
[all …]
/external/llvm/lib/Target/Hexagon/
DHexagonMachineScheduler.cpp30 if (SUnits[su].getInstr()->isCall()) in postprocessDAG()
33 else if (SUnits[su].getInstr()->isCompare() && LastSequentialCall) in postprocessDAG()
44 if (!SU || !SU->getInstr()) in isResourceAvailable()
49 switch (SU->getInstr()->getOpcode()) { in isResourceAvailable()
51 if (!ResourcesModel->canReserveResources(*SU->getInstr())) in isResourceAvailable()
101 switch (SU->getInstr()->getOpcode()) { in reserveResources()
103 ResourcesModel->reserveResources(*SU->getInstr()); in reserveResources()
124 DEBUG(Packet[i]->getInstr()->dump()); in reserveResources()
249 assert(SU->getInstr() && "Scheduled SUnit must have instr"); in releaseBottomNode()
281 unsigned uops = SchedModel->getNumMicroOps(SU->getInstr()); in checkHazard()
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DHexagonVLIWPacketizer.cpp382 if (PacketSU->getInstr()->isInlineAsm()) in canPromoteToDotCur()
553 if (PacketSU->getInstr()->mayStore()) in canPromoteToNewValueStore()
639 MachineInstr* TempMI = TempSU->getInstr(); in canPromoteToNewValueStore()
652 if (MO.isReg() && TempSU->getInstr()->modifiesRegister(MO.getReg(), HRI)) in canPromoteToNewValueStore()
704 MachineInstr *PacketMI = PacketSU->getInstr(); in canPromoteToNewValue()
735 const MachineInstr *PI = PacketSU->getInstr(); in canPromoteToDotNew()
1136 MachineInstr *I = SUI->getInstr(); in isLegalToPacketizeTogether()
1137 MachineInstr *J = SUJ->getInstr(); in isLegalToPacketizeTogether()
1179 MachineInstr *PI = PacketSU->getInstr(); in isLegalToPacketizeTogether()
1448 MachineInstr *I = SUI->getInstr(); in isLegalToPruneDependencies()
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/external/llvm/lib/Target/AMDGPU/
DR600MachineScheduler.cpp163 for (MachineInstr::mop_iterator It = SU->getInstr()->operands_begin(), in schedNode()
164 E = SU->getInstr()->operands_end(); It != E; ++It) { in schedNode()
198 if (isPhysicalRegCopy(SU->getInstr())) { in releaseBottomNode()
223 MachineInstr *MI = SU->getInstr(); in getAluKind()
296 int Opcode = SU->getInstr()->getOpcode(); in getInstKind()
325 InstructionsGroupCandidate.push_back(SU->getInstr()); in PopInst()
327 (!AnyALU || !TII->isVectorOnly(*SU->getInstr()))) { in PopInst()
396 AssignSlot(UnslotedSU->getInstr(), Slot); in AttemptFillSlot()
445 InstructionsGroupCandidate.push_back(SU->getInstr()); in pickAlu()
DGCNHazardRecognizer.cpp34 EmitInstruction(SU->getInstr()); in EmitInstruction()
43 MachineInstr *MI = SU->getInstr(); in getHazardType()
58 return PreEmitNoops(SU->getInstr()); in PreEmitNoops()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DR600MachineScheduler.cpp162 for (MachineInstr::mop_iterator It = SU->getInstr()->operands_begin(), in schedNode()
163 E = SU->getInstr()->operands_end(); It != E; ++It) { in schedNode()
196 if (isPhysicalRegCopy(SU->getInstr())) { in releaseBottomNode()
221 MachineInstr *MI = SU->getInstr(); in getAluKind()
295 int Opcode = SU->getInstr()->getOpcode(); in getInstKind()
324 InstructionsGroupCandidate.push_back(SU->getInstr()); in PopInst()
326 (!AnyALU || !TII->isVectorOnly(*SU->getInstr()))) { in PopInst()
395 AssignSlot(UnslotedSU->getInstr(), Slot); in AttemptFillSlot()
444 InstructionsGroupCandidate.push_back(SU->getInstr()); in pickAlu()
DSIMachineScheduler.cpp272 TopRPTracker.getDownwardPressure(SU->getInstr(), pressure, MaxPressure); in pickNode()
339 RPTracker.setPos(SU->getInstr()); in initRegPressure()
420 TopRPTracker.setPos(SU->getInstr()); in schedule()
1156 if (SIInstrInfo::isEXP(*SU.getInstr())) { in colorExports()
1180 if (!SIInstrInfo::isEXP(*DAG->SUnits[k].getInstr())) in colorExports()
1365 MachineInstr *MI = SU->getInstr(); in scheduleInsideBlocks()
1394 Block->schedule((*SUs.begin())->getInstr(), (*SUs.rbegin())->getInstr()); in scheduleInsideBlocks()
1845 if (SITII->isLowLatencyInstruction(*Pred->getInstr())) { in moveLowLatencies()
1855 if (SITII->isLowLatencyInstruction(*SU->getInstr())) { in moveLowLatencies()
1876 } else if (SU->getInstr()->getOpcode() == AMDGPU::COPY) { in moveLowLatencies()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DMacroFusion.cpp72 dbgs() << DAG.TII->getName(FirstSU.getInstr()->getOpcode()) << " - " in fuseInstructionPair()
73 << DAG.TII->getName(SecondSU.getInstr()->getOpcode()) << '\n';); in fuseInstructionPair()
141 if (DAG->ExitSU.getInstr()) in apply()
149 const MachineInstr &AnchorMI = *AnchorSU.getInstr(); in scheduleAdjacentImpl()
167 const MachineInstr *DepMI = DepSU.getInstr(); in scheduleAdjacentImpl()
DSlotIndexes.cpp115 assert(MIEntry.getInstr() == &MI && "Instruction indexes broken."); in removeMachineInstrFromMaps()
128 assert(MIEntry.getInstr() == &MI && "Instruction indexes broken."); in removeSingleMachineInstrFromMaps()
221 MachineInstr *SlotMI = ListI->getInstr(); in repairIndexesInRange()
259 if (itr->getInstr()) { in dump()
260 dbgs() << *itr->getInstr(); in dump()
DScheduleDAGInstrs.cpp231 const MachineOperand &MO = SU->getInstr()->getOperand(OperIdx); in addPhysRegDataDeps()
258 RegUse = UseSU->getInstr(); in addPhysRegDataDeps()
261 SchedModel.computeOperandLatency(SU->getInstr(), OperIdx, RegUse, in addPhysRegDataDeps()
274 MachineInstr *MI = SU->getInstr(); in addPhysRegDeps()
297 !DefSU->getInstr()->registerDefIsDead(*Alias))) { in addPhysRegDeps()
303 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr())); in addPhysRegDeps()
371 MachineInstr *MI = SU->getInstr(); in addVRegDefDeps()
409 MachineInstr *Use = UseSU->getInstr(); in addVRegDefDeps()
455 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr())); in addVRegDefDeps()
480 const MachineInstr *MI = SU->getInstr(); in addVRegUseDeps()
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DMachineScheduler.cpp767 LLVM_DEBUG(if (EntrySU.getInstr() != nullptr) EntrySU.dumpAll(this); in schedule()
770 if (ExitSU.getInstr() != nullptr) ExitSU.dumpAll(this);); in schedule()
790 MachineInstr *MI = SU->getInstr(); in schedule()
940 const MachineInstr &MI = *SU.getInstr(); in collectVRegUses()
1131 << PrintLaneMask(P.LaneMask) << ' ' << *SU.getInstr(); in updatePressureDiffs()
1160 LI.Query(LIS->getInstructionIndex(*SU->getInstr())); in updatePressureDiffs()
1165 << *SU->getInstr(); in updatePressureDiffs()
1200 LLVM_DEBUG(if (EntrySU.getInstr() != nullptr) EntrySU.dumpAll(this); in schedule()
1209 if (SchedModel.mustBeginGroup(SU.getInstr()) && in schedule()
1210 SchedModel.mustEndGroup(SU.getInstr())) in schedule()
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DMachinePipeliner.cpp349 return Source->getInstr()->isPHI() || Dep.getSUnit()->getInstr()->isPHI(); in isBackedge()
359 if (V->getInstr()->isPHI() && Dep.getKind() == SDep::Anti) in getDistance()
564 os << " SU(" << I->NodeNum << ") " << *(I->getInstr()); in print()
1075 MachineInstr &MI = *SU.getInstr(); in addLoopCarriedDependences()
1100 MachineInstr &LdMI = *Load->getInstr(); in addLoopCarriedDependences()
1174 MachineInstr *MI = I.getInstr(); in updatePhiDependences()
1230 MachineInstr *PMI = PI.getSUnit()->getInstr(); in updatePhiDependences()
1232 if (I.getInstr()->isPHI()) { in updatePhiDependences()
1255 if (!canUseLastOffsetValue(I.getInstr(), BasePos, OffsetPos, NewBase, in changeDependences()
1260 unsigned OrigBase = I.getInstr()->getOperand(BasePos).getReg(); in changeDependences()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/
DSystemZHazardRecognizer.cpp106 if (CurrGroupSize == 2 && has4RegOps(SU->getInstr())) in fitsIntoCurrentGroup()
165 OS << TII->getName(SU->getInstr()->getOpcode()); in dumpSU()
200 if (has4RegOps(SU->getInstr())) in dumpSU()
281 LastEmittedMI = SU->getInstr(); in EmitInstruction()
287 LastEmittedMI = SU->getInstr(); in EmitInstruction()
325 CurrGroupHas4RegOps |= has4RegOps(SU->getInstr()); in EmitInstruction()
360 if (CurrGroupSize == 2 && has4RegOps(SU->getInstr())) in groupingCost()
/external/swiftshader/third_party/LLVM/lib/CodeGen/
DScheduleDAGInstrs.cpp281 !DefSU->getInstr()->registerDefIsDead(Reg))) in BuildSchedGraph()
292 !DefSU->getInstr()->registerDefIsDead(*Alias))) in BuildSchedGraph()
313 MachineInstr *UseMI = UseSU->getInstr(); in BuildSchedGraph()
579 if (SU->getInstr()->getDesc().mayLoad()) in ComputeLatency()
582 SU->Latency = TII->getInstrLatency(InstrItins, SU->getInstr()); in ComputeLatency()
599 MachineInstr *DefMI = Def->getInstr(); in ComputeOperandLatency()
613 MachineInstr *UseMI = Use->getInstr(); in ComputeOperandLatency()
644 SU->getInstr()->dump(); in dumpNode()
655 SU->getInstr()->print(oss); in getGraphNodeLabel()
676 BB->insert(InsertPos, SU->getInstr()); in EmitSchedule()
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/external/llvm/lib/CodeGen/
DMachinePipeliner.cpp295 return Source->getInstr()->isPHI() || Dep.getSUnit()->getInstr()->isPHI(); in isBackedge()
302 return (!Source->getInstr()->isPHI() && in isOrder()
303 !Dep.getSUnit()->getInstr()->isPHI()); in isOrder()
313 if (Source->getInstr()->isPHI()) in getLatency()
315 if (Dep.getSUnit()->getInstr()->isPHI()) in getLatency()
327 if (V->getInstr()->isPHI() && Dep.getKind() == SDep::Anti) in getDistance()
515 os << " SU(" << I->NodeNum << ") " << *(I->getInstr()); in print()
999 MachineInstr &MI = *SU.getInstr(); in addLoopCarriedDependences()
1020 MachineInstr &LdMI = *Load->getInstr(); in addLoopCarriedDependences()
1085 MachineInstr *MI = I.getInstr(); in updatePhiDependences()
[all …]
DScheduleDAGInstrs.cpp284 const MachineOperand &MO = SU->getInstr()->getOperand(OperIdx); in addPhysRegDataDeps()
311 RegUse = UseSU->getInstr(); in addPhysRegDataDeps()
314 SchedModel.computeOperandLatency(SU->getInstr(), OperIdx, RegUse, in addPhysRegDataDeps()
327 MachineInstr *MI = SU->getInstr(); in addPhysRegDeps()
347 !DefSU->getInstr()->registerDefIsDead(*Alias))) { in addPhysRegDeps()
353 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr())); in addPhysRegDeps()
422 MachineInstr *MI = SU->getInstr(); in addVRegDefDeps()
460 MachineInstr *Use = UseSU->getInstr(); in addVRegDefDeps()
506 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr())); in addVRegDefDeps()
531 const MachineInstr *MI = SU->getInstr(); in addVRegUseDeps()
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DMachineScheduler.cpp712 MachineInstr *MI = SU->getInstr(); in schedule()
1015 << ' ' << *SU.getInstr(); in updatePressureDiffs()
1046 LI.Query(LIS->getInstructionIndex(*SU->getInstr())); in updatePressureDiffs()
1052 << *SU->getInstr(); in updatePressureDiffs()
1233 LiveQueryResult LRQ = LI.Query(LIS->getInstructionIndex(*SU->getInstr())); in computeCyclicCriticalPath()
1275 MachineInstr *MI = SU->getInstr(); in scheduleMI()
1405 if (TII->getMemOpBaseRegImmOfs(*SU->getInstr(), BaseReg, Offset, TRI)) in clusterNeighboringMemOps()
1421 if (TII->shouldClusterMemOps(*SUa->getInstr(), *SUb->getInstr(), in clusterNeighboringMemOps()
1454 if ((IsLoad && !SU->getInstr()->mayLoad()) || in apply()
1455 (!IsLoad && !SU->getInstr()->mayStore())) in apply()
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DSlotIndexes.cpp179 MachineInstr *SlotMI = ListI->getInstr(); in repairIndexesInRange()
217 if (itr->getInstr()) { in dump()
218 dbgs() << *itr->getInstr(); in dump()
/external/llvm/lib/Target/ARM/
DARMHazardRecognizer.cpp38 MachineInstr *MI = SU->getInstr(); in getHazardType()
83 MachineInstr *MI = SU->getInstr(); in EmitInstruction()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMHazardRecognizer.cpp38 MachineInstr *MI = SU->getInstr(); in getHazardType()
83 MachineInstr *MI = SU->getInstr(); in EmitInstruction()
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMHazardRecognizer.cpp38 MachineInstr *MI = SU->getInstr(); in getHazardType()
84 MachineInstr *MI = SU->getInstr(); in EmitInstruction()

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