| /external/swiftshader/third_party/LLVM/include/llvm/Target/ |
| D | TargetCallingConv.h | 56 bool isInReg() const { return Flags & InReg; } in isInReg() function
|
| D | TargetCallingConv.td | 51 class CCIfInReg<CCAction A> : CCIf<"ArgFlags.isInReg()", A> {}
|
| D | TargetLowering.h | 1213 bool isInReg : 1; member
1219 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false), in ArgListEntry()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | TargetCallingConv.h | 69 bool isInReg() const { return IsInReg; } in isInReg() function
|
| /external/llvm/include/llvm/Target/ |
| D | TargetCallingConv.h | 76 bool isInReg() const { return Flags & InReg; } in isInReg() function
|
| D | TargetCallingConv.td | 66 class CCIfInReg<CCAction A> : CCIf<"ArgFlags.isInReg()", A> {}
|
| D | TargetLowering.h | 2466 bool isInReg : 1; member
2476 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false), in ArgListEntry()
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
| D | MipsGenCallingConv.inc | 118 if (ArgFlags.isInReg()) {
274 if (ArgFlags.isInReg()) {
640 if (ArgFlags.isInReg()) {
715 if (ArgFlags.isInReg()) {
732 if (ArgFlags.isInReg()) {
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUCallLowering.cpp | 193 !OrigArg.Flags.isInReg() && !OrigArg.Flags.isByVal() && in lowerFormalArguments()
|
| D | AMDGPUCallingConv.td | 15 class CCIfNotInReg<CCAction A> : CCIf<"!ArgFlags.isInReg()", A> {}
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUCallingConv.td | 15 class CCIfNotInReg<CCAction A> : CCIf<"!ArgFlags.isInReg()", A> {}
|
| D | SIISelLowering.cpp | 619 if (CallConv == CallingConv::AMDGPU_PS && !Arg.Flags.isInReg() && in LowerFormalArguments()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Target/ |
| D | TargetCallingConv.td | 66 class CCIfInReg<CCAction A> : CCIf<"ArgFlags.isInReg()", A> {}
|
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86GenCallingConv.inc | 141 if (ArgFlags.isInReg()) {
171 if (ArgFlags.isInReg()) {
918 if (ArgFlags.isInReg()) {
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGBuilder.cpp | 5168 Entry.isInReg = false; in LowerCallTo()
5191 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg); in LowerCallTo()
5601 void MarkAllocatedRegs(bool isOutReg, bool isInReg, in MarkAllocatedRegs() argument
5609 if (isInReg) { in MarkAllocatedRegs()
5700 bool isInReg = false; in GetRegistersForValue() local
5707 isInReg = OpInfo.hasMatchingInput(); in GetRegistersForValue()
5710 isInReg = true; in GetRegistersForValue()
5715 isInReg = true; in GetRegistersForValue()
5794 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI); in GetRegistersForValue()
6354 if (Args[i].isInReg) in LowerCallTo()
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/X86/ |
| D | X86GenCallingConv.inc | 396 if (ArgFlags.isInReg()) {
426 if (ArgFlags.isInReg()) {
640 if (ArgFlags.isInReg()) {
652 if (ArgFlags.isInReg()) {
664 if (ArgFlags.isInReg()) {
2861 if (ArgFlags.isInReg()) {
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsFastISel.cpp | 1282 if (Flag.isInReg() || Flag.isSRet() || Flag.isNest() || Flag.isByVal()) in fastLowerCall()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsFastISel.cpp | 1501 if (Flag.isInReg() || Flag.isSRet() || Flag.isNest() || Flag.isByVal()) in fastLowerCall()
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCFastISel.cpp | 1523 if (Flags.isInReg() || Flags.isSRet() || Flags.isNest() || Flags.isByVal()) in fastLowerCall()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCFastISel.cpp | 1610 if (Flags.isInReg() || Flags.isSRet() || Flags.isNest() || Flags.isByVal()) in fastLowerCall()
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGBuilder.cpp | 2066 Entry.isInReg = true; in visitSPDescriptorParent()
7516 Entry.isInReg = false; in LowerCallTo()
7589 if (Args[i].isInReg) in LowerCallTo()
|
| D | TargetLowering.cpp | 103 isInReg = CS->paramHasAttr(AttrIdx, Attribute::InReg); in setAttributes()
|
| /external/llvm/lib/Target/X86/ |
| D | X86FastISel.cpp | 3360 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) { in fastLowerCall()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86FastISel.cpp | 3576 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) { in fastLowerCall()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 3181 if (Flag.isInReg() || Flag.isSRet() || Flag.isNest() || Flag.isByVal() || in fastLowerCall()
|