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/external/v8/src/wasm/
Dwasm-opcodes.h29 #define FOREACH_CONTROL_OPCODE(V) \ argument
30 V(Unreachable, 0x00, _) \
31 V(Nop, 0x01, _) \
32 V(Block, 0x02, _) \
33 V(Loop, 0x03, _) \
34 V(If, 0x04, _) \
35 V(Else, 0x05, _) \
36 V(Try, 0x06, _ /* eh_prototype */) \
37 V(Catch, 0x07, _ /* eh_prototype */) \
38 V(Throw, 0x08, _ /* eh_prototype */) \
[all …]
/external/angle/third_party/glslang/src/Test/baseResults/
Dspv.vulkan100.subgroupPartitioned.comp.out2 ERROR: 0:19: 'subgroup op' : requires SPIR-V 1.3
3 ERROR: 0:21: 'subgroup op' : requires SPIR-V 1.3
4 ERROR: 0:22: 'subgroup op' : requires SPIR-V 1.3
5 ERROR: 0:23: 'subgroup op' : requires SPIR-V 1.3
6 ERROR: 0:24: 'subgroup op' : requires SPIR-V 1.3
7 ERROR: 0:26: 'subgroup op' : requires SPIR-V 1.3
8 ERROR: 0:27: 'subgroup op' : requires SPIR-V 1.3
9 ERROR: 0:28: 'subgroup op' : requires SPIR-V 1.3
10 ERROR: 0:29: 'subgroup op' : requires SPIR-V 1.3
11 ERROR: 0:31: 'subgroup op' : requires SPIR-V 1.3
[all …]
Dspv.vulkan100.subgroupArithmetic.comp.out2 ERROR: 0:19: 'subgroup op' : requires SPIR-V 1.3
3 ERROR: 0:20: 'subgroup op' : requires SPIR-V 1.3
4 ERROR: 0:21: 'subgroup op' : requires SPIR-V 1.3
5 ERROR: 0:22: 'subgroup op' : requires SPIR-V 1.3
6 ERROR: 0:24: 'subgroup op' : requires SPIR-V 1.3
7 ERROR: 0:25: 'subgroup op' : requires SPIR-V 1.3
8 ERROR: 0:26: 'subgroup op' : requires SPIR-V 1.3
9 ERROR: 0:27: 'subgroup op' : requires SPIR-V 1.3
10 ERROR: 0:29: 'subgroup op' : requires SPIR-V 1.3
11 ERROR: 0:30: 'subgroup op' : requires SPIR-V 1.3
[all …]
/external/deqp-deps/glslang/Test/baseResults/
Dspv.vulkan100.subgroupPartitioned.comp.out2 ERROR: 0:19: 'subgroup op' : requires SPIR-V 1.3
3 ERROR: 0:21: 'subgroup op' : requires SPIR-V 1.3
4 ERROR: 0:22: 'subgroup op' : requires SPIR-V 1.3
5 ERROR: 0:23: 'subgroup op' : requires SPIR-V 1.3
6 ERROR: 0:24: 'subgroup op' : requires SPIR-V 1.3
7 ERROR: 0:26: 'subgroup op' : requires SPIR-V 1.3
8 ERROR: 0:27: 'subgroup op' : requires SPIR-V 1.3
9 ERROR: 0:28: 'subgroup op' : requires SPIR-V 1.3
10 ERROR: 0:29: 'subgroup op' : requires SPIR-V 1.3
11 ERROR: 0:31: 'subgroup op' : requires SPIR-V 1.3
[all …]
Dspv.vulkan100.subgroupArithmetic.comp.out2 ERROR: 0:19: 'subgroup op' : requires SPIR-V 1.3
3 ERROR: 0:20: 'subgroup op' : requires SPIR-V 1.3
4 ERROR: 0:21: 'subgroup op' : requires SPIR-V 1.3
5 ERROR: 0:22: 'subgroup op' : requires SPIR-V 1.3
6 ERROR: 0:24: 'subgroup op' : requires SPIR-V 1.3
7 ERROR: 0:25: 'subgroup op' : requires SPIR-V 1.3
8 ERROR: 0:26: 'subgroup op' : requires SPIR-V 1.3
9 ERROR: 0:27: 'subgroup op' : requires SPIR-V 1.3
10 ERROR: 0:29: 'subgroup op' : requires SPIR-V 1.3
11 ERROR: 0:30: 'subgroup op' : requires SPIR-V 1.3
[all …]
/external/libxml2/result/noent/
Datt48 <val o="0" v="53"/>
9 <val o="e08" v="53"/>
10 <val o="1c32" v="53"/>
11 <val o="2a3c" v="53"/>
12 <val o="3835" v="53"/>
13 <val o="4645" v="53"/>
14 <val o="5455" v="53"/>
15 <val o="6265" v="53"/>
16 <val o="7075" v="53"/>
17 <val o="7e85" v="53"/>
[all …]
/external/libxml2/test/
Datt48 <val o="0" v="53"/>
9 <val o="e08" v="53"/>
10 <val o="1c32" v="53"/>
11 <val o="2a3c" v="53"/>
12 <val o="3835" v="53"/>
13 <val o="4645" v="53"/>
14 <val o="5455" v="53"/>
15 <val o="6265" v="53"/>
16 <val o="7075" v="53"/>
17 <val o="7e85" v="53"/>
[all …]
/external/libxml2/result/
Datt48 <val o="0" v="53"/>
9 <val o="e08" v="53"/>
10 <val o="1c32" v="53"/>
11 <val o="2a3c" v="53"/>
12 <val o="3835" v="53"/>
13 <val o="4645" v="53"/>
14 <val o="5455" v="53"/>
15 <val o="6265" v="53"/>
16 <val o="7075" v="53"/>
17 <val o="7e85" v="53"/>
[all …]
/external/v8/src/codegen/x64/
Dsse-instr.h9 #define SSE_UNOP_INSTRUCTION_LIST(V) \ argument
10 V(sqrtps, 0F, 51) \
11 V(rsqrtps, 0F, 52) \
12 V(rcpps, 0F, 53) \
13 V(cvtdq2ps, 0F, 5B)
16 #define SSE_BINOP_INSTRUCTION_LIST(V) \ argument
17 V(andps, 0F, 54) \
18 V(andnps, 0F, 55) \
19 V(orps, 0F, 56) \
20 V(xorps, 0F, 57) \
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AMDGPU/
Dflat.s18 flat_load_dword v1, v[3:4]
20 // CI: flat_load_dword v1, v[3:4] ; encoding: [0x00,0x00,0x30,0xdc,0x03,0x00,0x00,0x01]
21 // VI: flat_load_dword v1, v[3:4] ; encoding: [0x00,0x00,0x50,0xdc,0x03,0x00,0x00,0x01]
23 flat_load_dword v1, v[3:4] glc
25 // CI: flat_load_dword v1, v[3:4] glc ; encoding: [0x00,0x00,0x31,0xdc,0x03,0x00,0x00,0x01]
26 // VI: flat_load_dword v1, v[3:4] glc ; encoding: [0x00,0x00,0x51,0xdc,0x03,0x00,0x00,0x01]
28 flat_load_dword v1, v[3:4] glc slc
30 // CI: flat_load_dword v1, v[3:4] glc slc ; encoding: [0x00,0x00,0x33,0xdc,0x03,0x00,0x00,0x01]
31 // VI: flat_load_dword v1, v[3:4] glc slc ; encoding: [0x00,0x00,0x53,0xdc,0x03,0x00,0x00,0x01]
33 flat_store_dword v[3:4], v1
[all …]
Dflat-global.s5 global_load_ubyte v1, v[3:4], off
6 // GFX9: global_load_ubyte v1, v[3:4], off ; encoding: [0x00,0x80,0x40,0xdc,0x03,0x00,0x7f,0x01]
9 global_load_sbyte v1, v[3:4], off
10 // GFX9: global_load_sbyte v1, v[3:4], off ; encoding: [0x00,0x80,0x44,0xdc,0x03,0x00,0x7f,0x01]
13 global_load_ushort v1, v[3:4], off
14 // GFX9: global_load_ushort v1, v[3:4], off ; encoding: [0x00,0x80,0x48,0xdc,0x03,0x00,0x7f,0x01]
17 global_load_sshort v1, v[3:4], off
18 // GFX9: global_load_sshort v1, v[3:4], off ; encoding: [0x00,0x80,0x4c,0xdc,0x03,0x00,0x7f,0x01]
21 global_load_dword v1, v[3:4], off
22 // GFX9: global_load_dword v1, v[3:4], off ; encoding: [0x00,0x80,0x50,0xdc,0x03,0x00,0x7f,0x01]
[all …]
/external/u-boot/arch/arm/include/asm/arch-vf610/
Dimx-regs.h11 #define IRAM_BASE_ADDR 0x3F000000 /* internal ram */
12 #define IRAM_SIZE 0x00080000 /* 512 KB */
14 #define AIPS0_BASE_ADDR 0x40000000
15 #define AIPS1_BASE_ADDR 0x40080000
17 /* AIPS 0 */
18 #define MSCM_BASE_ADDR (AIPS0_BASE_ADDR + 0x00001000)
19 #define MSCM_IR_BASE_ADDR (AIPS0_BASE_ADDR + 0x00001800)
20 #define CA5SCU_BASE_ADDR (AIPS0_BASE_ADDR + 0x00002000)
21 #define CA5_INTD_BASE_ADDR (AIPS0_BASE_ADDR + 0x00003000)
22 #define CA5_L2C_BASE_ADDR (AIPS0_BASE_ADDR + 0x00006000)
[all …]
/external/u-boot/arch/arm/include/asm/arch-mx5/
Dcrm_regs.h29 u32 ccr; /* 0x0000 */
33 u32 cacrr; /* 0x0010*/
37 u32 cscmr2; /* 0x0020 */
41 u32 cdcdr; /* 0x0030 */
45 u32 cscdr4; /* 0x0040 */
49 u32 ctor; /* 0x0050 */
53 u32 ccosr; /* 0x0060 */
57 u32 CCGR2; /* 0x0070 */
61 u32 CCGR6; /* 0x0080 */
63 u32 CCGR7; /* 0x0084 */
[all …]
/external/libjpeg-turbo/
Djaricom.c32 #define V(i, a, b, c, d) \ macro
39 V( 0, 0x5a1d, 1, 1, 1 ),
40 V( 1, 0x2586, 14, 2, 0 ),
41 V( 2, 0x1114, 16, 3, 0 ),
42 V( 3, 0x080b, 18, 4, 0 ),
43 V( 4, 0x03d8, 20, 5, 0 ),
44 V( 5, 0x01da, 23, 6, 0 ),
45 V( 6, 0x00e5, 25, 7, 0 ),
46 V( 7, 0x006f, 28, 8, 0 ),
47 V( 8, 0x0036, 30, 9, 0 ),
[all …]
/external/v8/src/snapshot/
Dserializer-deserializer.h34 #define UNUSED_SERIALIZER_BYTE_CODES(V) \ argument
35 /* Free range 0x1c..0x1f */ \
36 V(0x1c) V(0x1d) V(0x1e) V(0x1f) \
37 /* Free range 0x20..0x2f */ \
38 V(0x20) V(0x21) V(0x22) V(0x23) V(0x24) V(0x25) V(0x26) V(0x27) \
39 V(0x28) V(0x29) V(0x2a) V(0x2b) V(0x2c) V(0x2d) V(0x2e) V(0x2f) \
40 /* Free range 0x30..0x3f */ \
41 V(0x30) V(0x31) V(0x32) V(0x33) V(0x34) V(0x35) V(0x36) V(0x37) \
42 V(0x38) V(0x39) V(0x3a) V(0x3b) V(0x3c) V(0x3d) V(0x3e) V(0x3f) \
43 /* Free range 0x97..0x9f */ \
[all …]
/external/llvm/test/MC/AMDGPU/
Dflat.s18 flat_load_dword v1, v[3:4]
20 // CI: flat_load_dword v1, v[3:4] ; encoding: [0x00,0x00,0x30,0xdc,0x03,0x00,0x00,0x01]
21 // VI: flat_load_dword v1, v[3:4] ; encoding: [0x00,0x00,0x50,0xdc,0x03,0x00,0x00,0x01]
23 flat_load_dword v1, v[3:4] glc
25 // CI: flat_load_dword v1, v[3:4] glc ; encoding: [0x00,0x00,0x31,0xdc,0x03,0x00,0x00,0x01]
26 // VI: flat_load_dword v1, v[3:4] glc ; encoding: [0x00,0x00,0x51,0xdc,0x03,0x00,0x00,0x01]
28 flat_load_dword v1, v[3:4] glc slc
30 // CI: flat_load_dword v1, v[3:4] glc slc ; encoding: [0x00,0x00,0x33,0xdc,0x03,0x00,0x00,0x01]
31 // VI: flat_load_dword v1, v[3:4] glc slc ; encoding: [0x00,0x00,0x53,0xdc,0x03,0x00,0x00,0x01]
33 flat_load_dword v1, v[3:4] glc tfe
[all …]
/external/v8/src/codegen/ppc/
Dconstants-ppc.h28 #define ABI_USES_FUNCTION_DESCRIPTORS 0
35 #define ABI_PASSES_HANDLES_IN_REGS 0
42 #define ABI_RETURNS_OBJECT_PAIRS_IN_REGS 0
50 #define ABI_CALL_VIA_IP 0
63 constexpr size_t kMaxPCRelativeCodeRangeInMB = 0;
113 eq = 0, // Equal.
140 #define PPC_XX3_OPCODE_LIST(V) \ argument
142 V(xsadddp, XSADDDP, 0xF0000100) \
144 V(xsaddsp, XSADDSP, 0xF0000000) \
146 V(xscmpodp, XSCMPODP, 0xF0000158) \
[all …]
/external/mesa3d/src/amd/compiler/tests/
Dtest_to_hw_instr.cpp50 //~gfx[67]>> p_unit_test 0
51 //~gfx[67]! v1: %0:v[1] = v_xor_b32 %0:v[1], %0:v[0]
52 //~gfx[67]! v1: %0:v[0] = v_xor_b32 %0:v[1], %0:v[0]
53 //~gfx[67]! v1: %0:v[1] = v_xor_b32 %0:v[1], %0:v[0]
54 bld.pseudo(aco_opcode::p_unit_test, Operand(0u));
60 //~gfx[67]! v2b: %0:v[0][16:32] = v_lshlrev_b32 16, %0:v[0][0:16]
61 //~gfx[67]! v1: %0:v[0] = v_alignbyte_b32 %0:v[1][0:16], %0:v[0][16:32], 2
62 //~gfx[67]! v1: %0:v[0] = v_alignbyte_b32 %0:v[0][0:16], %0:v[0][16:32], 2
69 //~gfx[67]! v2b: %0:v[0][16:32] = v_lshlrev_b32 16, %0:v[0][0:16]
70 //~gfx[67]! v1: %0:v[0] = v_alignbyte_b32 %0:v[1][0:16], %0:v[0][16:32], 2
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dllvm.fma.f16.ll8 ; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
9 ; GCN: buffer_load_ushort v[[B_F16:[0-9]+]]
10 ; GCN: buffer_load_ushort v[[C_F16:[0-9]+]]
11 ; SI: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]
12 ; SI: v_cvt_f32_f16_e32 v[[B_F32:[0-9]+]], v[[B_F16]]
13 ; SI: v_cvt_f32_f16_e32 v[[C_F32:[0-9]+]], v[[C_F16]]
14 ; SI: v_fma_f32 v[[R_F32:[0-9]+]], v[[A_F32:[0-9]]], v[[B_F32:[0-9]]], v[[C_F32:[0-9]]]
15 ; SI: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[R_F32]]
16 ; VI: v_fma_f16 v[[R_F16:[0-9]+]], v[[A_F16]], v[[B_F16]], v[[C_F16]]
17 ; GCN: buffer_store_short v[[R_F16]]
[all …]
Dsdwa-peephole.ll1 ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -amdgpu-sdwa-peephole=0 -m…
6 ; NOSDWA: v_lshrrev_b32_e32 v[[DST:[0-9]+]], 16, v{{[0-9]+}}
7 ; NOSDWA: v_add_u32_e32 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v[[DST]]
10 ; VI: v_add_u32_sdwa v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD…
11 ; GFX9: v_add_u32_sdwa v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD sr…
22 ; NOSDWA: v_lshrrev_b32_e32 v[[DST:[0-9]+]], 16, v{{[0-9]+}}
23 ; NOSDWA: v_subrev_u32_e32 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v[[DST]]
26 ; VI: v_subrev_u32_sdwa v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_…
27 ; GFX9: v_sub_u32_sdwa v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD sr…
37 ; NOSDWA: v_lshrrev_b32_e32 v[[DST0:[0-9]+]], 16, v{{[0-9]+}}
[all …]
Dv_mac_f16.ll5 ; GCN: {{buffer|flat}}_load_ushort v[[A_F16:[0-9]+]]
6 ; GCN: {{buffer|flat}}_load_ushort v[[B_F16:[0-9]+]]
7 ; GCN: {{buffer|flat}}_load_ushort v[[C_F16:[0-9]+]]
8 ; SI: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]
9 ; SI: v_cvt_f32_f16_e32 v[[B_F32:[0-9]+]], v[[B_F16]]
10 ; SI: v_cvt_f32_f16_e32 v[[C_F32:[0-9]+]], v[[C_F16]]
11 ; SI: v_mac_f32_e32 v[[C_F32]], v[[A_F32]], v[[B_F32]]
12 ; SI: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[C_F32]]
13 ; SI: buffer_store_short v[[R_F16]]
14 ; VI: v_mac_f16_e32 v[[C_F16]], v[[A_F16]], v[[B_F16]]
[all …]
Dfmul.f16.ll6 ; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
7 ; GCN: buffer_load_ushort v[[B_F16:[0-9]+]]
8 ; SI: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]
9 ; SI: v_cvt_f32_f16_e32 v[[B_F32:[0-9]+]], v[[B_F16]]
10 ; SI: v_mul_f32_e32 v[[R_F32:[0-9]+]], v[[A_F32]], v[[B_F32]]
11 ; SI: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[R_F32]]
12 ; GFX89: v_mul_f16_e32 v[[R_F16:[0-9]+]], v[[A_F16]], v[[B_F16]]
13 ; GCN: buffer_store_short v[[R_F16]]
28 ; GCN: buffer_load_ushort v[[B_F16:[0-9]+]]
29 ; SI: v_cvt_f32_f16_e32 v[[B_F32:[0-9]+]], v[[B_F16]]
[all …]
/external/v8/src/codegen/ia32/
Dsse-instr.h8 #define SSE2_INSTRUCTION_LIST(V) \ argument
9 V(packsswb, 66, 0F, 63) \
10 V(packssdw, 66, 0F, 6B) \
11 V(packuswb, 66, 0F, 67) \
12 V(pmaddwd, 66, 0F, F5) \
13 V(paddb, 66, 0F, FC) \
14 V(paddw, 66, 0F, FD) \
15 V(paddd, 66, 0F, FE) \
16 V(paddq, 66, 0F, D4) \
17 V(paddsb, 66, 0F, EC) \
[all …]
/external/v8/src/codegen/s390/
Dconstants-s390.h67 eq = 0x8, // Equal.
68 ne = 0x7, // Not equal.
69 ge = 0xa, // Greater or equal.
70 lt = 0x4, // Less than.
71 gt = 0x2, // Greater than.
72 le = 0xc, // Less then or equal
73 al = 0xf, // Always.
75 CC_NOP = 0x0, // S390 NOP
76 CC_EQ = 0x08, // S390 condition code 0b1000
77 CC_LT = 0x04, // S390 condition code 0b0100
[all …]
/external/ethtool/
Dde2104x.c88 "0x18: CSR3 (Rx Ring Base Address) 0x%08x\n" in print_ring_addresses()
89 "0x20: CSR4 (Tx Ring Base Address) 0x%08x\n" in print_ring_addresses()
99 "0x40: CSR8 (Missed Frames Counter) 0x%08x\n", csr8); in print_rx_missed()
104 unsigned int rx_missed = csr8 & 0xffff; in print_rx_missed()
117 u32 tmp, v, *data = (u32 *)regs->data; in de21040_dump_regs() local
125 v = data[0]; in de21040_dump_regs()
127 "0x00: CSR0 (Bus Mode) 0x%08x\n" in de21040_dump_regs()
132 v, in de21040_dump_regs()
133 csr0_tap[(v >> 17) & 3], in de21040_dump_regs()
134 v & (1 << 16) ? "Diagnostic" : "Standard", in de21040_dump_regs()
[all …]

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