| /external/libunwind/tests/ |
| D | check-namespace.sh.in | 9 plat=@arch@
14 LIBUNWIND_GENERIC=../src/.libs/libunwind-${plat}.so
75 if [ ${plat} = "arm" ]; then
82 if [ ${plat} = "mips" ]; then
91 match _UL${plat}_create_addr_space
92 match _UL${plat}_destroy_addr_space
93 match _UL${plat}_get_fpreg
94 match _UL${plat}_get_proc_info
95 match _UL${plat}_get_proc_info_by_ip
96 match _UL${plat}_get_proc_name
[all …]
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| /external/u-boot/drivers/clk/altera/ |
| D | clk-arria10.c | 42 struct socfpga_a10_clk_platdata *plat = dev_get_platdata(clk->dev); in socfpga_a10_clk_get_upstream() local
45 if (plat->clks.count == 0) in socfpga_a10_clk_get_upstream()
48 if (plat->clks.count == 1) { in socfpga_a10_clk_get_upstream()
49 *upclk = &plat->clks.clks[0]; in socfpga_a10_clk_get_upstream()
53 if (!plat->ctl_reg) { in socfpga_a10_clk_get_upstream()
58 reg = readl(plat->regs + plat->ctl_reg); in socfpga_a10_clk_get_upstream()
61 if (plat->type == SOCFPGA_A10_CLK_MAIN_PLL) { in socfpga_a10_clk_get_upstream()
64 } else if (plat->type == SOCFPGA_A10_CLK_PER_PLL) { in socfpga_a10_clk_get_upstream()
77 *upclk = &plat->clks.clks[reg]; in socfpga_a10_clk_get_upstream()
83 struct socfpga_a10_clk_platdata *plat = dev_get_platdata(clk->dev); in socfpga_a10_clk_endisable() local
[all …]
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| /external/u-boot/drivers/gpio/ |
| D | dwapb_gpio.c | 44 struct gpio_dwapb_platdata *plat = dev_get_platdata(dev); in dwapb_gpio_direction_input() local
46 clrbits_le32(plat->base + GPIO_SWPORT_DDR(plat->bank), 1 << pin); in dwapb_gpio_direction_input()
53 struct gpio_dwapb_platdata *plat = dev_get_platdata(dev); in dwapb_gpio_direction_output() local
55 setbits_le32(plat->base + GPIO_SWPORT_DDR(plat->bank), 1 << pin); in dwapb_gpio_direction_output()
58 setbits_le32(plat->base + GPIO_SWPORT_DR(plat->bank), 1 << pin); in dwapb_gpio_direction_output()
60 clrbits_le32(plat->base + GPIO_SWPORT_DR(plat->bank), 1 << pin); in dwapb_gpio_direction_output()
67 struct gpio_dwapb_platdata *plat = dev_get_platdata(dev); in dwapb_gpio_get_value() local
68 return !!(readl(plat->base + GPIO_EXT_PORT(plat->bank)) & (1 << pin)); in dwapb_gpio_get_value()
74 struct gpio_dwapb_platdata *plat = dev_get_platdata(dev); in dwapb_gpio_set_value() local
77 setbits_le32(plat->base + GPIO_SWPORT_DR(plat->bank), 1 << pin); in dwapb_gpio_set_value()
[all …]
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| D | mt7621_gpio.c | 46 static u32 reg_offs(struct mediatek_gpio_platdata *plat, int reg) in reg_offs() argument
48 return (reg * 0x10) + (plat->bank * 0x4); in reg_offs()
53 struct mediatek_gpio_platdata *plat = dev_get_platdata(dev); in mediatek_gpio_get_value() local
56 reg_offs(plat, GPIO_REG_DATA)) & BIT(offset)); in mediatek_gpio_get_value()
62 struct mediatek_gpio_platdata *plat = dev_get_platdata(dev); in mediatek_gpio_set_value() local
65 reg_offs(plat, value ? GPIO_REG_DSET : GPIO_REG_DCLR)); in mediatek_gpio_set_value()
72 struct mediatek_gpio_platdata *plat = dev_get_platdata(dev); in mediatek_gpio_direction_input() local
74 clrbits_le32(mediatek_gpio_membase + reg_offs(plat, GPIO_REG_CTRL), in mediatek_gpio_direction_input()
83 struct mediatek_gpio_platdata *plat = dev_get_platdata(dev); in mediatek_gpio_direction_output() local
85 setbits_le32(mediatek_gpio_membase + reg_offs(plat, GPIO_REG_CTRL), in mediatek_gpio_direction_output()
[all …]
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| /external/u-boot/drivers/power/pmic/ |
| D | i2c_pmic_emul.c | 31 struct sandbox_i2c_pmic_plat_data *plat = dev_get_platdata(emul); in sandbox_i2c_pmic_read_data() local
33 if (plat->rw_idx + len > plat->buf_size) { in sandbox_i2c_pmic_read_data()
35 plat->reg_count); in sandbox_i2c_pmic_read_data()
40 (unsigned int)chip & 0xff, plat->rw_reg, plat->rw_idx, len); in sandbox_i2c_pmic_read_data()
42 memcpy(buffer, plat->reg + plat->rw_idx, len); in sandbox_i2c_pmic_read_data()
51 struct sandbox_i2c_pmic_plat_data *plat = dev_get_platdata(emul); in sandbox_i2c_pmic_write_data() local
58 plat->rw_reg = *buffer; in sandbox_i2c_pmic_write_data()
59 plat->rw_idx = plat->rw_reg * plat->trans_len; in sandbox_i2c_pmic_write_data()
62 (unsigned int)chip & 0xff, plat->rw_reg, plat->rw_idx, len); in sandbox_i2c_pmic_write_data()
71 if (plat->rw_idx + len > plat->buf_size) { in sandbox_i2c_pmic_write_data()
[all …]
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| /external/u-boot/drivers/rtc/ |
| D | i2c_rtc_emul.c | 52 struct sandbox_i2c_rtc_plat_data *plat = dev_get_platdata(dev); in sandbox_i2c_rtc_set_offset() local
55 old_offset = plat->offset; in sandbox_i2c_rtc_set_offset()
56 plat->use_system_time = use_system_time; in sandbox_i2c_rtc_set_offset()
58 plat->offset = offset; in sandbox_i2c_rtc_set_offset()
65 struct sandbox_i2c_rtc_plat_data *plat = dev_get_platdata(dev); in sandbox_i2c_rtc_get_set_base_time() local
68 old_base_time = plat->base_time; in sandbox_i2c_rtc_get_set_base_time()
70 plat->base_time = base_time; in sandbox_i2c_rtc_get_set_base_time()
77 struct sandbox_i2c_rtc_plat_data *plat = dev_get_platdata(dev); in reset_time() local
81 plat->base_time = rtc_mktime(&now); in reset_time()
82 plat->offset = 0; in reset_time()
[all …]
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| /external/u-boot/drivers/serial/ |
| D | serial_lpuart.c | 137 struct lpuart_serial_platdata *plat = dev->platdata; in is_lpuart32() local
139 return plat->flags & LPUART_FLAG_REGMAP_32BIT_REG; in is_lpuart32()
145 struct lpuart_serial_platdata *plat = dev_get_platdata(dev); in _lpuart_serial_setbrg() local
146 struct lpuart_fsl *base = plat->reg; in _lpuart_serial_setbrg()
166 static int _lpuart_serial_getc(struct lpuart_serial_platdata *plat) in _lpuart_serial_getc() argument
168 struct lpuart_fsl *base = plat->reg; in _lpuart_serial_getc()
177 static void _lpuart_serial_putc(struct lpuart_serial_platdata *plat, in _lpuart_serial_putc() argument
180 struct lpuart_fsl *base = plat->reg; in _lpuart_serial_putc()
189 static int _lpuart_serial_tstc(struct lpuart_serial_platdata *plat) in _lpuart_serial_tstc() argument
191 struct lpuart_fsl *base = plat->reg; in _lpuart_serial_tstc()
[all …]
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| D | serial_rockchip.c | 17 struct ns16550_platdata plat; member
23 struct ns16550_platdata plat; member
30 struct rockchip_uart_platdata *plat = dev_get_platdata(dev); in rockchip_serial_probe() local
33 plat->plat.base = plat->dtplat.reg[0]; in rockchip_serial_probe()
34 plat->plat.reg_shift = plat->dtplat.reg_shift; in rockchip_serial_probe()
35 plat->plat.clock = plat->dtplat.clock_frequency; in rockchip_serial_probe()
36 plat->plat.fcr = UART_FCR_DEFVAL; in rockchip_serial_probe()
37 dev->platdata = &plat->plat; in rockchip_serial_probe()
|
| /external/u-boot/drivers/usb/host/ |
| D | dwc3-sti-glue.c | 45 static int sti_dwc3_glue_drd_init(struct sti_dwc3_glue_platdata *plat) in sti_dwc3_glue_drd_init() argument
49 val = readl(plat->syscfg_base + plat->syscfg_offset); in sti_dwc3_glue_drd_init()
53 switch (plat->mode) { in sti_dwc3_glue_drd_init()
73 pr_err("Unsupported mode of operation %d\n", plat->mode); in sti_dwc3_glue_drd_init()
76 writel(val, plat->syscfg_base + plat->syscfg_offset); in sti_dwc3_glue_drd_init()
81 static void sti_dwc3_glue_init(struct sti_dwc3_glue_platdata *plat) in sti_dwc3_glue_init() argument
85 reg = readl(plat->glue_base + CLKRST_CTRL); in sti_dwc3_glue_init()
90 writel(reg, plat->glue_base + CLKRST_CTRL); in sti_dwc3_glue_init()
93 reg = readl(plat->glue_base + USB2_VBUS_MNGMNT_SEL1); in sti_dwc3_glue_init()
99 writel(reg, plat->glue_base + USB2_VBUS_MNGMNT_SEL1); in sti_dwc3_glue_init()
[all …]
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| /external/u-boot/drivers/ddr/altera/ |
| D | sdram_s10.c | 69 static u32 hmc_readl(struct altera_sdram_platdata *plat, u32 reg) in hmc_readl() argument
71 return readl(plat->iomhc + reg); in hmc_readl()
74 static u32 hmc_ecc_readl(struct altera_sdram_platdata *plat, u32 reg) in hmc_ecc_readl() argument
76 return readl(plat->hmc + reg); in hmc_ecc_readl()
79 static u32 hmc_ecc_writel(struct altera_sdram_platdata *plat, in hmc_ecc_writel() argument
82 return writel(data, plat->hmc + reg); in hmc_ecc_writel()
85 static u32 ddr_sch_writel(struct altera_sdram_platdata *plat, u32 data, in ddr_sch_writel() argument
88 return writel(data, plat->ddr_sch + reg); in ddr_sch_writel()
102 static int emif_clear(struct altera_sdram_platdata *plat) in emif_clear() argument
104 hmc_ecc_writel(plat, 0, RSTHANDSHAKECTRL); in emif_clear()
[all …]
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| /external/u-boot/drivers/spi/ |
| D | cadence_qspi.c | 24 struct cadence_spi_platdata *plat = bus->platdata; in cadence_spi_write_speed() local
28 plat->ref_clk_hz, hz); in cadence_spi_write_speed()
31 cadence_qspi_apb_delay(priv->regbase, plat->ref_clk_hz, hz, in cadence_spi_write_speed()
32 plat->tshsl_ns, plat->tsd2d_ns, in cadence_spi_write_speed()
33 plat->tchsh_ns, plat->tslch_ns); in cadence_spi_write_speed()
120 struct cadence_spi_platdata *plat = bus->platdata; in cadence_spi_set_speed() local
124 if (hz > plat->max_hz) in cadence_spi_set_speed()
125 hz = plat->max_hz; in cadence_spi_set_speed()
155 struct cadence_spi_platdata *plat = bus->platdata; in cadence_spi_probe() local
159 priv->regbase = plat->regbase; in cadence_spi_probe()
[all …]
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| D | soft_spi.c | 41 struct soft_spi_platdata *plat = dev_get_platdata(bus); in soft_spi_scl() local
43 dm_gpio_set_value(&plat->sclk, bit); in soft_spi_scl()
51 struct soft_spi_platdata *plat = dev_get_platdata(bus); in soft_spi_sda() local
53 dm_gpio_set_value(&plat->mosi, bit); in soft_spi_sda()
61 struct soft_spi_platdata *plat = dev_get_platdata(bus); in soft_spi_cs_activate() local
63 dm_gpio_set_value(&plat->cs, 0); in soft_spi_cs_activate()
64 dm_gpio_set_value(&plat->sclk, 0); in soft_spi_cs_activate()
65 dm_gpio_set_value(&plat->cs, 1); in soft_spi_cs_activate()
73 struct soft_spi_platdata *plat = dev_get_platdata(bus); in soft_spi_cs_deactivate() local
75 dm_gpio_set_value(&plat->cs, 0); in soft_spi_cs_deactivate()
[all …]
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| D | cadence_qspi_apb.c | 378 void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat) in cadence_qspi_apb_controller_init() argument
382 cadence_qspi_apb_controller_disable(plat->regbase); in cadence_qspi_apb_controller_init()
385 reg = readl(plat->regbase + CQSPI_REG_SIZE); in cadence_qspi_apb_controller_init()
389 reg |= (plat->page_size << CQSPI_REG_SIZE_PAGE_LSB); in cadence_qspi_apb_controller_init()
390 reg |= (plat->block_size << CQSPI_REG_SIZE_BLOCK_LSB); in cadence_qspi_apb_controller_init()
391 writel(reg, plat->regbase + CQSPI_REG_SIZE); in cadence_qspi_apb_controller_init()
394 writel(0, plat->regbase + CQSPI_REG_REMAP); in cadence_qspi_apb_controller_init()
397 writel(plat->fifo_depth / 2, plat->regbase + CQSPI_REG_SRAMPARTITION); in cadence_qspi_apb_controller_init()
400 writel(0, plat->regbase + CQSPI_REG_IRQMASK); in cadence_qspi_apb_controller_init()
402 cadence_qspi_apb_controller_enable(plat->regbase); in cadence_qspi_apb_controller_init()
[all …]
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| /external/u-boot/drivers/mmc/ |
| D | am654_sdhci.c | 98 struct am654_sdhci_plat *plat = dev_get_platdata(dev); in am654_sdhci_set_ios_post() local
110 if (plat->dll_on) { in am654_sdhci_set_ios_post()
111 regmap_update_bits(plat->base, PHY_CTRL1, ENDLL_MASK, 0); in am654_sdhci_set_ios_post()
113 plat->dll_on = false; in am654_sdhci_set_ios_post()
123 (plat->otap_del_sel << OTAPDLYSEL_SHIFT); in am654_sdhci_set_ios_post()
124 regmap_update_bits(plat->base, PHY_CTRL4, mask, val); in am654_sdhci_set_ios_post()
142 regmap_update_bits(plat->base, PHY_CTRL5, mask, val); in am654_sdhci_set_ios_post()
145 regmap_update_bits(plat->base, PHY_CTRL1, ENDLL_MASK, in am654_sdhci_set_ios_post()
151 ret = regmap_read_poll_timeout(plat->base, PHY_STAT1, val, in am654_sdhci_set_ios_post()
156 plat->dll_on = true; in am654_sdhci_set_ios_post()
[all …]
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| /external/u-boot/drivers/cache/ |
| D | cache-v5l2.c | 74 struct v5l2_plat *plat = dev_get_platdata(dev); in v5l2_enable() local
75 volatile struct l2cache *regs = plat->regs; in v5l2_enable()
85 struct v5l2_plat *plat = dev_get_platdata(dev); in v5l2_disable() local
86 volatile struct l2cache *regs = plat->regs; in v5l2_disable()
107 struct v5l2_plat *plat = dev_get_platdata(dev); in v5l2_ofdata_to_platdata() local
111 plat->regs = regs; in v5l2_ofdata_to_platdata()
113 plat->iprefetch = -EINVAL; in v5l2_ofdata_to_platdata()
114 plat->dprefetch = -EINVAL; in v5l2_ofdata_to_platdata()
115 plat->tram_ctl[0] = -EINVAL; in v5l2_ofdata_to_platdata()
116 plat->dram_ctl[0] = -EINVAL; in v5l2_ofdata_to_platdata()
[all …]
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| /external/arm-trusted-firmware/plat/xilinx/zynqmp/ |
| D | platform.mk | 55 PLAT_INCLUDES := -Iinclude/plat/arm/common/ \
56 -Iinclude/plat/arm/common/aarch64/ \
70 plat/arm/common/arm_cci.c \
71 plat/arm/common/arm_common.c \
72 plat/arm/common/arm_gicv2.c \
73 plat/common/plat_gicv2.c \
74 plat/xilinx/common/ipi.c \
75 plat/xilinx/zynqmp/zynqmp_ipi.c \
76 plat/xilinx/zynqmp/aarch64/zynqmp_helpers.S \
77 plat/xilinx/zynqmp/aarch64/zynqmp_common.c
[all …]
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| /external/u-boot/drivers/video/ |
| D | sandbox_sdl.c | 24 struct sandbox_sdl_plat *plat = dev_get_platdata(dev); in sandbox_sdl_probe() local
28 ret = sandbox_sdl_init_display(plat->xres, plat->yres, plat->bpix); in sandbox_sdl_probe()
33 uc_priv->xsize = plat->xres; in sandbox_sdl_probe()
34 uc_priv->ysize = plat->yres; in sandbox_sdl_probe()
35 uc_priv->bpix = plat->bpix; in sandbox_sdl_probe()
36 uc_priv->rot = plat->rot; in sandbox_sdl_probe()
37 uc_priv->vidconsole_drv_name = plat->vidconsole_drv_name; in sandbox_sdl_probe()
38 uc_priv->font_size = plat->font_size; in sandbox_sdl_probe()
46 struct sandbox_sdl_plat *plat = dev_get_platdata(dev); in sandbox_sdl_bind() local
51 plat->xres = fdtdec_get_int(blob, node, "xres", LCD_MAX_WIDTH); in sandbox_sdl_bind()
[all …]
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| D | broadwell_igd.c | 355 struct broadwell_igd_plat *plat = dev_get_platdata(dev); in igd_setup_panel() local
360 reg32 = (plat->dp_hotplug[0] & 0x7) << 2; in igd_setup_panel()
361 reg32 |= (plat->dp_hotplug[1] & 0x7) << 10; in igd_setup_panel()
362 reg32 |= (plat->dp_hotplug[2] & 0x7) << 18; in igd_setup_panel()
366 reg32 = (plat->port_select & 0x3) << 30; in igd_setup_panel()
367 reg32 |= (plat->power_up_delay & 0x1fff) << 16; in igd_setup_panel()
368 reg32 |= (plat->power_backlight_on_delay & 0x1fff); in igd_setup_panel()
372 reg32 = (plat->power_down_delay & 0x1fff) << 16; in igd_setup_panel()
373 reg32 |= (plat->power_backlight_off_delay & 0x1fff); in igd_setup_panel()
377 if (plat->power_cycle_delay) { in igd_setup_panel()
[all …]
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| /external/arm-trusted-firmware/plat/intel/soc/agilex/ |
| D | platform.mk | 22 plat/common/plat_gicv2.c \
23 plat/intel/soc/common/aarch64/platform_common.c \
24 plat/intel/soc/common/aarch64/plat_helpers.S
37 plat/intel/soc/agilex/bl2_plat_setup.c \
38 plat/intel/soc/agilex/soc/agilex_clock_manager.c \
39 plat/intel/soc/agilex/soc/agilex_memory_controller.c \
40 plat/intel/soc/agilex/soc/agilex_pinmux.c \
41 plat/intel/soc/common/bl2_plat_mem_params_desc.c \
42 plat/intel/soc/common/socfpga_delay_timer.c \
43 plat/intel/soc/common/socfpga_image_load.c \
[all …]
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| /external/arm-trusted-firmware/plat/intel/soc/stratix10/ |
| D | platform.mk | 22 plat/common/plat_gicv2.c \
23 plat/intel/soc/common/aarch64/platform_common.c \
24 plat/intel/soc/common/aarch64/plat_helpers.S
37 plat/intel/soc/stratix10/bl2_plat_setup.c \
38 plat/intel/soc/stratix10/soc/s10_clock_manager.c \
39 plat/intel/soc/stratix10/soc/s10_memory_controller.c \
40 plat/intel/soc/stratix10/soc/s10_pinmux.c \
41 plat/intel/soc/common/bl2_plat_mem_params_desc.c \
42 plat/intel/soc/common/socfpga_delay_timer.c \
43 plat/intel/soc/common/socfpga_image_load.c \
[all …]
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| /external/arm-trusted-firmware/plat/arm/board/a5ds/ |
| D | platform.mk | 10 DYN_CFG_SOURCES += plat/arm/common/arm_dyn_cfg.c \
11 plat/arm/common/arm_dyn_cfg_helpers.c \
17 plat/common/plat_gicv2.c \
18 plat/arm/common/arm_gicv2.c
20 A5DS_SECURITY_SOURCES := plat/arm/board/a5ds/a5ds_security.c
25 plat/arm/board/a5ds/a5ds_common.c \
26 plat/arm/common/${ARCH}/arm_helpers.S \
27 plat/arm/common/arm_common.c \
28 plat/arm/common/arm_console.c \
29 plat/arm/board/common/${ARCH}/board_arm_helpers.S
[all …]
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| /external/u-boot/arch/x86/cpu/broadwell/ |
| D | sata.c | 42 struct sata_platdata *plat = dev_get_platdata(dev); in broadwell_sata_init() local
57 reg16 |= 0x8000 | plat->port_map; in broadwell_sata_init()
75 reg32 |= (plat->port_map ^ 0xf) << 24; in broadwell_sata_init()
76 reg32 |= (plat->devslp_mux & 1) << 15; in broadwell_sata_init()
90 writel(plat->port_map, abar + 0x0c); in broadwell_sata_init()
95 if (plat->devslp_disable) { in broadwell_sata_init()
102 if (!(plat->port_map & (1 << port))) in broadwell_sata_init()
112 if ((plat->port_map & ((1 << 3)|(1 << 2))) == 0) in broadwell_sata_init()
115 if ((plat->port_map & ((1 << 1)|(1 << 0))) == 0) in broadwell_sata_init()
120 if (plat->port0_gen3_tx) in broadwell_sata_init()
[all …]
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| /external/arm-trusted-firmware/plat/xilinx/versal/ |
| D | platform.mk | 40 PLAT_INCLUDES := -Iinclude/plat/arm/common/ \
56 plat/common/aarch64/crash_console_helpers.S \
57 plat/arm/common/arm_cci.c \
58 plat/arm/common/arm_common.c \
59 plat/common/plat_gicv3.c \
60 plat/xilinx/versal/aarch64/versal_helpers.S \
61 plat/xilinx/versal/aarch64/versal_common.c
66 plat/common/plat_psci_common.c \
67 plat/xilinx/common/ipi.c \
68 plat/xilinx/common/plat_startup.c \
[all …]
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| /external/arm-trusted-firmware/plat/hisilicon/hikey/ |
| D | platform.mk | 52 plat/hisilicon/hikey/aarch64/hikey_common.c
65 plat/hisilicon/hikey/aarch64/hikey_helpers.S \
66 plat/hisilicon/hikey/hikey_bl1_setup.c \
67 plat/hisilicon/hikey/hikey_bl_common.c \
68 plat/hisilicon/hikey/hikey_io_storage.c
83 plat/hisilicon/hikey/aarch64/hikey_helpers.S \
84 plat/hisilicon/hikey/hikey_bl2_mem_params_desc.c \
85 plat/hisilicon/hikey/hikey_bl2_setup.c \
86 plat/hisilicon/hikey/hikey_bl_common.c \
87 plat/hisilicon/hikey/hikey_security.c \
[all …]
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| /external/arm-trusted-firmware/plat/layerscape/common/ |
| D | ls_common.mk | 18 PLAT_BL_COMMON_SOURCES += plat/layerscape/common/${ARCH}/ls_helpers.S \
19 plat/layerscape/common/ls_common.c
29 plat/layerscape/common/ls_timer.c \
30 plat/layerscape/common/ls_bl1_setup.c \
31 plat/layerscape/common/ls_io_storage.c
36 plat/layerscape/common/ls_timer.c \
37 plat/layerscape/common/ls_bl2_setup.c \
38 plat/layerscape/common/ls_io_storage.c
39 BL2_SOURCES += plat/layerscape/common/${ARCH}/ls_bl2_mem_params_desc.c
40 BL2_SOURCES += plat/layerscape/common/ls_image_load.c \
[all …]
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