| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 48 unsigned Opc = MI.getOpcode(); in isLoadFromStackSlot() local
50 if ((Opc == Mips::LW) || (Opc == Mips::LD) || in isLoadFromStackSlot()
51 (Opc == Mips::LWC1) || (Opc == Mips::LDC1) || (Opc == Mips::LDC164)) { in isLoadFromStackSlot()
70 unsigned Opc = MI.getOpcode(); in isStoreToStackSlot() local
72 if ((Opc == Mips::SW) || (Opc == Mips::SD) || in isStoreToStackSlot()
73 (Opc == Mips::SWC1) || (Opc == Mips::SDC1) || (Opc == Mips::SDC164)) { in isStoreToStackSlot()
88 unsigned Opc = 0, ZeroReg = 0; in copyPhysReg() local
94 Opc = Mips::MOVE16_MM; in copyPhysReg()
96 Opc = Mips::OR, ZeroReg = Mips::ZERO; in copyPhysReg()
98 Opc = Mips::CFC1; in copyPhysReg()
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| D | Mips16InstrInfo.cpp | 74 unsigned Opc = 0; in copyPhysReg() local
78 Opc = Mips::MoveR3216; in copyPhysReg()
81 Opc = Mips::Move32R16; in copyPhysReg()
84 Opc = Mips::Mfhi16, SrcReg = 0; in copyPhysReg()
87 Opc = Mips::Mflo16, SrcReg = 0; in copyPhysReg()
89 assert(Opc && "Cannot copy registers"); in copyPhysReg()
91 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc)); in copyPhysReg()
120 unsigned Opc = 0; in storeRegToStack() local
122 Opc = Mips::SwRxSpImmX16; in storeRegToStack()
123 assert(Opc && "Register class not handled!"); in storeRegToStack()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 43 unsigned Opc = MI.getOpcode(); in isLoadFromStackSlot() local
45 if ((Opc == Mips::LW) || (Opc == Mips::LD) || in isLoadFromStackSlot()
46 (Opc == Mips::LWC1) || (Opc == Mips::LDC1) || (Opc == Mips::LDC164)) { in isLoadFromStackSlot()
65 unsigned Opc = MI.getOpcode(); in isStoreToStackSlot() local
67 if ((Opc == Mips::SW) || (Opc == Mips::SD) || in isStoreToStackSlot()
68 (Opc == Mips::SWC1) || (Opc == Mips::SDC1) || (Opc == Mips::SDC164)) { in isStoreToStackSlot()
83 unsigned Opc = 0, ZeroReg = 0; in copyPhysReg() local
89 Opc = Mips::MOVE16_MM; in copyPhysReg()
91 Opc = Mips::OR, ZeroReg = Mips::ZERO; in copyPhysReg()
93 Opc = Mips::CFC1; in copyPhysReg()
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| D | Mips16InstrInfo.cpp | 63 unsigned Opc = 0; in copyPhysReg() local
67 Opc = Mips::MoveR3216; in copyPhysReg()
70 Opc = Mips::Move32R16; in copyPhysReg()
73 Opc = Mips::Mfhi16, SrcReg = 0; in copyPhysReg()
77 Opc = Mips::Mflo16, SrcReg = 0; in copyPhysReg()
80 assert(Opc && "Cannot copy registers"); in copyPhysReg()
82 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc)); in copyPhysReg()
100 unsigned Opc = 0; in storeRegToStack() local
102 Opc = Mips::SwRxSpImmX16; in storeRegToStack()
103 assert(Opc && "Register class not handled!"); in storeRegToStack()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/NVPTX/ |
| D | NVPTXISelDAGToDAG.cpp | 747 unsigned Opc; in SelectAddrSpaceCast() local
751 Opc = TM.is64Bit() ? NVPTX::cvta_global_yes_64 : NVPTX::cvta_global_yes; in SelectAddrSpaceCast()
754 Opc = TM.is64Bit() ? (useShortPointers() ? NVPTX::cvta_shared_yes_6432 in SelectAddrSpaceCast()
759 Opc = TM.is64Bit() ? (useShortPointers() ? NVPTX::cvta_const_yes_6432 in SelectAddrSpaceCast()
764 Opc = TM.is64Bit() ? (useShortPointers() ? NVPTX::cvta_local_yes_6432 in SelectAddrSpaceCast()
769 ReplaceNode(N, CurDAG->getMachineNode(Opc, SDLoc(N), N->getValueType(0), in SelectAddrSpaceCast()
776 unsigned Opc; in SelectAddrSpaceCast() local
780 Opc = TM.is64Bit() ? NVPTX::cvta_to_global_yes_64 in SelectAddrSpaceCast()
784 Opc = TM.is64Bit() ? (useShortPointers() ? NVPTX::cvta_to_shared_yes_3264 in SelectAddrSpaceCast()
789 Opc = TM.is64Bit() ? (useShortPointers() ? NVPTX::cvta_to_const_yes_3264 in SelectAddrSpaceCast()
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| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXISelDAGToDAG.cpp | 622 unsigned Opc; in SelectAddrSpaceCast() local
626 Opc = TM.is64Bit() ? NVPTX::cvta_global_yes_64 : NVPTX::cvta_global_yes; in SelectAddrSpaceCast()
629 Opc = TM.is64Bit() ? NVPTX::cvta_shared_yes_64 : NVPTX::cvta_shared_yes; in SelectAddrSpaceCast()
632 Opc = TM.is64Bit() ? NVPTX::cvta_const_yes_64 : NVPTX::cvta_const_yes; in SelectAddrSpaceCast()
635 Opc = TM.is64Bit() ? NVPTX::cvta_local_yes_64 : NVPTX::cvta_local_yes; in SelectAddrSpaceCast()
638 ReplaceNode(N, CurDAG->getMachineNode(Opc, SDLoc(N), N->getValueType(0), in SelectAddrSpaceCast()
645 unsigned Opc; in SelectAddrSpaceCast() local
649 Opc = TM.is64Bit() ? NVPTX::cvta_to_global_yes_64 in SelectAddrSpaceCast()
653 Opc = TM.is64Bit() ? NVPTX::cvta_to_shared_yes_64 in SelectAddrSpaceCast()
657 Opc = in SelectAddrSpaceCast()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.h | 105 virtual unsigned getUnindexedOpcode(unsigned Opc) const =0;
420 bool isUncondBranchOpcode(int Opc) { in isUncondBranchOpcode() argument
421 return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B; in isUncondBranchOpcode()
425 bool isCondBranchOpcode(int Opc) { in isCondBranchOpcode() argument
426 return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc; in isCondBranchOpcode()
430 bool isJumpTableBranchOpcode(int Opc) { in isJumpTableBranchOpcode() argument
431 return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm || Opc == ARM::BR_JTadd || in isJumpTableBranchOpcode()
432 Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT; in isJumpTableBranchOpcode()
436 bool isIndirectBranchOpcode(int Opc) { in isIndirectBranchOpcode() argument
437 return Opc == ARM::BX || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND; in isIndirectBranchOpcode()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyFastISel.cpp | 380 unsigned Opc = Subtarget->hasAddr64() ? in materializeLoadStoreOperands() local
383 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), Reg) in materializeLoadStoreOperands()
596 unsigned Opc = Subtarget->hasAddr64() ? in fastMaterializeAlloca() local
599 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg) in fastMaterializeAlloca()
612 unsigned Opc = Subtarget->hasAddr64() ? in fastMaterializeConstant() local
615 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg) in fastMaterializeConstant()
648 unsigned Opc; in fastLowerArguments() local
655 Opc = WebAssembly::ARGUMENT_I32; in fastLowerArguments()
659 Opc = WebAssembly::ARGUMENT_I64; in fastLowerArguments()
663 Opc = WebAssembly::ARGUMENT_F32; in fastLowerArguments()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.h | 110 virtual unsigned getUnindexedOpcode(unsigned Opc) const = 0;
467 bool isUncondBranchOpcode(int Opc) { in isUncondBranchOpcode() argument
468 return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B; in isUncondBranchOpcode()
472 bool isCondBranchOpcode(int Opc) { in isCondBranchOpcode() argument
473 return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc; in isCondBranchOpcode()
476 static inline bool isJumpTableBranchOpcode(int Opc) { in isJumpTableBranchOpcode() argument
477 return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm_i12 || in isJumpTableBranchOpcode()
478 Opc == ARM::BR_JTm_rs || Opc == ARM::BR_JTadd || Opc == ARM::tBR_JTr || in isJumpTableBranchOpcode()
479 Opc == ARM::t2BR_JT; in isJumpTableBranchOpcode()
483 bool isIndirectBranchOpcode(int Opc) { in isIndirectBranchOpcode() argument
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| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyFastISel.cpp | 331 unsigned Opc = Subtarget->hasAddr64() ? in materializeLoadStoreOperands() local
334 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), Reg) in materializeLoadStoreOperands()
531 unsigned Opc = Subtarget->hasAddr64() ? in fastMaterializeAlloca() local
534 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg) in fastMaterializeAlloca()
547 unsigned Opc = Subtarget->hasAddr64() ? in fastMaterializeConstant() local
550 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg) in fastMaterializeConstant()
581 unsigned Opc; in fastLowerArguments() local
588 Opc = WebAssembly::ARGUMENT_I32; in fastLowerArguments()
592 Opc = WebAssembly::ARGUMENT_I64; in fastLowerArguments()
596 Opc = WebAssembly::ARGUMENT_F32; in fastLowerArguments()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.cpp | 310 unsigned Opc = 0; in canFoldIntoCSel() local
326 Opc = Is64Bit ? AArch64::CSINCXr : AArch64::CSINCWr; in canFoldIntoCSel()
336 Opc = Is64Bit ? AArch64::CSINVXr : AArch64::CSINVWr; in canFoldIntoCSel()
353 Opc = Is64Bit ? AArch64::CSNEGXr : AArch64::CSNEGWr; in canFoldIntoCSel()
359 assert(Opc && SrcOpNum && "Missing parameters"); in canFoldIntoCSel()
363 return Opc; in canFoldIntoCSel()
491 unsigned Opc = 0; in insertSelect() local
496 Opc = AArch64::CSELXr; in insertSelect()
500 Opc = AArch64::CSELWr; in insertSelect()
504 Opc = AArch64::FCSELDrrr; in insertSelect()
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| D | AArch64ConditionalCompares.cpp | 577 unsigned Opc = 0; in convert() local
581 Opc = AArch64::SUBSWri; in convert()
585 Opc = AArch64::SUBSXri; in convert()
590 const MCInstrDesc &MCID = TII->get(Opc); in convert()
609 unsigned Opc = 0; in convert() local
615 case AArch64::SUBSWri: Opc = AArch64::CCMPWi; break; in convert()
616 case AArch64::SUBSWrr: Opc = AArch64::CCMPWr; break; in convert()
617 case AArch64::SUBSXri: Opc = AArch64::CCMPXi; break; in convert()
618 case AArch64::SUBSXrr: Opc = AArch64::CCMPXr; break; in convert()
619 case AArch64::ADDSWri: Opc = AArch64::CCMNWi; break; in convert()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCFastISel.cpp | 114 unsigned fastEmit_i(MVT Ty, MVT RetTy, unsigned Opc, uint64_t Imm) override;
468 unsigned Opc; in PPCEmitLoad() local
493 Opc = Is32BitInt ? PPC::LBZ : PPC::LBZ8; in PPCEmitLoad()
496 Opc = (IsZExt ? (Is32BitInt ? PPC::LHZ : PPC::LHZ8) in PPCEmitLoad()
500 Opc = (IsZExt ? (Is32BitInt ? PPC::LWZ : PPC::LWZ8) in PPCEmitLoad()
502 if ((Opc == PPC::LWA || Opc == PPC::LWA_32) && ((Addr.Offset & 3) != 0)) in PPCEmitLoad()
506 Opc = PPC::LD; in PPCEmitLoad()
512 Opc = PPCSubTarget->hasSPE() ? PPC::SPELWZ : PPC::LFS; in PPCEmitLoad()
515 Opc = FP64LoadOpc; in PPCEmitLoad()
528 bool Is32VSXLoad = IsVSSRC && Opc == PPC::LFS; in PPCEmitLoad()
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| D | PPCReduceCRLogicals.cpp | 366 unsigned Opc = MI.getOpcode(); in isCRLogical() local
367 return Opc == PPC::CRAND || Opc == PPC::CRNAND || Opc == PPC::CROR || in isCRLogical()
368 Opc == PPC::CRXOR || Opc == PPC::CRNOR || Opc == PPC::CREQV || in isCRLogical()
369 Opc == PPC::CRANDC || Opc == PPC::CRORC || Opc == PPC::CRSET || in isCRLogical()
370 Opc == PPC::CRUNSET || Opc == PPC::CR6SET || Opc == PPC::CR6UNSET; in isCRLogical()
475 unsigned Opc = UseMI.getOpcode(); in createCRLogicalOpInfo() local
476 if (Opc == PPC::ISEL || Opc == PPC::ISEL8) in createCRLogicalOpInfo()
478 if (Opc == PPC::BC || Opc == PPC::BCn || Opc == PPC::BCLR || in createCRLogicalOpInfo()
479 Opc == PPC::BCLRn) in createCRLogicalOpInfo()
654 unsigned Opc = CRI.MI->getOpcode(); in splitBlockOnBinaryCROp() local
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCFastISel.cpp | 114 unsigned fastEmit_i(MVT Ty, MVT RetTy, unsigned Opc, uint64_t Imm) override;
465 unsigned Opc; in PPCEmitLoad() local
489 Opc = Is32BitInt ? PPC::LBZ : PPC::LBZ8; in PPCEmitLoad()
492 Opc = (IsZExt ? in PPCEmitLoad()
497 Opc = (IsZExt ? in PPCEmitLoad()
500 if ((Opc == PPC::LWA || Opc == PPC::LWA_32) && ((Addr.Offset & 3) != 0)) in PPCEmitLoad()
504 Opc = PPC::LD; in PPCEmitLoad()
510 Opc = PPC::LFS; in PPCEmitLoad()
513 Opc = FP64LoadOpc; in PPCEmitLoad()
526 bool Is32VSXLoad = IsVSSRC && Opc == PPC::LFS; in PPCEmitLoad()
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| /external/llvm/lib/Target/X86/ |
| D | X86FastISel.cpp | 97 bool X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT,
129 bool X86SelectFPExtOrFPTrunc(const Instruction *I, unsigned Opc,
357 unsigned Opc = 0; in X86FastEmitLoad() local
363 Opc = X86::MOV8rm; in X86FastEmitLoad()
367 Opc = X86::MOV16rm; in X86FastEmitLoad()
371 Opc = X86::MOV32rm; in X86FastEmitLoad()
376 Opc = X86::MOV64rm; in X86FastEmitLoad()
381 Opc = HasAVX ? X86::VMOVSSrm : X86::MOVSSrm; in X86FastEmitLoad()
384 Opc = X86::LD_Fp32m; in X86FastEmitLoad()
390 Opc = HasAVX ? X86::VMOVSDrm : X86::MOVSDrm; in X86FastEmitLoad()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | XRayInstrumentation.cpp | 96 unsigned Opc = 0; in replaceRetWithPatchableRet() local
101 Opc = TargetOpcode::PATCHABLE_RET; in replaceRetWithPatchableRet()
106 Opc = TargetOpcode::PATCHABLE_TAIL_CALL; in replaceRetWithPatchableRet()
108 if (Opc != 0) { in replaceRetWithPatchableRet()
109 auto MIB = BuildMI(MBB, T, T.getDebugLoc(), TII->get(Opc)) in replaceRetWithPatchableRet()
127 unsigned Opc = 0; in prependRetWithPatchableExit() local
130 Opc = TargetOpcode::PATCHABLE_FUNCTION_EXIT; in prependRetWithPatchableExit()
133 Opc = TargetOpcode::PATCHABLE_TAIL_CALL; in prependRetWithPatchableExit()
135 if (Opc != 0) { in prependRetWithPatchableExit()
138 BuildMI(MBB, T, T.getDebugLoc(), TII->get(Opc)); in prependRetWithPatchableExit()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86FastISel.cpp | 97 bool X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT,
131 bool X86SelectFPExtOrFPTrunc(const Instruction *I, unsigned Opc,
331 unsigned Opc = 0; in X86FastEmitLoad() local
337 Opc = X86::MOV8rm; in X86FastEmitLoad()
341 Opc = X86::MOV16rm; in X86FastEmitLoad()
345 Opc = X86::MOV32rm; in X86FastEmitLoad()
350 Opc = X86::MOV64rm; in X86FastEmitLoad()
355 Opc = HasAVX512 ? X86::VMOVSSZrm : HasAVX ? X86::VMOVSSrm : X86::MOVSSrm; in X86FastEmitLoad()
358 Opc = X86::LD_Fp32m; in X86FastEmitLoad()
364 Opc = HasAVX512 ? X86::VMOVSDZrm : HasAVX ? X86::VMOVSDrm : X86::MOVSDrm; in X86FastEmitLoad()
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| D | X86InstrInfo.cpp | 731 unsigned Opc, bool AllowSP, unsigned &NewSrc, in classifyLEAReg() argument
738 RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass; in classifyLEAReg()
740 RC = Opc != X86::LEA32r ? in classifyLEAReg()
747 if (Opc != X86::LEA64_32r) { in classifyLEAReg()
803 unsigned Opc, leaInReg; in convertToThreeAddressWithLEA() local
805 Opc = X86::LEA64_32r; in convertToThreeAddressWithLEA()
808 Opc = X86::LEA32r; in convertToThreeAddressWithLEA()
826 BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(Opc), leaOutReg); in convertToThreeAddressWithLEA()
954 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r; in convertToThreeAddress() local
960 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false, in convertToThreeAddress()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.cpp | 147 static unsigned getBranchDisplacementBits(unsigned Opc) { in getBranchDisplacementBits() argument
148 switch (Opc) { in getBranchDisplacementBits()
428 unsigned Opc = 0; in canFoldIntoCSel() local
445 Opc = Is64Bit ? AArch64::CSINCXr : AArch64::CSINCWr; in canFoldIntoCSel()
455 Opc = Is64Bit ? AArch64::CSINVXr : AArch64::CSINVWr; in canFoldIntoCSel()
473 Opc = Is64Bit ? AArch64::CSNEGXr : AArch64::CSNEGWr; in canFoldIntoCSel()
479 assert(Opc && SrcOpNum && "Missing parameters"); in canFoldIntoCSel()
483 return Opc; in canFoldIntoCSel()
612 unsigned Opc = 0; in insertSelect() local
617 Opc = AArch64::CSELXr; in insertSelect()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | SIFoldOperands.cpp | 128 unsigned Opc = UseMI.getOpcode(); in isInlineConstantIfFolded() local
129 switch (Opc) { in isInlineConstantIfFolded()
135 int Src2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2); in isInlineConstantIfFolded()
137 bool IsFMA = Opc == AMDGPU::V_FMAC_F32_e64; in isInlineConstantIfFolded()
138 bool IsF32 = Opc == AMDGPU::V_MAC_F32_e64; in isInlineConstantIfFolded()
140 unsigned Opc = IsFMA ? in isInlineConstantIfFolded() local
142 const MCInstrDesc &MadDesc = TII->get(Opc); in isInlineConstantIfFolded()
231 unsigned Opc = MI->getOpcode(); in tryAddToFoldList() local
232 if ((Opc == AMDGPU::V_MAC_F32_e64 || Opc == AMDGPU::V_MAC_F16_e64 || in tryAddToFoldList()
233 Opc == AMDGPU::V_FMAC_F32_e64) && in tryAddToFoldList()
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| /external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/ |
| D | WebAssemblyDisassemblerEmitter.cpp | 36 auto Opc = static_cast<unsigned>( in emitWebAssemblyDisassemblerTables() local
39 if (Opc == 0xFFFFFFFF) in emitWebAssemblyDisassemblerTables()
41 assert(Opc <= 0xFFFF); in emitWebAssemblyDisassemblerTables()
42 auto Prefix = Opc >> 8; in emitWebAssemblyDisassemblerTables()
43 Opc = Opc & 0xFF; in emitWebAssemblyDisassemblerTables()
44 auto &CGIP = OpcodeTable[Prefix][Opc]; in emitWebAssemblyDisassemblerTables()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonCFGOptimizer.cpp | 61 static bool IsConditionalBranch(int Opc) { in IsConditionalBranch() argument
62 return (Opc == Hexagon::J2_jumpt) || (Opc == Hexagon::J2_jumpf) in IsConditionalBranch()
63 || (Opc == Hexagon::J2_jumptnewpt) || (Opc == Hexagon::J2_jumpfnewpt); in IsConditionalBranch()
67 static bool IsUnconditionalJump(int Opc) { in IsUnconditionalJump() argument
68 return (Opc == Hexagon::J2_jump); in IsUnconditionalJump()
115 int Opc = MI.getOpcode(); in runOnMachineFunction() local
116 if (IsConditionalBranch(Opc)) { in runOnMachineFunction()
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| D | HexagonSplitConst32AndConst64.cpp | 90 int Opc = MI.getOpcode(); in runOnMachineFunction() local
91 if (Opc == Hexagon::CONST32_Int_Real && in runOnMachineFunction()
106 else if (Opc == Hexagon::CONST32_Int_Real || in runOnMachineFunction()
107 Opc == Hexagon::CONST32_Float_Real) { in runOnMachineFunction()
113 if (Opc == Hexagon::CONST32_Float_Real) { in runOnMachineFunction()
126 else if (Opc == Hexagon::CONST64_Int_Real || in runOnMachineFunction()
127 Opc == Hexagon::CONST64_Float_Real) { in runOnMachineFunction()
133 if (Opc == Hexagon::CONST64_Float_Real) { in runOnMachineFunction()
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | ConstantFoldingMIRBuilder.h | 92 MachineInstrBuilder buildInstr(unsigned Opc, DstTy &&Ty, UseArg1Ty &&Arg1, in buildInstr() argument
95 return buildInstr(Opc, Dst, getRegFromArg(std::forward<UseArg1Ty>(Arg1)), in buildInstr()
101 MachineInstrBuilder buildInstr(unsigned Opc, unsigned Dst, unsigned Src0, in buildInstr() argument
103 switch (Opc) { in buildInstr()
119 return buildBinaryOp(Opc, Dst, Src0, Src1); in buildInstr()
122 return buildInstr(Opc).addDef(Dst).addUse(Src0).addUse(Src1); in buildInstr()
127 MachineInstrBuilder buildInstr(unsigned Opc, DstTy &&Ty, in buildInstr() argument
129 auto MIB = buildInstr(Opc).addDef(getDestFromArg(Ty)); in buildInstr()
|