Home
last modified time | relevance | path

Searched refs:mmio_setbits_32 (Results 1 – 25 of 61) sorted by relevance

123

/external/arm-trusted-firmware/plat/marvell/a3700/common/
Dplat_pm.c271 mmio_setbits_32(MVEBU_CPU_1_RESET_REG, BIT(MVEBU_CPU_1_RESET_BIT)); in a3700_pwr_domain_on()
304 mmio_setbits_32(MVEBU_PM_NB_CPU_PWR_CTRL_REG, MVEBU_PM_L2_FLUSH_EN); in a3700_set_gen_pwr_off_option()
330 mmio_setbits_32(MVEBU_PM_NB_PWR_DEBUG_REG, MVEBU_PM_IGNORE_CM3_SLEEP); in a3700_set_gen_pwr_off_option()
331 mmio_setbits_32(MVEBU_PM_NB_PWR_DEBUG_REG, MVEBU_PM_IGNORE_CM3_DEEP); in a3700_set_gen_pwr_off_option()
337 mmio_setbits_32(MVEBU_PM_NB_PWR_OPTION_REG, MVEBU_PM_NB_SRAM_LKG_PD_EN); in a3700_set_gen_pwr_off_option()
346 mmio_setbits_32(MVEBU_PM_NB_PWR_CTRL_REG, MVEBU_PM_INTERFACE_IDLE); in a3700_set_gen_pwr_off_option()
349 mmio_setbits_32(MVEBU_PM_CPU_0_PWR_CTRL_REG, MVEBU_PM_CORE_PD); in a3700_set_gen_pwr_off_option()
350 mmio_setbits_32(MVEBU_PM_CPU_1_PWR_CTRL_REG, MVEBU_PM_CORE_PD); in a3700_set_gen_pwr_off_option()
355 mmio_setbits_32(MVEBU_PM_CPU_0_PWR_CTRL_REG, MVEBU_PM_CORE_SOC_PD); in a3700_set_gen_pwr_off_option()
356 mmio_setbits_32(MVEBU_PM_CPU_1_PWR_CTRL_REG, MVEBU_PM_CORE_SOC_PD); in a3700_set_gen_pwr_off_option()
[all …]
/external/arm-trusted-firmware/plat/imx/imx8m/
Dgpc_common.c42 mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id)); in imx_set_cpu_pwr_off()
44 mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1); in imx_set_cpu_pwr_off()
54 mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1); in imx_set_cpu_pwr_on()
56 mmio_setbits_32(IMX_GPC_BASE + CPU_PGC_UP_TRG, (1 << core_id)); in imx_set_cpu_pwr_on()
65 mmio_setbits_32(IMX_SRC_BASE + SRC_A53RCR1, (1 << core_id)); in imx_set_cpu_pwr_on()
72 mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id) | in imx_set_cpu_lpm()
75 mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1); in imx_set_cpu_lpm()
94 mmio_setbits_32(IMX_GPC_BASE + SLTx_CFG(0), PLAT_PDN_SLT_CTRL); in imx_a53_plat_slot_config()
95 mmio_setbits_32(IMX_GPC_BASE + SLTx_CFG(3), PLAT_PUP_SLT_CTRL); in imx_a53_plat_slot_config()
98 mmio_setbits_32(IMX_GPC_BASE + PLAT_PGC_PCR, 0x1); in imx_a53_plat_slot_config()
[all …]
/external/arm-trusted-firmware/plat/imx/imx8m/imx8mq/
Dgpc.c23 mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id) | in imx_set_cpu_pwr_off()
26 mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1); in imx_set_cpu_pwr_off()
34 mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id) | in imx_set_cpu_lpm()
37 mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1); in imx_set_cpu_lpm()
43 mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1); in imx_set_cpu_lpm()
51 mmio_setbits_32(IMX_GPC_BASE + SLTx_CFG(0), SLT_PLAT_PDN); in imx_pup_pdn_slot_config()
53 mmio_setbits_32(IMX_GPC_BASE + SLTx_CFG(1), SLT_PLAT_PUP); in imx_pup_pdn_slot_config()
55 mmio_setbits_32(IMX_GPC_BASE + SLTx_CFG(2), SLT_COREx_PUP(last_core)); in imx_pup_pdn_slot_config()
79 mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_BSC2, A53_LPM_STOP); in imx_set_cluster_powerdown()
92 mmio_setbits_32(IMX_GPC_BASE + A53_PLAT_PGC, 0x1); in imx_set_cluster_powerdown()
[all …]
/external/arm-trusted-firmware/plat/mediatek/mt8183/drivers/spmc/
Dmtspmc.c52 mmio_setbits_32(reg, SW_NO_WAIT_Q); in spm_disable_cpu_auto_off()
115 mmio_setbits_32(reg, (arm64 & 1) << (i + cpu)); in mcucfg_init_archstate()
175 mmio_setbits_32(per_cpu(0, 1, SPM_CPU_PWR), PWRCTRL_PWR_RST_B); in spmc_init()
176 mmio_setbits_32(per_cpu(0, 2, SPM_CPU_PWR), PWRCTRL_PWR_RST_B); in spmc_init()
177 mmio_setbits_32(per_cpu(0, 3, SPM_CPU_PWR), PWRCTRL_PWR_RST_B); in spmc_init()
181 mmio_setbits_32(per_cluster(1, SPM_CLUSTER_PWR), PWRCTRL_PWR_RST_B); in spmc_init()
189 mmio_setbits_32(per_cpu(1, 0, SPM_CPU_PWR), PWRCTRL_PWR_RST_B); in spmc_init()
190 mmio_setbits_32(per_cpu(1, 1, SPM_CPU_PWR), PWRCTRL_PWR_RST_B); in spmc_init()
191 mmio_setbits_32(per_cpu(1, 2, SPM_CPU_PWR), PWRCTRL_PWR_RST_B); in spmc_init()
192 mmio_setbits_32(per_cpu(1, 3, SPM_CPU_PWR), PWRCTRL_PWR_RST_B); in spmc_init()
[all …]
/external/arm-trusted-firmware/plat/mediatek/mt8183/
Dbl31_plat_setup.c41 mmio_setbits_32((uintptr_t)&mt8183_mcucfg->bus_pll_divider_cfg, in platform_setup_cpu()
43 mmio_setbits_32((uintptr_t)&mt8183_mcucfg->mp0_pll_divider_cfg, in platform_setup_cpu()
45 mmio_setbits_32((uintptr_t)&mt8183_mcucfg->mp2_pll_divider_cfg, in platform_setup_cpu()
56 mmio_setbits_32((uintptr_t)&mt8183_mcucfg->cci_clk_ctrl, in platform_setup_cpu()
64 mmio_setbits_32((uintptr_t)&mt8183_mcucfg->l2c_sram_ctrl, in platform_setup_cpu()
70 mmio_setbits_32((uintptr_t)&mt8183_mcucfg->mcu_misc_dcm_ctrl, in platform_setup_cpu()
77 mmio_setbits_32((uintptr_t)&mt8183_mcucfg->sync_dcm_cluster_config, in platform_setup_cpu()
80 mmio_setbits_32((uintptr_t)&mt8183_mcucfg->mp0_rgu_dcm_config, in platform_setup_cpu()
/external/arm-trusted-firmware/plat/mediatek/mt8173/
Dbl31_plat_setup.c40 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp1_miscdbg, MP1_AINACTS); in platform_setup_cpu()
41 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp1_clkenm_div, in platform_setup_cpu()
47 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp1_cpucfg, in platform_setup_cpu()
51 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp0_rv_addr[0].rv_addr_hw, in platform_setup_cpu()
55 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->bus_fabric_dcm_ctrl, in platform_setup_cpu()
59 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->l2c_sram_ctrl, in platform_setup_cpu()
61 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->cci_clk_ctrl, in platform_setup_cpu()
Dscu.c15 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp1_miscdbg, in disable_scu()
18 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp0_axi_config, in disable_scu()
/external/arm-trusted-firmware/drivers/st/ddr/
Dstm32mp1_ddr.c398 mmio_setbits_32((uintptr_t)&ctl->swctl, DDRCTRL_SWCTL_SW_DONE); in stm32mp1_wait_sw_done_ack()
534 mmio_setbits_32((uintptr_t)&priv->ctl->dbg1, DDRCTRL_DBG1_DIS_HIF); in stm32mp1_ddr3_dll_off()
594 mmio_setbits_32((uintptr_t)&priv->ctl->pwrctl, in stm32mp1_ddr3_dll_off()
614 mmio_setbits_32((uintptr_t)&priv->ctl->mstr, DDRCTRL_MSTR_DLL_OFF_MODE); in stm32mp1_ddr3_dll_off()
634 mmio_setbits_32((uintptr_t)&priv->phy->dllgcr, in stm32mp1_ddr3_dll_off()
638 mmio_setbits_32((uintptr_t)&priv->phy->acdllcr, DDRPHYC_ACDLLCR_DLLDIS); in stm32mp1_ddr3_dll_off()
640 mmio_setbits_32((uintptr_t)&priv->phy->dx0dllcr, in stm32mp1_ddr3_dll_off()
642 mmio_setbits_32((uintptr_t)&priv->phy->dx1dllcr, in stm32mp1_ddr3_dll_off()
644 mmio_setbits_32((uintptr_t)&priv->phy->dx2dllcr, in stm32mp1_ddr3_dll_off()
646 mmio_setbits_32((uintptr_t)&priv->phy->dx3dllcr, in stm32mp1_ddr3_dll_off()
[all …]
/external/arm-trusted-firmware/plat/allwinner/common/
Dsunxi_common.c102 mmio_setbits_32(port_base + 0x10, BIT(pin)); in sunxi_set_gpio_out()
143 mmio_setbits_32(SUNXI_R_PRCM_BASE + 0x28, BIT(0)); in sunxi_init_platform_r_twi()
156 mmio_setbits_32(SUNXI_R_PRCM_BASE + 0x28, device_bit); in sunxi_init_platform_r_twi()
158 mmio_setbits_32(SUNXI_R_PRCM_BASE + 0x19c, device_bit | BIT(0)); in sunxi_init_platform_r_twi()
162 mmio_setbits_32(SUNXI_R_PRCM_BASE + reset_offset, device_bit); in sunxi_init_platform_r_twi()
202 mmio_setbits_32(SUNXI_R_CPUCFG_BASE, BIT(0)); in sunxi_execute_arisc_code()
Dsunxi_cpu_ops.c62 mmio_setbits_32(SUNXI_POWEROFF_GATING_REG(cluster), in sunxi_cpu_off()
96 mmio_setbits_32(SUNXI_CPUCFG_CLS_CTRL_REG0(cluster), BIT(24 + core)); in sunxi_cpu_on()
102 mmio_setbits_32(SUNXI_POWERON_RST_REG(cluster), BIT(core)); in sunxi_cpu_on()
104 mmio_setbits_32(SUNXI_CPUCFG_RST_CTRL_REG(cluster), BIT(core)); in sunxi_cpu_on()
106 mmio_setbits_32(SUNXI_CPUCFG_DBG_REG0, BIT(core)); in sunxi_cpu_on()
/external/arm-trusted-firmware/plat/hisilicon/hikey960/
Dhikey960_bl1_setup.c124 mmio_setbits_32(UFS_SYS_PHY_CLK_CTRL_REG, BIT_SYSCTRL_REF_CLOCK_EN); in hikey960_ufs_reset()
130 mmio_setbits_32(UFS_SYS_PSW_POWER_CTRL_REG, BIT_UFS_PSW_MTCMOS_EN); in hikey960_ufs_reset()
132 mmio_setbits_32(UFS_SYS_HC_LP_CTRL_REG, BIT_SYSCTRL_PWR_READY); in hikey960_ufs_reset()
147 mmio_setbits_32(UFS_SYS_CLOCK_GATE_BYPASS_REG, in hikey960_ufs_reset()
149 mmio_setbits_32(UFS_SYS_UFS_SYSCTRL_REG, MASK_UFS_SYSCTRL_BYPASS); in hikey960_ufs_reset()
151 mmio_setbits_32(UFS_SYS_PSW_CLK_CTRL_REG, BIT_SYSCTRL_PSW_CLK_EN); in hikey960_ufs_reset()
156 mmio_setbits_32(UFS_SYS_RESET_CTRL_EN_REG, BIT_SYSCTRL_LP_RESET_N); in hikey960_ufs_reset()
Dhikey960_bl2_setup.c99 mmio_setbits_32(UFS_SYS_PHY_CLK_CTRL_REG, BIT_SYSCTRL_REF_CLOCK_EN); in hikey960_ufs_reset()
105 mmio_setbits_32(UFS_SYS_PSW_POWER_CTRL_REG, BIT_UFS_PSW_MTCMOS_EN); in hikey960_ufs_reset()
107 mmio_setbits_32(UFS_SYS_HC_LP_CTRL_REG, BIT_SYSCTRL_PWR_READY); in hikey960_ufs_reset()
122 mmio_setbits_32(UFS_SYS_CLOCK_GATE_BYPASS_REG, in hikey960_ufs_reset()
124 mmio_setbits_32(UFS_SYS_UFS_SYSCTRL_REG, MASK_UFS_SYSCTRL_BYPASS); in hikey960_ufs_reset()
126 mmio_setbits_32(UFS_SYS_PSW_CLK_CTRL_REG, BIT_SYSCTRL_PSW_CLK_EN); in hikey960_ufs_reset()
131 mmio_setbits_32(UFS_SYS_RESET_CTRL_EN_REG, BIT_SYSCTRL_LP_RESET_N); in hikey960_ufs_reset()
/external/arm-trusted-firmware/plat/mediatek/mt8173/drivers/mtcmos/
Dmtcmos.c136 mmio_setbits_32(reg_pwr_con, PWR_ISO); in mtcmos_ctrl_little_off()
137 mmio_setbits_32(reg_pwr_con, SRAM_CKISO); in mtcmos_ctrl_little_off()
139 mmio_setbits_32(reg_l1_pdn, L1_PDN); in mtcmos_ctrl_little_off()
145 mmio_setbits_32(reg_pwr_con, PWR_CLK_DIS); in mtcmos_ctrl_little_off()
204 mmio_setbits_32(SPM_PCM_RESERVE, MTCMOS_CTRL_EN); in mtcmos_non_cpu_ctrl()
264 mmio_setbits_32(SPM_PCM_RESERVE2, power_ctrl); in mtcmos_non_cpu_ctrl()
/external/arm-trusted-firmware/drivers/st/gpio/
Dstm32_gpio.c214 mmio_setbits_32(base + GPIO_MODE_OFFSET, in set_gpio()
218 mmio_setbits_32(base + GPIO_TYPE_OFFSET, BIT(pin)); in set_gpio()
225 mmio_setbits_32(base + GPIO_SPEED_OFFSET, speed << (pin << 1)); in set_gpio()
229 mmio_setbits_32(base + GPIO_PUPD_OFFSET, pull << (pin << 1)); in set_gpio()
234 mmio_setbits_32(base + GPIO_AFRL_OFFSET, in set_gpio()
240 mmio_setbits_32(base + GPIO_AFRH_OFFSET, in set_gpio()
269 mmio_setbits_32(base + GPIO_SECR_OFFSET, BIT(pin)); in set_gpio_secure_cfg()
/external/arm-trusted-firmware/plat/intel/soc/common/soc/
Dsocfpga_reset_manager.c87 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKEN), or_mask); in config_hps_hs_before_warm_reset()
105 mmio_setbits_32(SOCFPGA_SYSMGR(NOC_IDLEREQ_CLR), ~0); in socfpga_bridges_enable()
121 mmio_setbits_32(SOCFPGA_SYSMGR(NOC_TIMEOUT), 1); in socfpga_bridges_disable()
135 mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST), in socfpga_bridges_disable()
138 mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST), in socfpga_bridges_disable()
/external/arm-trusted-firmware/plat/mediatek/mt8183/drivers/gpio/
Dmtgpio.c241 mmio_setbits_32(pupd_addr, 1U << pupd_offset); in mt_set_gpio_pull_enable_chip()
245 mmio_setbits_32(pullen_addr, in mt_set_gpio_pull_enable_chip()
250 mmio_setbits_32(pupd_addr, 1U << pupd_offset); in mt_set_gpio_pull_enable_chip()
256 mmio_setbits_32(pupd_addr, 1U << (pupd_offset + 1)); in mt_set_gpio_pull_enable_chip()
259 mmio_setbits_32(pupd_addr, 3U << pupd_offset); in mt_set_gpio_pull_enable_chip()
302 mmio_setbits_32(pupd_addr, 1U << (pupd_offset + 2)); in mt_set_gpio_pull_select_chip()
311 mmio_setbits_32(pullsel_addr, in mt_set_gpio_pull_select_chip()
316 mmio_setbits_32(pupd_addr, 1U << (pupd_offset + 2)); in mt_set_gpio_pull_select_chip()
/external/arm-trusted-firmware/plat/intel/soc/common/
Dsocfpga_psci.c50 mmio_setbits_32(SOCFPGA_RSTMGR(MPUMODRST), 1 << cpu_id); in socfpga_pwr_domain_on()
81 mmio_setbits_32(SOCFPGA_RSTMGR(MPUMODRST), 1 << cpu_id); in socfpga_pwr_domain_suspend()
154 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKEN), RSTMGR_HDSKEN_SET); in socfpga_system_reset2()
157 mmio_setbits_32(SOCFPGA_RSTMGR(COLDMODRST), 0x100); in socfpga_system_reset2()
/external/arm-trusted-firmware/plat/rockchip/rk3399/drivers/m0/src/
Ddram.c21 mmio_setbits_32(PMU_BASE + PMU_BUS_IDLE_REQ, in idle_port()
60 mmio_setbits_32(PHY_REG(0, 927), (1 << 22)); in m0_main()
61 mmio_setbits_32(PHY_REG(1, 927), (1 << 22)); in m0_main()
/external/arm-trusted-firmware/plat/arm/board/n1sdp/
Dn1sdp_bl31_setup.c117 mmio_setbits_32(N1SDP_DMC0_ERR0CTLR0_REG, N1SDP_DMC_ERR0CTLR0_ECC_EN); in dmc_ecc_setup()
118 mmio_setbits_32(N1SDP_DMC1_ERR0CTLR0_REG, N1SDP_DMC_ERR0CTLR0_ECC_EN); in dmc_ecc_setup()
147 mmio_setbits_32(N1SDP_REMOTE_DMC0_ERR0CTLR0_REG, in remote_dmc_ecc_setup()
149 mmio_setbits_32(N1SDP_REMOTE_DMC1_ERR0CTLR0_REG, in remote_dmc_ecc_setup()
/external/arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/
Dspm_suspend.c284 mmio_setbits_32(ARMCA15PLL_PWR_CON0, ARMCA15PLL_PWR_ON); in bigcore_pll_on()
286 mmio_setbits_32(ARMCA15PLL_CON0, ARMCA15PLL_EN); in bigcore_pll_on()
292 mmio_setbits_32(ARMCA15PLL_PWR_CON0, ARMCA15PLL_ISO_EN); in bigcore_pll_off()
/external/arm-trusted-firmware/plat/mediatek/mt6795/
Dscu.c15 mmio_setbits_32((uintptr_t)&mt6795_mcucfg->mp1_miscdbg, in disable_scu()
18 mmio_setbits_32((uintptr_t)&mt6795_mcucfg->mp0_axi_config, in disable_scu()
/external/arm-trusted-firmware/plat/rockchip/rk3399/drivers/dram/
Dsuspend.c198 mmio_setbits_32(PHY_REG(ch, 927), (1 << 22)); in data_training()
475 mmio_setbits_32(CTL_REG(i, 276), 1 << 17); in dram_all_config()
516 mmio_setbits_32(PI_REG(ch, 0), START); in pctl_cfg()
517 mmio_setbits_32(CTL_REG(ch, 0), START); in pctl_cfg()
586 mmio_setbits_32(CTL_REG(0, 68), PWRUP_SREFRESH_EXIT); in pctl_start()
587 mmio_setbits_32(CTL_REG(1, 68), PWRUP_SREFRESH_EXIT); in pctl_start()
591 mmio_setbits_32(PMU_BASE + PMU_PWRMODE_CON, (1 << 19)); in pctl_start()
593 mmio_setbits_32(PMU_BASE + PMU_PWRMODE_CON, (1 << 23)); in pctl_start()
676 mmio_setbits_32(WDT0_BASE, 0x1); in pmusram_enable_watchdog()
/external/arm-trusted-firmware/plat/mediatek/mt8183/drivers/spm/
Dspm.c234 mmio_setbits_32(PCM_CON1, SPM_REGWR_CFG_KEY | PCM_TIMER_EN_LSB); in spm_set_wakeup_event()
263 mmio_setbits_32(PCM_CON1, SPM_REGWR_CFG_KEY | PCM_WDT_EN_LSB); in spm_set_pcm_wdt()
304 mmio_setbits_32(SPM_IRQ_MASK, ISRM_ALL_EXC_TWAM); in spm_clean_after_wakeup()
354 mmio_setbits_32(CLK_SCP_CFG_0, SPM_CK_OFF_CONTROL); in spm_boot_init()
355 mmio_setbits_32(CLK_SCP_CFG_1, SPM_AXI_26M_SEL); in spm_boot_init()
Dspm_suspend.c213 mmio_setbits_32(ARMPLL_L_PWR_CON0, 0x1); in spm_enable_armpll_l()
219 mmio_setbits_32(ARMPLL_L_CON0, 0x1); in spm_enable_armpll_l()
231 mmio_setbits_32(ARMPLL_L_PWR_CON0, 0x2); in spm_disable_armpll_l()
/external/arm-trusted-firmware/plat/mediatek/mt8183/drivers/mcsi/
Dmcsi.c56 mmio_setbits_32(CCI_CLK_CTRL, 1 << 8); in mcsi_cache_flush()
180 mmio_setbits_32(cci_base_addr + CENTRAL_CTRL_REG, INT_EN); in cci_interrupt_en()
200 mmio_setbits_32(cci_base_addr + offset, val); in cci_reg_access()

123