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Searched refs:params_from_bl2 (Results 1 – 18 of 18) sorted by relevance

/external/arm-trusted-firmware/plat/qemu/common/
Dqemu_bl31_setup.c38 bl_params_t *params_from_bl2 = (bl_params_t *)arg0; in bl31_early_platform_setup2() local
40 assert(params_from_bl2); in bl31_early_platform_setup2()
41 assert(params_from_bl2->h.type == PARAM_BL_PARAMS); in bl31_early_platform_setup2()
42 assert(params_from_bl2->h.version >= VERSION_2); in bl31_early_platform_setup2()
44 bl_params_node_t *bl_params = params_from_bl2->head; in bl31_early_platform_setup2()
/external/arm-trusted-firmware/plat/hisilicon/poplar/
Dbl31_plat_setup.c80 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; in bl31_early_platform_setup2() local
82 assert(params_from_bl2 != NULL); in bl31_early_platform_setup2()
83 assert(params_from_bl2->h.type == PARAM_BL_PARAMS); in bl31_early_platform_setup2()
84 assert(params_from_bl2->h.version >= VERSION_2); in bl31_early_platform_setup2()
86 bl_params_node_t *bl_params = params_from_bl2->head; in bl31_early_platform_setup2()
/external/arm-trusted-firmware/plat/nvidia/tegra/soc/t194/
Dplat_secondary.c27 plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); in plat_secondary_setup() local
39 memcpy((void *)((uintptr_t)params_from_bl2->tzdram_base), in plat_secondary_setup()
44 addr_low = (uint32_t)params_from_bl2->tzdram_base | CPU_RESET_MODE_AA64; in plat_secondary_setup()
45 addr_high = (uint32_t)((params_from_bl2->tzdram_base >> 32U) & 0x7ffU); in plat_secondary_setup()
Dplat_psci_handlers.c126 plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); in tegra_soc_pwr_domain_suspend() local
161 smmu_ctx_base = params_from_bl2->tzdram_base + in tegra_soc_pwr_domain_suspend()
300 plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); in tegra_soc_pwr_domain_power_down_wfi() local
312 val = params_from_bl2->tzdram_base + in tegra_soc_pwr_domain_power_down_wfi()
/external/arm-trusted-firmware/plat/nvidia/tegra/soc/t186/
Dplat_secondary.c34 const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); in plat_secondary_setup() local
46 (void)memcpy16((void *)(uintptr_t)params_from_bl2->tzdram_base, in plat_secondary_setup()
51 addr_low = (uint32_t)params_from_bl2->tzdram_base | CPU_RESET_MODE_AA64; in plat_secondary_setup()
52 addr_high = (uint32_t)((params_from_bl2->tzdram_base >> 32U) & 0x7ffU); in plat_secondary_setup()
Dplat_psci_handlers.c91 const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); in tegra_soc_pwr_domain_suspend() local
127 smmu_ctx_base = params_from_bl2->tzdram_base + in tegra_soc_pwr_domain_suspend()
272 const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); in tegra_soc_pwr_domain_power_down_wfi() local
283 val = params_from_bl2->tzdram_base + in tegra_soc_pwr_domain_power_down_wfi()
/external/arm-trusted-firmware/plat/hisilicon/hikey/
Dhikey_bl31_setup.c90 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; in bl31_early_platform_setup2() local
91 assert(params_from_bl2 != NULL); in bl31_early_platform_setup2()
92 assert(params_from_bl2->h.type == PARAM_BL_PARAMS); in bl31_early_platform_setup2()
93 assert(params_from_bl2->h.version >= VERSION_2); in bl31_early_platform_setup2()
95 bl_params_node_t *bl_params = params_from_bl2->head; in bl31_early_platform_setup2()
/external/arm-trusted-firmware/plat/qemu/common/sp_min/
Dsp_min_setup.c93 bl_params_t *params_from_bl2 = (bl_params_t *)arg0; in sp_min_early_platform_setup2() local
102 assert(params_from_bl2); in sp_min_early_platform_setup2()
103 assert(params_from_bl2->h.type == PARAM_BL_PARAMS); in sp_min_early_platform_setup2()
104 assert(params_from_bl2->h.version >= VERSION_2); in sp_min_early_platform_setup2()
106 bl_params_node_t *bl_params = params_from_bl2->head; in sp_min_early_platform_setup2()
/external/arm-trusted-firmware/plat/marvell/common/
Dmarvell_bl31_setup.c113 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; in marvell_bl31_early_platform_setup() local
114 assert(params_from_bl2 != NULL); in marvell_bl31_early_platform_setup()
115 assert(params_from_bl2->h.type == PARAM_BL_PARAMS); in marvell_bl31_early_platform_setup()
116 assert(params_from_bl2->h.version >= VERSION_2); in marvell_bl31_early_platform_setup()
118 bl_params_node_t *bl_params = params_from_bl2->head; in marvell_bl31_early_platform_setup()
/external/arm-trusted-firmware/plat/intel/soc/agilex/
Dbl31_plat_setup.c46 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; in bl31_early_platform_setup2() local
48 assert(params_from_bl2 != NULL); in bl31_early_platform_setup2()
49 assert(params_from_bl2->h.type == PARAM_BL_PARAMS); in bl31_early_platform_setup2()
50 assert(params_from_bl2->h.version >= VERSION_2); in bl31_early_platform_setup2()
57 bl_params_node_t *bl_params = params_from_bl2->head; in bl31_early_platform_setup2()
/external/arm-trusted-firmware/plat/rpi/rpi3/
Drpi3_bl31_setup.c84 bl_params_t *params_from_bl2 = (bl_params_t *) arg0; in bl31_early_platform_setup2() local
86 assert(params_from_bl2 != NULL); in bl31_early_platform_setup2()
87 assert(params_from_bl2->h.type == PARAM_BL_PARAMS); in bl31_early_platform_setup2()
88 assert(params_from_bl2->h.version >= VERSION_2); in bl31_early_platform_setup2()
90 bl_params_node_t *bl_params = params_from_bl2->head; in bl31_early_platform_setup2()
/external/arm-trusted-firmware/plat/arm/common/sp_min/
Darm_sp_min_setup.c105 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; in arm_sp_min_early_platform_setup() local
106 assert(params_from_bl2 != NULL); in arm_sp_min_early_platform_setup()
107 assert(params_from_bl2->h.type == PARAM_BL_PARAMS); in arm_sp_min_early_platform_setup()
108 assert(params_from_bl2->h.version >= VERSION_2); in arm_sp_min_early_platform_setup()
110 bl_params_node_t *bl_params = params_from_bl2->head; in arm_sp_min_early_platform_setup()
/external/arm-trusted-firmware/plat/layerscape/common/
Dls_bl31_setup.c118 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; in ls_bl31_early_platform_setup() local
120 assert(params_from_bl2 != NULL); in ls_bl31_early_platform_setup()
121 assert(params_from_bl2->h.type == PARAM_BL_PARAMS); in ls_bl31_early_platform_setup()
122 assert(params_from_bl2->h.version >= VERSION_2); in ls_bl31_early_platform_setup()
124 bl_params_node_t *bl_params = params_from_bl2->head; in ls_bl31_early_platform_setup()
/external/arm-trusted-firmware/plat/intel/soc/stratix10/
Dbl31_plat_setup.c56 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; in bl31_early_platform_setup2() local
57 assert(params_from_bl2 != NULL); in bl31_early_platform_setup2()
64 if (params_from_bl2->h.type == PARAM_BL_PARAMS && in bl31_early_platform_setup2()
65 params_from_bl2->h.version >= VERSION_2) { in bl31_early_platform_setup2()
67 bl_params_node_t *bl_params = params_from_bl2->head; in bl31_early_platform_setup2()
/external/arm-trusted-firmware/plat/hisilicon/hikey960/
Dhikey960_bl31_setup.c95 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; in bl31_early_platform_setup2() local
96 assert(params_from_bl2 != NULL); in bl31_early_platform_setup2()
97 assert(params_from_bl2->h.type == PARAM_BL_PARAMS); in bl31_early_platform_setup2()
98 assert(params_from_bl2->h.version >= VERSION_2); in bl31_early_platform_setup2()
100 bl_params_node_t *bl_params = params_from_bl2->head; in bl31_early_platform_setup2()
/external/arm-trusted-firmware/plat/arm/common/
Darm_bl31_setup.c152 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; in arm_bl31_early_platform_setup() local
153 assert(params_from_bl2 != NULL); in arm_bl31_early_platform_setup()
154 assert(params_from_bl2->h.type == PARAM_BL_PARAMS); in arm_bl31_early_platform_setup()
155 assert(params_from_bl2->h.version >= VERSION_2); in arm_bl31_early_platform_setup()
157 bl_params_node_t *bl_params = params_from_bl2->head; in arm_bl31_early_platform_setup()
/external/arm-trusted-firmware/plat/nvidia/tegra/common/drivers/smmu/
Dsmmu.c81 const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); in tegra_smmu_save_context() local
82 uint64_t tzdram_base = params_from_bl2->tzdram_base; in tegra_smmu_save_context()
83 uint64_t tzdram_end = tzdram_base + params_from_bl2->tzdram_size; in tegra_smmu_save_context()
/external/arm-trusted-firmware/plat/nvidia/tegra/common/
Dtegra_bl31_setup.c389 const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); in bl31_plat_arch_setup() local
426 mmap_add_region(params_from_bl2->tzdram_base, in bl31_plat_arch_setup()
427 params_from_bl2->tzdram_base, in bl31_plat_arch_setup()