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/external/elfutils/tests/
Drun-show-die-info.sh28 Offset : 11
29 CU offset : 11
38 Offset : 104
39 CU offset : 104
45 Offset : 127
46 CU offset : 127
52 Offset : 146
53 CU offset : 11
62 Offset : 239
63 CU offset : 104
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Drun-show-abbrev.sh25 abbrev[0]: attr[0]: code = 16, form = 6, offset = 0
26 abbrev[0]: attr[1]: code = 18, form = 1, offset = 2
27 abbrev[0]: attr[2]: code = 17, form = 1, offset = 4
28 abbrev[0]: attr[3]: code = 3, form = 8, offset = 6
29 abbrev[0]: attr[4]: code = 27, form = 8, offset = 8
30 abbrev[0]: attr[5]: code = 37, form = 8, offset = 10
31 abbrev[0]: attr[6]: code = 19, form = 11, offset = 12
33 abbrev[19]: attr[0]: code = 1, form = 19, offset = 19
34 abbrev[19]: attr[1]: code = 63, form = 12, offset = 21
35 abbrev[19]: attr[2]: code = 3, form = 8, offset = 23
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/external/mesa3d/src/freedreno/registers/dsi/
Ddsi.xml66 <reg32 offset="0x00000" name="6G_HW_VERSION">
72 <reg32 offset="0x00000" name="CTRL">
85 <reg32 offset="0x00004" name="STATUS0">
94 <reg32 offset="0x00008" name="FIFO_STATUS">
121 <reg32 offset="0x0000c" name="VID_CFG0">
132 <reg32 offset="0x0001c" name="VID_CFG1">
138 <reg32 offset="0x00020" name="ACTIVE_H">
142 <reg32 offset="0x00024" name="ACTIVE_V">
146 <reg32 offset="0x00028" name="TOTAL">
150 <reg32 offset="0x0002c" name="ACTIVE_HSYNC">
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/external/llvm-project/llvm/docs/
Dloop-terminology.svg122 <stop stop-color="#fff" offset="0"/>
123 <stop stop-color="#fff" offset=".0625"/>
124 <stop stop-color="#fefefe" offset=".09375"/>
125 <stop stop-color="#fefefe" offset=".097656"/>
126 <stop stop-color="#fdfefe" offset=".10156"/>
127 <stop stop-color="#fdfefe" offset=".10547"/>
128 <stop stop-color="#fcfdfd" offset=".10938"/>
129 <stop stop-color="#fbfdfd" offset=".11328"/>
130 <stop stop-color="#fbfdfd" offset=".11719"/>
131 <stop stop-color="#fafcfc" offset=".12109"/>
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Dloop-nonmaximal.svg58 <stop offset="0" style="stop-color:rgb(100%,100%,100%);stop-opacity:1;"/>
59 <stop offset="0.0625" style="stop-color:rgb(100%,100%,100%);stop-opacity:1;"/>
60 <stop offset="0.09375" style="stop-color:rgb(99.987793%,99.993896%,99.993896%);stop-opacity:1;"/>
61 <stop offset="0.0976562" style="stop-color:rgb(99.734497%,99.867249%,99.867249%);stop-opacity:1;"/>
62 <stop offset="0.101562" style="stop-color:rgb(99.494934%,99.746704%,99.746704%);stop-opacity:1;"/>
63 <stop offset="0.105469" style="stop-color:rgb(99.253845%,99.62616%,99.62616%);stop-opacity:1;"/>
64 <stop offset="0.109375" style="stop-color:rgb(99.014282%,99.507141%,99.507141%);stop-opacity:1;"/>
65 <stop offset="0.113281" style="stop-color:rgb(98.774719%,99.386597%,99.386597%);stop-opacity:1;"/>
66 <stop offset="0.117188" style="stop-color:rgb(98.535156%,99.267578%,99.267578%);stop-opacity:1;"/>
67 <stop offset="0.121094" style="stop-color:rgb(98.294067%,99.147034%,99.147034%);stop-opacity:1;"/>
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Dloop-irreducible.svg40 <stop offset="0" style="stop-color:rgb(100%,100%,100%);stop-opacity:1;"/>
41 <stop offset="0.0625" style="stop-color:rgb(100%,100%,100%);stop-opacity:1;"/>
42 <stop offset="0.09375" style="stop-color:rgb(99.987793%,99.993896%,99.993896%);stop-opacity:1;"/>
43 <stop offset="0.0976563" style="stop-color:rgb(99.736023%,99.867249%,99.867249%);stop-opacity:1;"/>
44 <stop offset="0.101562" style="stop-color:rgb(99.49646%,99.74823%,99.74823%);stop-opacity:1;"/>
45 <stop offset="0.105469" style="stop-color:rgb(99.255371%,99.627686%,99.627686%);stop-opacity:1;"/>
46 <stop offset="0.109375" style="stop-color:rgb(99.015808%,99.507141%,99.507141%);stop-opacity:1;"/>
47 <stop offset="0.113281" style="stop-color:rgb(98.774719%,99.386597%,99.386597%);stop-opacity:1;"/>
48 <stop offset="0.117188" style="stop-color:rgb(98.535156%,99.267578%,99.267578%);stop-opacity:1;"/>
49 <stop offset="0.121094" style="stop-color:rgb(98.294067%,99.147034%,99.147034%);stop-opacity:1;"/>
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/external/mesa3d/src/freedreno/fdl/
Dfd6_layout_test.c39 { .offset = 0, .pitch = 256 },
40 { .offset = 8192, .pitch = 256 },
41 { .offset = 12288, .pitch = 256 },
42 { .offset = 14336, .pitch = 256 },
43 { .offset = 15360, .pitch = 256 },
44 { .offset = 15872, .pitch = 256 },
59 { .offset = 0, .pitch = 4096 },
60 { .offset = 65536, .pitch = 2048 },
61 { .offset = 98304, .pitch = 1024 },
62 { .offset = 114688, .pitch = 512 },
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/external/mesa3d/src/freedreno/registers/hdmi/
Dhdmi.xml35 <reg32 offset="0x00000" name="CTRL">
40 <reg32 offset="0x00020" name="AUDIO_PKT_CTRL1">
43 <reg32 offset="0x00024" name="ACR_PKT_CTRL">
60 <reg32 offset="0x0028" name="VBI_PKT_CTRL">
80 <reg32 offset="0x0002c" name="INFOFRAME_CTRL0">
97 <reg32 offset="0x00030" name="INFOFRAME_CTRL1">
103 <reg32 offset="0x00034" name="GEN_PKT_CTRL">
133 <reg32 offset="0x00040" name="GC">
136 <reg32 offset="0x00044" name="AUDIO_PKT_CTRL2">
145 <reg32 offset="0x0006c" name="AVI_INFO" stride="4" length="4"/>
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/external/mesa3d/src/freedreno/registers/adreno/
Da6xx_gmu.xml42 <reg32 offset="0x80" name="GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL"/>
43 <reg32 offset="0x81" name="GMU_GX_SPTPRAC_POWER_CONTROL"/>
44 <reg32 offset="0xc00" name="GMU_CM3_ITCM_START"/>
45 <reg32 offset="0x1c00" name="GMU_CM3_DTCM_START"/>
46 <reg32 offset="0x23f0" name="GMU_NMI_CONTROL_STATUS"/>
47 <reg32 offset="0x23f8" name="GMU_BOOT_SLUMBER_OPTION"/>
48 <reg32 offset="0x23f9" name="GMU_GX_VOTE_IDX"/>
49 <reg32 offset="0x23fa" name="GMU_MX_VOTE_IDX"/>
50 <reg32 offset="0x23fc" name="GMU_DCVS_ACK_OPTION"/>
51 <reg32 offset="0x23fd" name="GMU_DCVS_PERF_SETTING"/>
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Da5xx.xml862 <reg32 offset="0x0800" name="CP_RB_BASE"/>
863 <reg32 offset="0x0801" name="CP_RB_BASE_HI"/>
864 <reg32 offset="0x0802" name="CP_RB_CNTL"/>
865 <reg32 offset="0x0804" name="CP_RB_RPTR_ADDR"/>
866 <reg32 offset="0x0805" name="CP_RB_RPTR_ADDR_HI"/>
867 <reg32 offset="0x0806" name="CP_RB_RPTR"/>
868 <reg32 offset="0x0807" name="CP_RB_WPTR"/>
869 <reg32 offset="0x0808" name="CP_PFP_STAT_ADDR"/>
870 <reg32 offset="0x0809" name="CP_PFP_STAT_DATA"/>
871 <reg32 offset="0x080b" name="CP_DRAW_STATE_ADDR"/>
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Da6xx.xml967 <reg32 offset="0x0800" name="CP_RB_BASE"/>
968 <reg32 offset="0x0801" name="CP_RB_BASE_HI"/>
969 <reg32 offset="0x0802" name="CP_RB_CNTL"/>
970 <reg32 offset="0x0804" name="CP_RB_RPTR_ADDR_LO"/>
971 <reg32 offset="0x0805" name="CP_RB_RPTR_ADDR_HI"/>
972 <reg32 offset="0x0806" name="CP_RB_RPTR"/>
973 <reg32 offset="0x0807" name="CP_RB_WPTR"/>
974 <reg32 offset="0x0808" name="CP_SQE_CNTL"/>
975 <reg32 offset="0x0812" name="CP_CP2GMU_STATUS">
978 <reg32 offset="0x0821" name="CP_HW_FAULT"/>
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Da4xx.xml865 <reg32 offset="0x0cc0" name="RB_GMEM_BASE_ADDR"/>
866 <reg32 offset="0x0cc7" name="RB_PERFCTR_RB_SEL_0" type="a4xx_rb_perfcounter_select"/>
867 <reg32 offset="0x0cc8" name="RB_PERFCTR_RB_SEL_1" type="a4xx_rb_perfcounter_select"/>
868 <reg32 offset="0x0cc9" name="RB_PERFCTR_RB_SEL_2" type="a4xx_rb_perfcounter_select"/>
869 <reg32 offset="0x0cca" name="RB_PERFCTR_RB_SEL_3" type="a4xx_rb_perfcounter_select"/>
870 <reg32 offset="0x0ccb" name="RB_PERFCTR_RB_SEL_4" type="a4xx_rb_perfcounter_select"/>
871 <reg32 offset="0x0ccc" name="RB_PERFCTR_RB_SEL_5" type="a4xx_rb_perfcounter_select"/>
872 <reg32 offset="0x0ccd" name="RB_PERFCTR_RB_SEL_6" type="a4xx_rb_perfcounter_select"/>
873 <reg32 offset="0x0cce" name="RB_PERFCTR_RB_SEL_7" type="a4xx_rb_perfcounter_select"/>
874 <reg32 offset="0x0ccf" name="RB_PERFCTR_CCU_SEL_0" type="a4xx_ccu_perfcounter_select"/>
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/external/tpm2-tss/include/tss2/
Dtss2_mu.h28 size_t *offset);
34 size_t *offset,
42 size_t *offset);
48 size_t *offset,
56 size_t *offset);
62 size_t *offset,
70 size_t *offset);
76 size_t *offset,
84 size_t *offset);
90 size_t *offset,
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/external/llvm-project/lldb/unittests/Utility/
DDataExtractorTest.cpp21 lldb::offset_t offset; in TEST() local
23 offset = 0; in TEST()
24 ASSERT_EQ(buffer[1], LE.GetMaxU64Bitfield(&offset, sizeof(buffer), 8, 8)); in TEST()
25 offset = 0; in TEST()
26 ASSERT_EQ(buffer[1], BE.GetMaxU64Bitfield(&offset, sizeof(buffer), 8, 8)); in TEST()
27 offset = 0; in TEST()
29 LE.GetMaxU64Bitfield(&offset, sizeof(buffer), 64, 0)); in TEST()
30 offset = 0; in TEST()
32 BE.GetMaxU64Bitfield(&offset, sizeof(buffer), 64, 0)); in TEST()
33 offset = 0; in TEST()
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/external/libnetfilter_conntrack/src/expect/
Dsnprintf_xml.c57 unsigned int size = 0, offset = 0; in snprintf_expect_meta_xml() local
60 BUFFER_SIZE(ret, size, len, offset); in snprintf_expect_meta_xml()
63 ret = snprintf(buf+offset, len, in snprintf_expect_meta_xml()
66 BUFFER_SIZE(ret, size, len, offset); in snprintf_expect_meta_xml()
69 ret = snprintf(buf+offset, len, "<timeout>%u</timeout>", in snprintf_expect_meta_xml()
71 BUFFER_SIZE(ret, size, len, offset); in snprintf_expect_meta_xml()
74 ret = snprintf(buf+offset, len, "<class>%u</class>", in snprintf_expect_meta_xml()
76 BUFFER_SIZE(ret, size, len, offset); in snprintf_expect_meta_xml()
79 ret = snprintf(buf+offset, len, "<zone>%u</zone>", exp->zone); in snprintf_expect_meta_xml()
80 BUFFER_SIZE(ret, size, len, offset); in snprintf_expect_meta_xml()
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/external/llvm/unittests/Support/
DDataExtractorTest.cpp28 uint32_t offset = 0; in TEST() local
30 EXPECT_EQ(0x80U, DE.getU8(&offset)); in TEST()
31 EXPECT_EQ(1U, offset); in TEST()
32 offset = 0; in TEST()
33 EXPECT_EQ(0x8090U, DE.getU16(&offset)); in TEST()
34 EXPECT_EQ(2U, offset); in TEST()
35 offset = 0; in TEST()
36 EXPECT_EQ(0x8090FFFFU, DE.getU32(&offset)); in TEST()
37 EXPECT_EQ(4U, offset); in TEST()
38 offset = 0; in TEST()
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/external/llvm-project/llvm/test/tools/llvm-pdbutil/
Dexplain-dbi-stream.test4 ; RUN: -offset=0xF000 \
5 ; RUN: -offset=0xF004 \
6 ; RUN: -offset=0xF008 \
7 ; RUN: -offset=0xF00C \
8 ; RUN: -offset=0xF00E \
9 ; RUN: -offset=0xF010 \
10 ; RUN: -offset=0xF012 \
11 ; RUN: -offset=0xF014 \
12 ; RUN: -offset=0xF016 \
13 ; RUN: -offset=0xF018 \
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/external/mesa3d/src/freedreno/registers/mdp/
Dmdp4.xml103 <array offset="0x400" name="MV" length="9" stride="4">
104 <reg32 offset="0" name="VAL"/>
106 <array offset="0x500" name="PRE_BV" length="3" stride="4">
107 <reg32 offset="0" name="VAL"/>
109 <array offset="0x580" name="POST_BV" length="3" stride="4">
110 <reg32 offset="0" name="VAL"/>
112 <array offset="0x600" name="PRE_LV" length="6" stride="4">
113 <reg32 offset="0" name="VAL"/>
115 <array offset="0x680" name="POST_LV" length="6" stride="4">
116 <reg32 offset="0" name="VAL"/>
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/external/vixl/test/aarch32/
Dtest-assembler-cond-rd-memop-immediate-512-a32.cc73 int32_t offset; member
100 const TestData kTests[] = {{{pl, r13, r0, plus, 0, Offset},
103 "pl r13 r0 plus 0 Offset",
105 {{ge, r5, r3, plus, 0, Offset},
108 "ge r5 r3 plus 0 Offset",
110 {{cc, r0, r4, plus, 0, Offset},
113 "cc r0 r4 plus 0 Offset",
115 {{ge, r0, r0, plus, 0, Offset},
118 "ge r0 r0 plus 0 Offset",
120 {{eq, r12, r3, plus, 0, Offset},
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Dtest-assembler-cond-rd-memop-immediate-8192-a32.cc73 int32_t offset; member
100 const TestData kTests[] = {{{pl, r13, r0, plus, 0, Offset},
103 "pl r13 r0 plus 0 Offset",
105 {{ge, r5, r3, plus, 0, Offset},
108 "ge r5 r3 plus 0 Offset",
110 {{cc, r0, r4, plus, 0, Offset},
113 "cc r0 r4 plus 0 Offset",
115 {{ge, r0, r0, plus, 0, Offset},
118 "ge r0 r0 plus 0 Offset",
120 {{eq, r12, r3, plus, 0, Offset},
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Dtest-assembler-cond-rd-memop-rs-a32.cc104 const TestData kTests[] = {{{pl, r8, r11, plus, r6, Offset},
107 "pl r8 r11 plus r6 Offset",
109 {{le, r4, r8, plus, r5, Offset},
112 "le r4 r8 plus r5 Offset",
114 {{vs, r2, r6, plus, r14, Offset},
117 "vs r2 r6 plus r14 Offset",
119 {{ls, r1, r7, plus, r8, Offset},
122 "ls r1 r7 plus r8 Offset",
124 {{ge, r14, r6, plus, r14, Offset},
127 "ge r14 r6 plus r14 Offset",
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/external/flatbuffers/tests/
Dmonster_test_generated.ts115 * @returns flatbuffers.Offset
117 static endInParentNamespace(builder:flatbuffers.Builder):flatbuffers.Offset {
118 var offset = builder.endObject();
119 return offset;
122 static createInParentNamespace(builder:flatbuffers.Builder):flatbuffers.Offset {
175 * @returns flatbuffers.Offset
177 static endMonster(builder:flatbuffers.Builder):flatbuffers.Offset {
178 var offset = builder.endObject();
179 return offset;
182 static createMonster(builder:flatbuffers.Builder):flatbuffers.Offset {
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/external/mesa3d/src/util/
Dvma.c32 uint64_t offset; member
69 assert(hole->offset > 0); in util_vma_heap_validate()
76 assert(hole->size + hole->offset == 0 || in util_vma_heap_validate()
77 hole->size + hole->offset > hole->offset); in util_vma_heap_validate()
81 * hole->size + hole->offset == prev_offset, then we failed to join in util_vma_heap_validate()
84 assert(hole->size + hole->offset > hole->offset && in util_vma_heap_validate()
85 hole->size + hole->offset < prev_offset); in util_vma_heap_validate()
87 prev_offset = hole->offset; in util_vma_heap_validate()
96 uint64_t offset, uint64_t size) in util_vma_hole_alloc() argument
98 assert(hole->offset <= offset); in util_vma_hole_alloc()
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/external/angle/third_party/vulkan-deps/glslang/src/Test/baseResults/
Dreflection.vert.out3 named.deadMember1: offset 0, type 8b51, size 1, index 0, binding -1, stages 1
4 anonDeadMember2: offset 64, type 8b52, size 1, index 1, binding -1, stages 1
5 ufDead4: offset -1, type 1406, size 1, index -1, binding -1, stages 1
6 anonMember1: offset 0, type 8b51, size 1, index 1, binding -1, stages 1
7 uf1: offset -1, type 1406, size 1, index -1, binding -1, stages 1
8 uf2: offset -1, type 1406, size 1, index -1, binding -1, stages 1
9 named.member3: offset 32, type 8b52, size 1, index 0, binding -1, stages 1
10 image_ui2D: offset -1, type 9063, size 1, index -1, binding -1, stages 1
11 sampler_2D: offset -1, type 8b5e, size 1, index -1, binding -1, stages 1
12 sampler_2DMSArray: offset -1, type 910b, size 1, index -1, binding -1, stages 1
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/external/deqp-deps/glslang/Test/baseResults/
Dreflection.vert.out3 named.deadMember1: offset 0, type 8b51, size 1, index 0, binding -1, stages 1
4 anonDeadMember2: offset 64, type 8b52, size 1, index 1, binding -1, stages 1
5 ufDead4: offset -1, type 1406, size 1, index -1, binding -1, stages 1
6 anonMember1: offset 0, type 8b51, size 1, index 1, binding -1, stages 1
7 uf1: offset -1, type 1406, size 1, index -1, binding -1, stages 1
8 uf2: offset -1, type 1406, size 1, index -1, binding -1, stages 1
9 named.member3: offset 32, type 8b52, size 1, index 0, binding -1, stages 1
10 image_ui2D: offset -1, type 9063, size 1, index -1, binding -1, stages 1
11 sampler_2D: offset -1, type 8b5e, size 1, index -1, binding -1, stages 1
12 sampler_2DMSArray: offset -1, type 910b, size 1, index -1, binding -1, stages 1
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