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Searched refs:ARM (Results 1 – 25 of 2011) sorted by relevance

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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMExpandPseudoInsts.cpp153 { ARM::VLD1LNq16Pseudo, ARM::VLD1LNd16, true, false, false, EvenDblSpc, 1, 4 ,true},
154 { ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD, true, true, true, EvenDblSpc, 1, 4 ,true},
155 { ARM::VLD1LNq32Pseudo, ARM::VLD1LNd32, true, false, false, EvenDblSpc, 1, 2 ,true},
156 { ARM::VLD1LNq32Pseudo_UPD, ARM::VLD1LNd32_UPD, true, true, true, EvenDblSpc, 1, 2 ,true},
157 { ARM::VLD1LNq8Pseudo, ARM::VLD1LNd8, true, false, false, EvenDblSpc, 1, 8 ,true},
158 { ARM::VLD1LNq8Pseudo_UPD, ARM::VLD1LNd8_UPD, true, true, true, EvenDblSpc, 1, 8 ,true},
160 { ARM::VLD1d16QPseudo, ARM::VLD1d16Q, true, false, false, SingleSpc, 4, 4 ,false},
161 { ARM::VLD1d16TPseudo, ARM::VLD1d16T, true, false, false, SingleSpc, 3, 4 ,false},
162 { ARM::VLD1d32QPseudo, ARM::VLD1d32Q, true, false, false, SingleSpc, 4, 2 ,false},
163 { ARM::VLD1d32TPseudo, ARM::VLD1d32T, true, false, false, SingleSpc, 3, 2 ,false},
[all …]
DARMFeatures.h28 case ARM::tADC: in isV8EligibleForIT()
29 case ARM::tADDi3: in isV8EligibleForIT()
30 case ARM::tADDi8: in isV8EligibleForIT()
31 case ARM::tADDrr: in isV8EligibleForIT()
32 case ARM::tAND: in isV8EligibleForIT()
33 case ARM::tASRri: in isV8EligibleForIT()
34 case ARM::tASRrr: in isV8EligibleForIT()
35 case ARM::tBIC: in isV8EligibleForIT()
36 case ARM::tEOR: in isV8EligibleForIT()
37 case ARM::tLSLri: in isV8EligibleForIT()
[all …]
DARMBaseInstrInfo.cpp89 { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false },
90 { ARM::VMLSS, ARM::VMULS, ARM::VSUBS, false, false },
91 { ARM::VMLAD, ARM::VMULD, ARM::VADDD, false, false },
92 { ARM::VMLSD, ARM::VMULD, ARM::VSUBD, false, false },
93 { ARM::VNMLAS, ARM::VNMULS, ARM::VSUBS, true, false },
94 { ARM::VNMLSS, ARM::VMULS, ARM::VSUBS, true, false },
95 { ARM::VNMLAD, ARM::VNMULD, ARM::VSUBD, true, false },
96 { ARM::VNMLSD, ARM::VMULD, ARM::VSUBD, true, false },
99 { ARM::VMLAfd, ARM::VMULfd, ARM::VADDfd, false, false },
100 { ARM::VMLSfd, ARM::VMULfd, ARM::VSUBfd, false, false },
[all …]
DARMRegisterBankInfo.cpp30 namespace ARM { namespace
144 const RegisterBank &RBGPR = getRegBank(ARM::GPRRegBankID); in ARMRegisterBankInfo()
146 assert(&ARM::GPRRegBank == &RBGPR && "The order in RegBanks is messed up"); in ARMRegisterBankInfo()
149 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRRegClassID)) && in ARMRegisterBankInfo()
151 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRwithAPSRRegClassID)) && in ARMRegisterBankInfo()
153 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRnopcRegClassID)) && in ARMRegisterBankInfo()
155 assert(RBGPR.covers(*TRI.getRegClass(ARM::rGPRRegClassID)) && in ARMRegisterBankInfo()
157 assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPRRegClassID)) && in ARMRegisterBankInfo()
159 assert(RBGPR.covers(*TRI.getRegClass(ARM::tcGPRRegClassID)) && in ARMRegisterBankInfo()
161 assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPR_and_tcGPRRegClassID)) && in ARMRegisterBankInfo()
[all …]
DThumb2SizeReduction.cpp83 { ARM::t2ADCrr, 0, ARM::tADC, 0, 0, 0, 1, 0,0, 0,0,0 },
84 { ARM::t2ADDri, ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 0,0, 0,1,0 },
85 { ARM::t2ADDrr, ARM::tADDrr, ARM::tADDhirr, 0, 0, 1, 0, 0,1, 0,0,0 },
86 { ARM::t2ADDSri,ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 2,2, 0,1,0 },
87 { ARM::t2ADDSrr,ARM::tADDrr, 0, 0, 0, 1, 0, 2,0, 0,1,0 },
88 { ARM::t2ANDrr, 0, ARM::tAND, 0, 0, 0, 1, 0,0, 1,0,0 },
89 { ARM::t2ASRri, ARM::tASRri, 0, 5, 0, 1, 0, 0,0, 1,0,1 },
90 { ARM::t2ASRrr, 0, ARM::tASRrr, 0, 0, 0, 1, 0,0, 1,0,1 },
91 { ARM::t2BICrr, 0, ARM::tBIC, 0, 0, 0, 1, 0,0, 1,0,0 },
94 { ARM::t2CMNzrr, ARM::tCMNz, 0, 0, 0, 1, 0, 2,0, 0,0,0 },
[all …]
/external/llvm/lib/Target/ARM/
DARMExpandPseudoInsts.cpp150 { ARM::VLD1LNq16Pseudo, ARM::VLD1LNd16, true, false, false, EvenDblSpc, 1, 4 ,true},
151 { ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD, true, true, true, EvenDblSpc, 1, 4 ,true},
152 { ARM::VLD1LNq32Pseudo, ARM::VLD1LNd32, true, false, false, EvenDblSpc, 1, 2 ,true},
153 { ARM::VLD1LNq32Pseudo_UPD, ARM::VLD1LNd32_UPD, true, true, true, EvenDblSpc, 1, 2 ,true},
154 { ARM::VLD1LNq8Pseudo, ARM::VLD1LNd8, true, false, false, EvenDblSpc, 1, 8 ,true},
155 { ARM::VLD1LNq8Pseudo_UPD, ARM::VLD1LNd8_UPD, true, true, true, EvenDblSpc, 1, 8 ,true},
157 { ARM::VLD1d64QPseudo, ARM::VLD1d64Q, true, false, false, SingleSpc, 4, 1 ,false},
158 { ARM::VLD1d64QPseudoWB_fixed, ARM::VLD1d64Qwb_fixed, true, true, false, SingleSpc, 4, 1 ,fals…
159 { ARM::VLD1d64TPseudo, ARM::VLD1d64T, true, false, false, SingleSpc, 3, 1 ,false},
160 { ARM::VLD1d64TPseudoWB_fixed, ARM::VLD1d64Twb_fixed, true, true, false, SingleSpc, 3, 1 ,fals…
[all …]
DARMFeatures.h29 case ARM::tADC: in isV8EligibleForIT()
30 case ARM::tADDi3: in isV8EligibleForIT()
31 case ARM::tADDi8: in isV8EligibleForIT()
32 case ARM::tADDrr: in isV8EligibleForIT()
33 case ARM::tAND: in isV8EligibleForIT()
34 case ARM::tASRri: in isV8EligibleForIT()
35 case ARM::tASRrr: in isV8EligibleForIT()
36 case ARM::tBIC: in isV8EligibleForIT()
37 case ARM::tEOR: in isV8EligibleForIT()
38 case ARM::tLSLri: in isV8EligibleForIT()
[all …]
DARMBaseInstrInfo.cpp66 { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false },
67 { ARM::VMLSS, ARM::VMULS, ARM::VSUBS, false, false },
68 { ARM::VMLAD, ARM::VMULD, ARM::VADDD, false, false },
69 { ARM::VMLSD, ARM::VMULD, ARM::VSUBD, false, false },
70 { ARM::VNMLAS, ARM::VNMULS, ARM::VSUBS, true, false },
71 { ARM::VNMLSS, ARM::VMULS, ARM::VSUBS, true, false },
72 { ARM::VNMLAD, ARM::VNMULD, ARM::VSUBD, true, false },
73 { ARM::VNMLSD, ARM::VMULD, ARM::VSUBD, true, false },
76 { ARM::VMLAfd, ARM::VMULfd, ARM::VADDfd, false, false },
77 { ARM::VMLSfd, ARM::VMULfd, ARM::VSUBfd, false, false },
[all …]
DThumb2SizeReduction.cpp64 { ARM::t2ADCrr, 0, ARM::tADC, 0, 0, 0, 1, 0,0, 0,0,0 },
65 { ARM::t2ADDri, ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 0,0, 0,1,0 },
66 { ARM::t2ADDrr, ARM::tADDrr, ARM::tADDhirr, 0, 0, 1, 0, 0,1, 0,0,0 },
67 { ARM::t2ADDSri,ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 2,2, 0,1,0 },
68 { ARM::t2ADDSrr,ARM::tADDrr, 0, 0, 0, 1, 0, 2,0, 0,1,0 },
69 { ARM::t2ANDrr, 0, ARM::tAND, 0, 0, 0, 1, 0,0, 1,0,0 },
70 { ARM::t2ASRri, ARM::tASRri, 0, 5, 0, 1, 0, 0,0, 1,0,1 },
71 { ARM::t2ASRrr, 0, ARM::tASRrr, 0, 0, 0, 1, 0,0, 1,0,1 },
72 { ARM::t2BICrr, 0, ARM::tBIC, 0, 0, 0, 1, 0,0, 1,0,0 },
75 { ARM::t2CMNzrr, ARM::tCMNz, 0, 0, 0, 1, 0, 2,0, 0,0,0 },
[all …]
DThumb2InstrInfo.cpp37 NopInst.setOpcode(ARM::tHINT); in getNoopForMachoTarget()
79 if (MBBI->getOpcode() == ARM::t2IT) { in ReplaceTailWithBranchTo()
117 if (!ARM::GPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
120 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg) in copyPhysReg()
138 if (RC == &ARM::GPRRegClass || RC == &ARM::tGPRRegClass || in storeRegToStackSlot()
139 RC == &ARM::tcGPRRegClass || RC == &ARM::rGPRRegClass || in storeRegToStackSlot()
140 RC == &ARM::GPRnopcRegClass) { in storeRegToStackSlot()
141 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2STRi12)) in storeRegToStackSlot()
147 if (ARM::GPRPairRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
153 MRI->constrainRegClass(SrcReg, &ARM::GPRPair_with_gsub_1_in_rGPRRegClass); in storeRegToStackSlot()
[all …]
/external/llvm-project/llvm/lib/Target/ARM/
DARMExpandPseudoInsts.cpp185 { ARM::VLD1LNq16Pseudo, ARM::VLD1LNd16, true, false, false, EvenDblSpc, 1, 4 ,true},
186 { ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD, true, true, true, EvenDblSpc, 1, 4 ,true},
187 { ARM::VLD1LNq32Pseudo, ARM::VLD1LNd32, true, false, false, EvenDblSpc, 1, 2 ,true},
188 { ARM::VLD1LNq32Pseudo_UPD, ARM::VLD1LNd32_UPD, true, true, true, EvenDblSpc, 1, 2 ,true},
189 { ARM::VLD1LNq8Pseudo, ARM::VLD1LNd8, true, false, false, EvenDblSpc, 1, 8 ,true},
190 { ARM::VLD1LNq8Pseudo_UPD, ARM::VLD1LNd8_UPD, true, true, true, EvenDblSpc, 1, 8 ,true},
192 { ARM::VLD1d16QPseudo, ARM::VLD1d16Q, true, false, false, SingleSpc, 4, 4 ,false},
193 { ARM::VLD1d16TPseudo, ARM::VLD1d16T, true, false, false, SingleSpc, 3, 4 ,false},
194 { ARM::VLD1d32QPseudo, ARM::VLD1d32Q, true, false, false, SingleSpc, 4, 2 ,false},
195 { ARM::VLD1d32TPseudo, ARM::VLD1d32T, true, false, false, SingleSpc, 3, 2 ,false},
[all …]
DARMFeatures.h28 case ARM::tADC: in isV8EligibleForIT()
29 case ARM::tADDi3: in isV8EligibleForIT()
30 case ARM::tADDi8: in isV8EligibleForIT()
31 case ARM::tADDrr: in isV8EligibleForIT()
32 case ARM::tAND: in isV8EligibleForIT()
33 case ARM::tASRri: in isV8EligibleForIT()
34 case ARM::tASRrr: in isV8EligibleForIT()
35 case ARM::tBIC: in isV8EligibleForIT()
36 case ARM::tEOR: in isV8EligibleForIT()
37 case ARM::tLSLri: in isV8EligibleForIT()
[all …]
DARMBaseInstrInfo.cpp93 { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false },
94 { ARM::VMLSS, ARM::VMULS, ARM::VSUBS, false, false },
95 { ARM::VMLAD, ARM::VMULD, ARM::VADDD, false, false },
96 { ARM::VMLSD, ARM::VMULD, ARM::VSUBD, false, false },
97 { ARM::VNMLAS, ARM::VNMULS, ARM::VSUBS, true, false },
98 { ARM::VNMLSS, ARM::VMULS, ARM::VSUBS, true, false },
99 { ARM::VNMLAD, ARM::VNMULD, ARM::VSUBD, true, false },
100 { ARM::VNMLSD, ARM::VMULD, ARM::VSUBD, true, false },
103 { ARM::VMLAfd, ARM::VMULfd, ARM::VADDfd, false, false },
104 { ARM::VMLSfd, ARM::VMULfd, ARM::VSUBfd, false, false },
[all …]
DARMRegisterBankInfo.cpp30 namespace ARM { namespace
142 const RegisterBank &RBGPR = getRegBank(ARM::GPRRegBankID); in ARMRegisterBankInfo()
144 assert(&ARM::GPRRegBank == &RBGPR && "The order in RegBanks is messed up"); in ARMRegisterBankInfo()
147 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRRegClassID)) && in ARMRegisterBankInfo()
149 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRwithAPSRRegClassID)) && in ARMRegisterBankInfo()
151 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRnopcRegClassID)) && in ARMRegisterBankInfo()
153 assert(RBGPR.covers(*TRI.getRegClass(ARM::rGPRRegClassID)) && in ARMRegisterBankInfo()
155 assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPRRegClassID)) && in ARMRegisterBankInfo()
157 assert(RBGPR.covers(*TRI.getRegClass(ARM::tcGPRRegClassID)) && in ARMRegisterBankInfo()
159 assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPR_and_tcGPRRegClassID)) && in ARMRegisterBankInfo()
[all …]
/external/llvm-project/llvm/unittests/Support/
DTargetParserTest.cpp37 ARM::ArchKind AK = ARM::parseCPUArch(CPUName); in testARMCPU()
38 bool pass = ARM::getArchName(AK).equals(ExpectedArch); in testARMCPU()
39 unsigned FPUKind = ARM::getDefaultFPU(CPUName, AK); in testARMCPU()
40 pass &= ARM::getFPUName(FPUKind).equals(ExpectedFPU); in testARMCPU()
42 uint64_t ExtKind = ARM::getDefaultExtensions(CPUName, AK); in testARMCPU()
43 if (ExtKind > 1 && (ExtKind & ARM::AEK_NONE)) in testARMCPU()
44 pass &= ((ExtKind ^ ARM::AEK_NONE) == ExpectedFlags); in testARMCPU()
47 pass &= ARM::getCPUAttr(AK).equals(CPUAttr); in testARMCPU()
54 ARM::AEK_NONE, "")); in TEST()
56 ARM::AEK_NONE, "")); in TEST()
[all …]
/external/llvm-project/llvm/include/llvm/Support/
DARMTargetParser.def1 //===- ARMTargetParser.def - ARM target parsing defines ---------*- C++ -*-===//
9 // This file provides defines to build up the ARM target parser's logic.
49 ARMBuildAttrs::CPUArch::Pre_v4, FK_NONE, ARM::AEK_NONE)
51 FK_NONE, ARM::AEK_NONE)
53 FK_NONE, ARM::AEK_NONE)
55 FK_NONE, ARM::AEK_NONE)
57 FK_NONE, ARM::AEK_NONE)
59 FK_NONE, ARM::AEK_NONE)
61 FK_NONE, ARM::AEK_NONE)
63 FK_NONE, ARM::AEK_NONE)
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Support/
DARMTargetParser.def1 //===- ARMTargetParser.def - ARM target parsing defines ---------*- C++ -*-===//
9 // This file provides defines to build up the ARM target parser's logic.
49 ARMBuildAttrs::CPUArch::Pre_v4, FK_NONE, ARM::AEK_NONE)
51 FK_NONE, ARM::AEK_NONE)
53 FK_NONE, ARM::AEK_NONE)
55 FK_NONE, ARM::AEK_NONE)
57 FK_NONE, ARM::AEK_NONE)
59 FK_NONE, ARM::AEK_NONE)
61 FK_NONE, ARM::AEK_NONE)
63 FK_NONE, ARM::AEK_NONE)
[all …]
/external/llvm/test/CodeGen/ARM/
Dsegmented-stacks.ll1 … < %s -mtriple=arm-linux-androideabi -verify-machineinstrs | FileCheck %s -check-prefix=ARM-android
2 … %s -mtriple=arm-linux-unknown-gnueabi -verify-machineinstrs | FileCheck %s -check-prefix=ARM-linux
17 ; ARM-linux: test_basic:
19 ; ARM-linux: push {r4, r5}
20 ; ARM-linux-NEXT: mrc p15, #0, r4, c13, c0, #3
21 ; ARM-linux-NEXT: mov r5, sp
22 ; ARM-linux-NEXT: ldr r4, [r4, #4]
23 ; ARM-linux-NEXT: cmp r4, r5
24 ; ARM-linux-NEXT: blo .LBB0_2
26 ; ARM-linux: mov r4, #48
[all …]
/external/llvm-project/llvm/test/CodeGen/ARM/
Dsegmented-stacks.ll1 …le=arm-linux-androideabi -mattr=+v4t -verify-machineinstrs | FileCheck %s -check-prefix=ARM-android
2 …arm-linux-unknown-gnueabi -mattr=+v4t -verify-machineinstrs | FileCheck %s -check-prefix=ARM-linux
17 ; ARM-linux: test_basic:
19 ; ARM-linux: push {r4, r5}
20 ; ARM-linux-NEXT: mrc p15, #0, r4, c13, c0, #3
21 ; ARM-linux-NEXT: mov r5, sp
22 ; ARM-linux-NEXT: ldr r4, [r4, #4]
23 ; ARM-linux-NEXT: cmp r4, r5
24 ; ARM-linux-NEXT: blo .LBB0_2
26 ; ARM-linux: mov r4, #48
[all …]
Ddebug-frame-large-stack.ll1 …sm -o - < %s -mtriple arm-arm-netbsd-eabi -frame-pointer=all| FileCheck %s --check-prefix=CHECK-ARM
2 …filetype=asm -o - < %s -mtriple arm-arm-netbsd-eabi | FileCheck %s --check-prefix=CHECK-ARM-FP-ELIM
9 ; CHECK-ARM-LABEL: test1:
10 ; CHECK-ARM: .cfi_startproc
11 ; CHECK-ARM: sub sp, sp, #256
12 ; CHECK-ARM: .cfi_endproc
14 ; CHECK-ARM-FP-ELIM-LABEL: test1:
15 ; CHECK-ARM-FP-ELIM: .cfi_startproc
16 ; CHECK-ARM-FP-ELIM: sub sp, sp, #256
17 ; CHECK-ARM-FP-ELIM: .cfi_endproc
[all …]
/external/llvm/unittests/Support/
DTargetParserTest.cpp47 {NAME, ARM::ARCH_FPU, ARCH_BASE_EXT, AArch64::ArchKind::ID, ARCH_ATTR},
51 ArchNames<ARM::ArchKind> kARMARCHNames[] = {
54 {NAME, ARM::ARCH_FPU, ARCH_BASE_EXT, ARM::ID, ARCH_ATTR},
67 {NAME, AArch64::ArchKind::ID, ARM::DEFAULT_FPU, DEFAULT_EXT},
71 CpuNames<ARM::ArchKind> kARMCPUNames[] = {
73 {NAME, ARM::ID, ARM::DEFAULT_FPU, DEFAULT_EXT},
97 for (ARM::ArchKind AK = static_cast<ARM::ArchKind>(0); in TEST()
98 AK <= ARM::ArchKind::AK_LAST; in TEST()
99 AK = static_cast<ARM::ArchKind>(static_cast<unsigned>(AK) + 1)) in TEST()
100 EXPECT_TRUE(AK == ARM::AK_LAST ? ARM::getArchName(AK).empty() in TEST()
[all …]
/external/llvm/include/llvm/Support/
DARMTargetParser.def1 //===- ARMTargetParser.def - ARM target parsing defines ---------*- C++ -*-===//
10 // This file provides defines to build up the ARM target parser's logic.
48 ARMBuildAttrs::CPUArch::Pre_v4, FK_NONE, ARM::AEK_NONE)
50 FK_NONE, ARM::AEK_NONE)
52 FK_NONE, ARM::AEK_NONE)
54 FK_NONE, ARM::AEK_NONE)
56 FK_NONE, ARM::AEK_NONE)
58 FK_NONE, ARM::AEK_NONE)
60 FK_NONE, ARM::AEK_NONE)
62 FK_NONE, ARM::AEK_NONE)
[all …]
/external/swiftshader/third_party/llvm-subzero/include/llvm/Support/
DARMTargetParser.def1 //===- ARMTargetParser.def - ARM target parsing defines ---------*- C++ -*-===//
10 // This file provides defines to build up the ARM target parser's logic.
48 ARMBuildAttrs::CPUArch::Pre_v4, FK_NONE, ARM::AEK_NONE)
50 FK_NONE, ARM::AEK_NONE)
52 FK_NONE, ARM::AEK_NONE)
54 FK_NONE, ARM::AEK_NONE)
56 FK_NONE, ARM::AEK_NONE)
58 FK_NONE, ARM::AEK_NONE)
60 FK_NONE, ARM::AEK_NONE)
62 FK_NONE, ARM::AEK_NONE)
[all …]
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/
DARMGenRegisterInfo.inc18 namespace ARM {
317 } // end namespace ARM
321 namespace ARM {
447 } // end namespace ARM
452 namespace ARM {
458 } // end namespace ARM
463 namespace ARM {
524 } // end namespace ARM
1479 { ARM::APSR },
1480 { ARM::APSR_NZCV },
[all …]
DARMGenRegisterBank.inc12 namespace ARM {
18 } // end namespace ARM
35 namespace ARM {
38 (1u << (ARM::HPRRegClassID - 0)) |
39 (1u << (ARM::SPRRegClassID - 0)) |
40 (1u << (ARM::SPR_8RegClassID - 0)) |
41 (1u << (ARM::FPWithVPRRegClassID - 0)) |
42 (1u << (ARM::FPWithVPR_with_ssub_0RegClassID - 0)) |
43 (1u << (ARM::FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8RegClassID - 0)) |
46 (1u << (ARM::DPRRegClassID - 32)) |
[all …]

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