| /external/vixl/test/aarch32/config/ |
| D | cond-dt-drt-drd-drn-drm-float.json | 29 "Vabd", // VABD{<c>}{<q>}.F32 {<Dd>}, <Dn>, <Dm> ; T1
30 // VABD{<c>}{<q>}.F32 {<Dd>}, <Dn>, <Dm> ; A1
31 "Vadd", // VADD{<c>}{<q>}.F32 {<Dd>}, <Dn>, <Dm> ; A1
32 // VADD{<c>}{<q>}.F64 {<Dd>}, <Dn>, <Dm> ; A2
33 // VADD{<c>}{<q>}.F32 {<Dd>}, <Dn>, <Dm> ; T1
34 // VADD{<c>}{<q>}.F64 {<Dd>}, <Dn>, <Dm> ; T2
35 "Vceq", // VCEQ{<c>}{<q>}.<dt> {<Dd>}, <Dn>, <Dm> ; A2
36 // VCEQ{<c>}{<q>}.<dt> {<Dd>}, <Dn>, <Dm> ; T2
37 "Vcge", // VCGE{<c>}{<q>}.F32 {<Dd>}, <Dn>, <Dm> ; A2
38 // VCGE{<c>}{<q>}.F32 {<Dd>}, <Dn>, <Dm> ; T2
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| /external/libopus/win32/ |
| D | .gitignore | 2 [Dd]ebug/
3 [Dd]ebugDLL/
4 [Dd]ebugDLL_fixed/
5 [Dd]ebugPublic/
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrVFP.td | 101 def VLDRD : ADI5<0b1101, 0b01, (outs DPR:$Dd), (ins addrmode5:$addr),
102 IIC_fpLoad64, "vldr", "\t$Dd, $addr",
103 [(set DPR:$Dd, (f64 (alignedload32 addrmode5:$addr)))]>;
120 def VSTRD : ADI5<0b1101, 0b00, (outs), (ins DPR:$Dd, addrmode5:$addr),
121 IIC_fpStore64, "vstr", "\t$Dd, $addr",
122 [(alignedstore32 (f64 DPR:$Dd), addrmode5:$addr)]>;
335 let TwoOperandAliasConstraint = "$Dn = $Dd" in
337 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
338 IIC_fpALU64, "vadd", ".f64\t$Dd, $Dn, $Dm",
339 [(set DPR:$Dd, (fadd DPR:$Dn, (f64 DPR:$Dm)))]>;
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|
| D | ARMInstrNEON.td | 6215 def : NEONInstAlias<"vcvt${p}.s32.f32 $Dd, $Dm, #0",
6216 (VCVTf2sd DPR:$Dd, DPR:$Dm, pred:$p)>;
6217 def : NEONInstAlias<"vcvt${p}.u32.f32 $Dd, $Dm, #0",
6218 (VCVTf2ud DPR:$Dd, DPR:$Dm, pred:$p)>;
6219 def : NEONInstAlias<"vcvt${p}.f32.s32 $Dd, $Dm, #0",
6220 (VCVTs2fd DPR:$Dd, DPR:$Dm, pred:$p)>;
6221 def : NEONInstAlias<"vcvt${p}.f32.u32 $Dd, $Dm, #0",
6222 (VCVTu2fd DPR:$Dd, DPR:$Dm, pred:$p)>;
6233 def : NEONInstAlias<"vcvt${p}.s16.f16 $Dd, $Dm, #0",
6234 (VCVTh2sd DPR:$Dd, DPR:$Dm, pred:$p)>;
[all …]
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| D | ARMInstrFormats.td | 1459 bits<5> Dd;
1464 let Inst{22} = Dd{4};
1466 let Inst{15-12} = Dd{3-0};
1609 bits<5> Dd;
1615 let Inst{15-12} = Dd{3-0};
1616 let Inst{22} = Dd{4};
1635 bits<5> Dd;
1643 let Inst{15-12} = Dd{3-0};
1644 let Inst{22} = Dd{4};
1661 bits<5> Dd;
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|
| /external/swiftshader/third_party/subzero/src/ |
| D | IceAssemblerARM32.cpp | 1203 void AssemblerARM32::emitSIMDBase(IValueT Opcode, IValueT Dd, IValueT Dn, in emitSIMDBase() argument
1207 (getYInRegYXXXX(Dd) << 22) | (getXXXXInRegYXXXX(Dn) << 16) | in emitSIMDBase()
1208 (getXXXXInRegYXXXX(Dd) << 12) | (IsFloatTy ? B10 : 0) | in emitSIMDBase()
1214 void AssemblerARM32::emitSIMD(IValueT Opcode, Type ElmtTy, IValueT Dd, in emitSIMD() argument
1219 emitSIMDBase(Opcode | (ElmtSize << ElmtShift), Dd, Dn, Dm, UseQRegs, in emitSIMD()
1272 IValueT Dd, IValueT Dn, IValueT Dm) { in emitVFPddd() argument
1273 assert(Dd < RegARM32::getNumDRegs()); in emitVFPddd()
1280 (getYInRegYXXXX(Dd) << 22) | (getXXXXInRegYXXXX(Dn) << 16) | in emitVFPddd()
1281 (getXXXXInRegYXXXX(Dd) << 12) | (getYInRegYXXXX(Dn) << 7) | in emitVFPddd()
1289 IValueT Dd = encodeDRegister(OpDd, "Dd", InstName); in emitVFPddd() local
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| D | IceAssemblerARM32.h | 786 void emitVFPds(CondARM32::Cond Cond, IValueT Opcode, IValueT Dd, IValueT Sm);
791 void emitVMem1Op(IValueT Opcode, IValueT Dd, IValueT Rn, IValueT Rm,
797 void emitVMem1Op(IValueT Opcode, IValueT Dd, IValueT Rn, IValueT Rm,
838 void emitSIMDBase(IValueT Opcode, IValueT Dd, IValueT Dn, IValueT Dm,
843 void emitSIMD(IValueT Opcode, Type ElmtTy, IValueT Dd, IValueT Dn, IValueT Dm,
896 void emitVFPddd(CondARM32::Cond Cond, IValueT Opcode, IValueT Dd, IValueT Dn,
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMInstrVFP.td | 144 def VLDRD : ADI5<0b1101, 0b01, (outs DPR:$Dd), (ins addrmode5:$addr),
145 IIC_fpLoad64, "vldr", "\t$Dd, $addr",
146 [(set DPR:$Dd, (f64 (alignedload32 addrmode5:$addr)))]>,
166 def VSTRD : ADI5<0b1101, 0b00, (outs), (ins DPR:$Dd, addrmode5:$addr),
167 IIC_fpStore64, "vstr", "\t$Dd, $addr",
168 [(alignedstore32 (f64 DPR:$Dd), addrmode5:$addr)]>,
368 let TwoOperandAliasConstraint = "$Dn = $Dd" in
370 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
371 IIC_fpALU64, "vadd", ".f64\t$Dd, $Dn, $Dm",
372 [(set DPR:$Dd, (fadd DPR:$Dn, (f64 DPR:$Dm)))]>,
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| D | ARMInstrNEON.td | 6747 def : NEONInstAlias<"vcvt${p}.s32.f32 $Dd, $Dm, #0",
6748 (VCVTf2sd DPR:$Dd, DPR:$Dm, pred:$p)>;
6749 def : NEONInstAlias<"vcvt${p}.u32.f32 $Dd, $Dm, #0",
6750 (VCVTf2ud DPR:$Dd, DPR:$Dm, pred:$p)>;
6751 def : NEONInstAlias<"vcvt${p}.f32.s32 $Dd, $Dm, #0",
6752 (VCVTs2fd DPR:$Dd, DPR:$Dm, pred:$p)>;
6753 def : NEONInstAlias<"vcvt${p}.f32.u32 $Dd, $Dm, #0",
6754 (VCVTu2fd DPR:$Dd, DPR:$Dm, pred:$p)>;
6765 def : NEONInstAlias<"vcvt${p}.s16.f16 $Dd, $Dm, #0",
6766 (VCVTh2sd DPR:$Dd, DPR:$Dm, pred:$p)>;
[all …]
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| D | ARMInstrFormats.td | 1589 bits<5> Dd;
1594 let Inst{22} = Dd{4};
1596 let Inst{15-12} = Dd{3-0};
1741 bits<5> Dd;
1747 let Inst{15-12} = Dd{3-0};
1748 let Inst{22} = Dd{4};
1767 bits<5> Dd;
1775 let Inst{15-12} = Dd{3-0};
1776 let Inst{22} = Dd{4};
1793 bits<5> Dd;
[all …]
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| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMInstrVFP.td | 154 def VLDRD : ADI5<0b1101, 0b01, (outs DPR:$Dd), (ins addrmode5:$addr),
155 IIC_fpLoad64, "vldr", "\t$Dd, $addr",
156 [(set DPR:$Dd, (f64 (alignedload32 addrmode5:$addr)))]>,
189 def VSTRD : ADI5<0b1101, 0b00, (outs), (ins DPR:$Dd, addrmode5:$addr),
190 IIC_fpStore64, "vstr", "\t$Dd, $addr",
191 [(alignedstore32 (f64 DPR:$Dd), addrmode5:$addr)]>,
403 let TwoOperandAliasConstraint = "$Dn = $Dd" in
405 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
406 IIC_fpALU64, "vadd", ".f64\t$Dd, $Dn, $Dm",
407 [(set DPR:$Dd, (fadd DPR:$Dn, (f64 DPR:$Dm)))]>,
[all …]
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| D | ARMInstrNEON.td | 6798 def : NEONInstAlias<"vcvt${p}.s32.f32 $Dd, $Dm, #0",
6799 (VCVTf2sd DPR:$Dd, DPR:$Dm, pred:$p)>;
6800 def : NEONInstAlias<"vcvt${p}.u32.f32 $Dd, $Dm, #0",
6801 (VCVTf2ud DPR:$Dd, DPR:$Dm, pred:$p)>;
6802 def : NEONInstAlias<"vcvt${p}.f32.s32 $Dd, $Dm, #0",
6803 (VCVTs2fd DPR:$Dd, DPR:$Dm, pred:$p)>;
6804 def : NEONInstAlias<"vcvt${p}.f32.u32 $Dd, $Dm, #0",
6805 (VCVTu2fd DPR:$Dd, DPR:$Dm, pred:$p)>;
6816 def : NEONInstAlias<"vcvt${p}.s16.f16 $Dd, $Dm, #0",
6817 (VCVTh2sd DPR:$Dd, DPR:$Dm, pred:$p)>;
[all …]
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| D | ARMInstrFormats.td | 1598 bits<5> Dd;
1603 let Inst{22} = Dd{4};
1605 let Inst{15-12} = Dd{3-0};
1750 bits<5> Dd;
1756 let Inst{15-12} = Dd{3-0};
1757 let Inst{22} = Dd{4};
1776 bits<5> Dd;
1784 let Inst{15-12} = Dd{3-0};
1785 let Inst{22} = Dd{4};
1802 bits<5> Dd;
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| /external/ImageMagick/PerlMagick/t/reference/write/ |
| D | output_p7.miff | 10 …$$$$$Dd����������ddd������qMI$$$$$$$$$M������qI$$$$$$$$$$$$$$$$$$$DDD$$$DDD$Dd��d�����dddh���qv�qq…
|
| /external/llvm-project/llvm/test/tools/llvm-config/ |
| D | booleans.test | 15 CHECK-BUILD-MODE: {{[Dd][Ee][Bb][Uu][Gg]|[Rr][Ee][Ll][Ee][Aa][Ss][Ee]|[Rr][Ee][Ll][Ww][Ii][Tt][Hh][…
|
| /external/icu/icu4c/source/test/fuzzer/ |
| D | collator_rulebased_fuzzer_seed_corpus.txt | 2 &D<dd<<<Dd<<<DD
|
| /external/icu/icu4c/source/data/coll/ |
| D | cy.txt | 9 "&D<dd<<<Dd<<<DD"
|
| /external/cldr/tools/java/org/unicode/cldr/util/data/transforms/ |
| D | en-IPA-spellout.txt | 8 [Dd] > di ;
|
| /external/ms-tpm-20-ref/ |
| D | .gitignore | 16 [Dd]ebug/
17 [Dd]ebugPublic/
41 [Dd]ebugPS/
|
| /external/llvm-project/llvm/test/DebugInfo/Generic/ |
| D | sroa-larger.ll | 20 ; } Dd;
30 ; F fn2() { return Dd; }
|
| /external/Reactive-Extensions/RxCpp/ |
| D | .gitignore | 14 [Dd]ebug/
|
| /external/Reactive-Extensions/RxCpp/Ix/CPP/ |
| D | .gitignore | 21 [Dd]ebug/
|
| /external/llvm-project/clang/include/clang/AST/ |
| D | CommentHTMLTags.td | 43 def Dd : Tag<"dd"> { let EndTagOptional = 1; }
|
| /external/clang/include/clang/AST/ |
| D | CommentHTMLTags.td | 43 def Dd : Tag<"dd"> { let EndTagOptional = 1; }
|
| /external/capstone/arch/ARM/ |
| D | ARMGenAsmWriter.inc | 8841 // (FCONSTD DPR:$Dd, vfp_f64imm:$val, pred:$p)
9486 // (VADDD DPR:$Dd, DPR:$Dn, DPR:$Dm, pred:$p)
9548 // (VCGEfd DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)
9587 // (VCGEsv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)
9600 // (VCGEsv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)
9639 // (VCGEsv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)
9665 // (VCGEuv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)
9678 // (VCGEuv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)
9717 // (VCGEuv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)
9730 // (VCGTfd DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)
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