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Searched refs:GENX (Results 1 – 19 of 19) sorted by relevance

/external/mesa3d/src/intel/vulkan/
DgenX_state.c51 unsigned size = GENX(SLICE_HASH_TABLE_length) * 4; in genX()
55 struct GENX(SLICE_HASH_TABLE) table0 = { in genX()
76 struct GENX(SLICE_HASH_TABLE) table1 = { in genX()
97 const struct GENX(SLICE_HASH_TABLE) *table = in genX()
99 GENX(SLICE_HASH_TABLE_pack)(NULL, device->slice_hash.map, table); in genX()
101 anv_batch_emit(batch, GENX(3DSTATE_SLICE_TABLE_STATE_POINTERS), ptr) { in genX()
106 anv_batch_emit(batch, GENX(3DSTATE_3D_MODE), mode) { in genX()
121 anv_batch_emit(&batch, GENX(PIPELINE_SELECT), ps) { in genX()
131 anv_pack_struct(&cache_mode_1, GENX(CACHE_MODE_1), in genX()
139 anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) { in genX()
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DgenX_gpu_memcpy.c87 dw = anv_batch_emitn(&cmd_buffer->batch, 5, GENX(3DSTATE_VERTEX_BUFFERS)); in genX()
88 GENX(VERTEX_BUFFER_STATE_pack)(&cmd_buffer->batch, dw + 1, in genX()
89 &(struct GENX(VERTEX_BUFFER_STATE)) { in genX()
102 dw = anv_batch_emitn(&cmd_buffer->batch, 3, GENX(3DSTATE_VERTEX_ELEMENTS)); in genX()
103 GENX(VERTEX_ELEMENT_STATE_pack)(&cmd_buffer->batch, dw + 1, in genX()
104 &(struct GENX(VERTEX_ELEMENT_STATE)) { in genX()
116 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_VF_INSTANCING), vfi) { in genX()
123 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_VF_SGVS), sgvs); in genX()
127 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_VS), vs); in genX()
128 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_HS), hs); in genX()
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Dgen8_cmd_buffer.c52 struct GENX(SF_CLIP_VIEWPORT) sfv = { in gen8_cmd_buffer_emit_viewport()
85 GENX(SF_CLIP_VIEWPORT_pack)(NULL, sf_clip_state.map + i * 64, &sfv); in gen8_cmd_buffer_emit_viewport()
89 GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP), clip) { in gen8_cmd_buffer_emit_viewport()
115 struct GENX(CC_VIEWPORT) cc_viewport = { in gen8_cmd_buffer_emit_depth_viewport()
120 GENX(CC_VIEWPORT_pack)(NULL, cc_state.map + i * 8, &cc_viewport); in gen8_cmd_buffer_emit_depth_viewport()
124 GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC), cc) { in gen8_cmd_buffer_emit_depth_viewport()
147 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) { in genX()
164 anv_pack_struct(&cache_mode, GENX(CACHE_MODE_0), in genX()
167 anv_batch_emit(&cmd_buffer->batch, GENX(MI_LOAD_REGISTER_IMM), lri) { in genX()
168 lri.RegisterOffset = GENX(CACHE_MODE_0_num); in genX()
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DgenX_query.c195 anv_batch_emit(&batch, GENX(MI_BATCH_BUFFER_END), bbe); in genX()
589 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) { in emit_ps_depth_count()
616 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) { in emit_query_pc_availability()
778 GENX(IA_VERTICES_COUNT_num),
779 GENX(IA_PRIMITIVES_COUNT_num),
780 GENX(VS_INVOCATION_COUNT_num),
781 GENX(GS_INVOCATION_COUNT_num),
782 GENX(GS_PRIMITIVES_COUNT_num),
783 GENX(CL_INVOCATION_COUNT_num),
784 GENX(CL_PRIMITIVES_COUNT_num),
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DgenX_pipeline.c115 GENX(3DSTATE_VERTEX_ELEMENTS)); in emit_vertex_input()
137 struct GENX(VERTEX_ELEMENT_STATE) element = { in emit_vertex_input()
144 GENX(VERTEX_ELEMENT_STATE_pack)(NULL, &p[1 + i * 2], &element); in emit_vertex_input()
165 struct GENX(VERTEX_ELEMENT_STATE) element = { in emit_vertex_input()
176 GENX(VERTEX_ELEMENT_STATE_pack)(NULL, &p[1 + slot * 2], &element); in emit_vertex_input()
183 anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_VF_INSTANCING), vfi) { in emit_vertex_input()
207 struct GENX(VERTEX_ELEMENT_STATE) element = { in emit_vertex_input()
221 GENX(VERTEX_ELEMENT_STATE_pack)(NULL, &p[1 + id_slot * 2], &element); in emit_vertex_input()
224 anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_VF_INSTANCING), vfi) { in emit_vertex_input()
231 anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_VF_SGVS), sgvs) { in emit_vertex_input()
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Dgen7_cmd_buffer.c215 uint32_t sf_dw[GENX(3DSTATE_SF_length)]; in genX()
216 struct GENX(3DSTATE_SF) sf = { in genX()
217 GENX(3DSTATE_SF_header), in genX()
226 GENX(3DSTATE_SF_pack)(NULL, sf_dw, &sf); in genX()
235 GENX(COLOR_CALC_STATE_length) * 4, in genX()
237 struct GENX(COLOR_CALC_STATE) cc = { in genX()
245 GENX(COLOR_CALC_STATE_pack)(NULL, cc_state.map, &cc); in genX()
247 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CC_STATE_POINTERS), ccp) { in genX()
253 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_LINE_STIPPLE), ls) { in genX()
270 uint32_t depth_stencil_dw[GENX(DEPTH_STENCIL_STATE_length)]; in genX()
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DgenX_cmd_buffer.c52 anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_IMM), lri) { in emit_lri()
77 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) { in genX()
107 anv_batch_emit(&cmd_buffer->batch, GENX(STATE_BASE_ADDRESS), sba) { in genX()
240 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) { in genX()
740 anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_DATA_IMM), sdi) { in set_image_compressed_bit()
755 anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_DATA_IMM), sdi) { in set_image_fast_clear_state()
848 anv_batch_emit(&cmd_buffer->batch, GENX(MI_PREDICATE), mip) { in anv_cmd_compute_resolve_predicate()
891 anv_batch_emit(&cmd_buffer->batch, GENX(MI_PREDICATE), mip) { in anv_cmd_simple_resolve_predicate()
1005 anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_DATA_IMM), sdi) { in init_fast_clear_color()
1012 anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_DATA_IMM), sdi) { in init_fast_clear_color()
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/external/mesa3d/src/intel/isl/
Disl_emit_depth_stencil.c65 struct GENX(3DSTATE_DEPTH_BUFFER) db = { in isl_genX()
66 GENX(3DSTATE_DEPTH_BUFFER_header), in isl_genX()
148 struct GENX(3DSTATE_STENCIL_BUFFER) sb = { in isl_genX()
149 GENX(3DSTATE_STENCIL_BUFFER_header), in isl_genX()
200 struct GENX(3DSTATE_HIER_DEPTH_BUFFER) hiz = { in isl_genX()
201 GENX(3DSTATE_HIER_DEPTH_BUFFER_header), in isl_genX()
203 struct GENX(3DSTATE_CLEAR_PARAMS) clear = { in isl_genX()
204 GENX(3DSTATE_CLEAR_PARAMS_header), in isl_genX()
297 GENX(3DSTATE_DEPTH_BUFFER_pack)(NULL, dw, &db); in isl_genX()
298 dw += GENX(3DSTATE_DEPTH_BUFFER_length); in isl_genX()
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Disl_surface_state.c251 struct GENX(RENDER_SURFACE_STATE) s = { 0 }; in isl_genX()
536 s.ShaderChannelSelectRed = (enum GENX(ShaderChannelSelect)) info->view->swizzle.r; in isl_genX()
537 s.ShaderChannelSelectGreen = (enum GENX(ShaderChannelSelect)) info->view->swizzle.g; in isl_genX()
538 s.ShaderChannelSelectBlue = (enum GENX(ShaderChannelSelect)) info->view->swizzle.b; in isl_genX()
539 s.ShaderChannelSelectAlpha = (enum GENX(ShaderChannelSelect)) info->view->swizzle.a; in isl_genX()
808 GENX(RENDER_SURFACE_STATE_pack)(NULL, state, &s); in isl_genX()
855 struct GENX(RENDER_SURFACE_STATE) s = { 0, }; in isl_genX()
921 s.ShaderChannelSelectRed = (enum GENX(ShaderChannelSelect)) info->swizzle.r; in isl_genX()
922 s.ShaderChannelSelectGreen = (enum GENX(ShaderChannelSelect)) info->swizzle.g; in isl_genX()
923 s.ShaderChannelSelectBlue = (enum GENX(ShaderChannelSelect)) info->swizzle.b; in isl_genX()
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/external/mesa3d/src/intel/blorp/
Dblorp_genX_exec.h234 blorp_emit(batch, GENX(PIPE_CONTROL), pc) { in emit_urb_config()
242 blorp_emit(batch, GENX(3DSTATE_URB_VS), urb) { in emit_urb_config()
350 blorp_fill_vertex_buffer_state(struct GENX(VERTEX_BUFFER_STATE) *vb, in blorp_fill_vertex_buffer_state()
383 struct GENX(VERTEX_BUFFER_STATE) vb[3]; in blorp_emit_vertex_buffers()
398 const unsigned num_dwords = 1 + num_vbs * GENX(VERTEX_BUFFER_STATE_length); in blorp_emit_vertex_buffers()
399 uint32_t *dw = blorp_emitn(batch, GENX(3DSTATE_VERTEX_BUFFERS), num_dwords); in blorp_emit_vertex_buffers()
404 GENX(VERTEX_BUFFER_STATE_pack)(batch, dw, &vb[i]); in blorp_emit_vertex_buffers()
405 dw += GENX(VERTEX_BUFFER_STATE_length); in blorp_emit_vertex_buffers()
418 struct GENX(VERTEX_ELEMENT_STATE) ve[num_elements]; in blorp_emit_vertex_elements()
469 ve[slot] = (struct GENX(VERTEX_ELEMENT_STATE)) { in blorp_emit_vertex_elements()
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/external/mesa3d/src/intel/genxml/
Dgen_macros.h65 # define GENX(X) GEN4_##X macro
68 # define GENX(X) GEN45_##X macro
71 # define GENX(X) GEN5_##X macro
74 # define GENX(X) GEN6_##X macro
77 # define GENX(X) GEN7_##X macro
80 # define GENX(X) GEN75_##X macro
83 # define GENX(X) GEN8_##X macro
86 # define GENX(X) GEN9_##X macro
89 # define GENX(X) GEN11_##X macro
92 # define GENX(X) GEN12_##X macro
/external/mesa3d/src/gallium/drivers/iris/
Diris_state.c476 iris_emit_cmd(batch, GENX(MI_LOAD_REGISTER_IMM), lri) { in _iris_emit_lri()
481 #define iris_emit_lri(b, r, v) _iris_emit_lri(b, GENX(r##_num), v)
486 iris_emit_cmd(batch, GENX(MI_LOAD_REGISTER_REG), lrr) { in _iris_emit_lrr()
530 iris_emit_cmd(batch, GENX(MI_LOAD_REGISTER_MEM), lrm) { in iris_load_register_mem32()
555 iris_emit_cmd(batch, GENX(MI_STORE_REGISTER_MEM), srm) { in iris_store_register_mem32()
578 iris_emit_cmd(batch, GENX(MI_STORE_DATA_IMM), sdi) { in iris_store_data_imm32()
595 _iris_pack_command(batch, GENX(MI_STORE_DATA_IMM), map, sdi) { in iris_store_data_imm64()
616 iris_emit_cmd(batch, GENX(MI_COPY_MEM_MEM), cp) { in iris_copy_mem_mem()
640 iris_emit_cmd(batch, GENX(3DSTATE_CC_STATE_POINTERS), t); in emit_pipeline_select()
668 iris_emit_cmd(batch, GENX(PIPELINE_SELECT), sel) { in emit_pipeline_select()
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Diris_query.c51 #define SO_PRIM_STORAGE_NEEDED(n) (GENX(SO_PRIM_STORAGE_NEEDED0_num) + (n) * 8)
52 #define SO_NUM_PRIMS_WRITTEN(n) (GENX(SO_NUM_PRIMS_WRITTEN0_num) + (n) * 8)
210 GENX(CL_INVOCATION_COUNT_num) : in write_value()
221 GENX(IA_VERTICES_COUNT_num), in write_value()
222 GENX(IA_PRIMITIVES_COUNT_num), in write_value()
223 GENX(VS_INVOCATION_COUNT_num), in write_value()
224 GENX(GS_INVOCATION_COUNT_num), in write_value()
225 GENX(GS_PRIMITIVES_COUNT_num), in write_value()
226 GENX(CL_INVOCATION_COUNT_num), in write_value()
227 GENX(CL_PRIMITIVES_COUNT_num), in write_value()
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/external/mesa3d/src/mesa/drivers/dri/i965/
DgenX_state_upload.c81 brw_batch_emit(brw, GENX(MI_LOAD_REGISTER_MEM), lrm) { in emit_lrm()
92 brw_batch_emit(brw, GENX(MI_LOAD_REGISTER_IMM), lri) { in emit_lri()
111 brw_batch_emit(brw, GENX(3DSTATE_POLY_STIPPLE_PATTERN), poly) { in genX()
150 brw_batch_emit(brw, GENX(3DSTATE_POLY_STIPPLE_OFFSET), poly) { in genX()
186 brw_batch_emit(brw, GENX(3DSTATE_LINE_STIPPLE), line) { in genX()
211 brw_batch_emit(brw, GENX(3DSTATE_DRAWING_RECTANGLE), rect) { in genX()
236 struct GENX(VERTEX_BUFFER_STATE) buf_state = { in genX()
277 GENX(VERTEX_BUFFER_STATE_pack)(brw, dw, &buf_state); in genX()
278 return dw + GENX(VERTEX_BUFFER_STATE_length); in genX()
492 brw_batch_emit(brw, GENX(3DSTATE_VF_SGVS), vfs) { in genX()
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Dgen4_blorp_exec.h55 blorp_emit_dynamic(batch, GENX(VS_STATE), vs, 64, &offset) { in blorp_emit_vs_state()
77 blorp_emit_dynamic(batch, GENX(SF_STATE), sf, 64, &offset) { in blorp_emit_sf_state()
113 blorp_emit_dynamic(batch, GENX(WM_STATE), wm, 64, &offset) { in blorp_emit_wm_state()
167 blorp_emit_dynamic(batch, GENX(COLOR_CALC_STATE), cc, 64, &offset) { in blorp_emit_color_calc_state()
183 blorp_emit(batch, GENX(3DSTATE_PIPELINED_POINTERS), pp) { in blorp_emit_pipeline()
194 blorp_emit(batch, GENX(CS_URB_STATE), curb); in blorp_emit_pipeline()
195 blorp_emit(batch, GENX(CONSTANT_BUFFER), curb); in blorp_emit_pipeline()
DgenX_pipe_control.c462 brw_batch_emit(brw, GENX(PIPE_CONTROL), pc) { in genX()
DgenX_blorp_exec.c359 blorp_emit(batch, GENX(3DSTATE_DRAWING_RECTANGLE), rect) { in genX()
/external/mesa3d/src/intel/common/
Dgen_mi_builder.h163 gen_mi_builder_pack(b, GENX(MI_MATH), dw, math) { in gen_mi_builder_flush_math()
164 math.DWordLength = 1 + b->num_math_dwords - GENX(MI_MATH_length_bias); in gen_mi_builder_flush_math()
393 gen_mi_builder_emit(b, GENX(MI_STORE_DATA_IMM), sdi) { in _gen_mi_copy_no_unref()
405 gen_mi_builder_emit(b, GENX(MI_COPY_MEM_MEM), cmm) { in _gen_mi_copy_no_unref()
423 gen_mi_builder_emit(b, GENX(MI_STORE_REGISTER_MEM), srm) { in _gen_mi_copy_no_unref()
441 gen_mi_builder_emit(b, GENX(MI_LOAD_REGISTER_IMM), lri) { in _gen_mi_copy_no_unref()
453 gen_mi_builder_emit(b, GENX(MI_LOAD_REGISTER_MEM), lrm) { in _gen_mi_copy_no_unref()
467 gen_mi_builder_emit(b, GENX(MI_LOAD_REGISTER_REG), lrr) { in _gen_mi_copy_no_unref()
594 gen_mi_builder_emit(b, GENX(MI_STORE_REGISTER_MEM), srm) { in gen_mi_store_if()
603 gen_mi_builder_emit(b, GENX(MI_STORE_REGISTER_MEM), srm) { in gen_mi_store_if()
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/external/mesa3d/src/intel/common/tests/
Dgen_mi_builder_test.cpp267 gen_mi_builder_emit(&b, GENX(MI_BATCH_BUFFER_END), bbe); in submit_batch()
271 gen_mi_builder_emit(&b, GENX(MI_NOOP), noop); in submit_batch()
696 emit_cmd(GENX(MI_PREDICATE), mip) { in TEST_F()
706 emit_cmd(GENX(MI_PREDICATE), mip) { in TEST_F()