Home
last modified time | relevance | path

Searched refs:MIRBuilder (Results 1 – 25 of 76) sorted by relevance

1234

/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/
DIRTranslator.h207 bool translateBitCast(const User &U, MachineIRBuilder &MIRBuilder);
210 bool translateLoad(const User &U, MachineIRBuilder &MIRBuilder);
213 bool translateStore(const User &U, MachineIRBuilder &MIRBuilder);
216 bool translateMemFunc(const CallInst &CI, MachineIRBuilder &MIRBuilder,
219 void getStackGuard(Register DstReg, MachineIRBuilder &MIRBuilder);
222 MachineIRBuilder &MIRBuilder);
233 MachineIRBuilder &MIRBuilder);
236 MachineIRBuilder &MIRBuilder);
238 bool translateInlineAsm(const CallInst &CI, MachineIRBuilder &MIRBuilder);
248 MachineIRBuilder &MIRBuilder);
[all …]
DCallLowering.h113 ValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, in ValueHandler()
115 : MIRBuilder(MIRBuilder), MRI(MRI), AssignFn(AssignFn) {} in ValueHandler()
163 MachineIRBuilder &MIRBuilder; member
195 MachineIRBuilder &MIRBuilder) const;
203 MachineIRBuilder &MIRBuilder) const;
209 bool handleAssignments(MachineIRBuilder &MIRBuilder,
214 MachineIRBuilder &MIRBuilder,
264 virtual bool lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val, in lowerReturn() argument
269 return lowerReturn(MIRBuilder, Val, VRegs); in lowerReturn()
276 virtual bool lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val, in lowerReturn() argument
[all …]
/external/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
DIRTranslator.h208 MachineIRBuilder &MIRBuilder);
212 bool translateBitCast(const User &U, MachineIRBuilder &MIRBuilder);
215 bool translateLoad(const User &U, MachineIRBuilder &MIRBuilder);
218 bool translateStore(const User &U, MachineIRBuilder &MIRBuilder);
221 bool translateMemFunc(const CallInst &CI, MachineIRBuilder &MIRBuilder,
224 void getStackGuard(Register DstReg, MachineIRBuilder &MIRBuilder);
227 MachineIRBuilder &MIRBuilder);
229 MachineIRBuilder &MIRBuilder);
240 MachineIRBuilder &MIRBuilder);
243 MachineIRBuilder &MIRBuilder);
[all …]
DCallLowering.h113 ValueHandler(bool IsIncoming, MachineIRBuilder &MIRBuilder, in ValueHandler()
115 : MIRBuilder(MIRBuilder), MRI(MRI), AssignFn(AssignFn), in ValueHandler()
178 MachineIRBuilder &MIRBuilder; member
188 IncomingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, in IncomingValueHandler()
190 : ValueHandler(true, MIRBuilder, MRI, AssignFn) {} in IncomingValueHandler()
194 OutgoingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, in OutgoingValueHandler()
196 : ValueHandler(false, MIRBuilder, MRI, AssignFn) {} in OutgoingValueHandler()
234 MachineIRBuilder &MIRBuilder) const;
242 MachineIRBuilder &MIRBuilder) const;
248 bool handleAssignments(MachineIRBuilder &MIRBuilder,
[all …]
/external/llvm-project/llvm/lib/CodeGen/GlobalISel/
DLegalizerHelper.cpp92 : MIRBuilder(Builder), Observer(Observer), MRI(MF.getRegInfo()), in LegalizerHelper()
95 MIRBuilder.setChangeObserver(Observer); in LegalizerHelper()
101 : MIRBuilder(B), Observer(Observer), MRI(MF.getRegInfo()), LI(LI), in LegalizerHelper()
103 MIRBuilder.setChangeObserver(Observer); in LegalizerHelper()
109 MIRBuilder.setInstrAndDebugLoc(MI); in legalizeInstrStep()
153 MIRBuilder.buildUnmerge(VRegs, Reg); in extractParts()
171 MIRBuilder.buildUnmerge(VRegs, Reg); in extractParts()
188 MIRBuilder.buildExtract(NewReg, Reg, MainSize * I); in extractParts()
195 MIRBuilder.buildExtract(NewReg, Reg, Offset); in extractParts()
210 MIRBuilder.buildMerge(DstReg, PartRegs); in insertParts()
[all …]
DIRTranslator.cpp289 MachineIRBuilder &MIRBuilder) { in translateBinaryOp() argument
303 MIRBuilder.buildInstr(Opcode, {Res}, {Op0, Op1}, Flags); in translateBinaryOp()
308 MachineIRBuilder &MIRBuilder) { in translateUnaryOp() argument
316 MIRBuilder.buildInstr(Opcode, {Res}, {Op0}, Flags); in translateUnaryOp()
320 bool IRTranslator::translateFNeg(const User &U, MachineIRBuilder &MIRBuilder) { in translateFNeg() argument
321 return translateUnaryOp(TargetOpcode::G_FNEG, U, MIRBuilder); in translateFNeg()
325 MachineIRBuilder &MIRBuilder) { in translateCompare() argument
334 MIRBuilder.buildICmp(Pred, Res, Op0, Op1); in translateCompare()
336 MIRBuilder.buildCopy( in translateCompare()
339 MIRBuilder.buildCopy( in translateCompare()
[all …]
DCallLowering.cpp78 bool CallLowering::lowerCall(MachineIRBuilder &MIRBuilder, const CallBase &CB, in lowerCall() argument
84 const DataLayout &DL = MIRBuilder.getDataLayout(); in lowerCall()
85 MachineFunction &MF = MIRBuilder.getMF(); in lowerCall()
129 return lowerCall(MIRBuilder, Info); in lowerCall()
169 MachineIRBuilder &MIRBuilder) const { in packRegs()
172 const DataLayout &DL = MIRBuilder.getMF().getDataLayout(); in packRegs()
173 MachineRegisterInfo *MRI = MIRBuilder.getMRI(); in packRegs()
183 MIRBuilder.buildUndef(Dst); in packRegs()
186 MIRBuilder.buildInsert(NewDst, Dst, SrcRegs[i], Offsets[i]); in packRegs()
195 MachineIRBuilder &MIRBuilder) const { in unpackRegs()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/
DLegalizerHelper.cpp69 : MIRBuilder(Builder), MRI(MF.getRegInfo()), in LegalizerHelper()
71 MIRBuilder.setMF(MF); in LegalizerHelper()
72 MIRBuilder.setChangeObserver(Observer); in LegalizerHelper()
78 : MIRBuilder(B), MRI(MF.getRegInfo()), LI(LI), Observer(Observer) { in LegalizerHelper()
79 MIRBuilder.setMF(MF); in LegalizerHelper()
80 MIRBuilder.setChangeObserver(Observer); in LegalizerHelper()
88 return LI.legalizeIntrinsic(MI, MRI, MIRBuilder) ? Legalized in legalizeInstrStep()
115 return LI.legalizeCustom(MI, MRI, MIRBuilder, Observer) ? Legalized in legalizeInstrStep()
127 MIRBuilder.buildUnmerge(VRegs, Reg); in extractParts()
145 MIRBuilder.buildUnmerge(VRegs, Reg); in extractParts()
[all …]
DIRTranslator.cpp289 MachineIRBuilder &MIRBuilder) { in translateBinaryOp() argument
303 MIRBuilder.buildInstr(Opcode, {Res}, {Op0, Op1}, Flags); in translateBinaryOp()
307 bool IRTranslator::translateFSub(const User &U, MachineIRBuilder &MIRBuilder) { in translateFSub() argument
319 MIRBuilder.buildInstr(TargetOpcode::G_FNEG, {Res}, {Op1}, Flags); in translateFSub()
322 return translateBinaryOp(TargetOpcode::G_FSUB, U, MIRBuilder); in translateFSub()
325 bool IRTranslator::translateFNeg(const User &U, MachineIRBuilder &MIRBuilder) { in translateFNeg() argument
333 MIRBuilder.buildInstr(TargetOpcode::G_FNEG, {Res}, {Op0}, Flags); in translateFNeg()
338 MachineIRBuilder &MIRBuilder) { in translateCompare() argument
347 MIRBuilder.buildICmp(Pred, Res, Op0, Op1); in translateCompare()
349 MIRBuilder.buildCopy( in translateCompare()
[all …]
DCallLowering.cpp32 bool CallLowering::lowerCall(MachineIRBuilder &MIRBuilder, ImmutableCallSite CS, in lowerCall() argument
68 isInTailCallPosition(CS, MIRBuilder.getMF().getTarget()) && in lowerCall()
69 (MIRBuilder.getMF() in lowerCall()
74 return lowerCall(MIRBuilder, Info); in lowerCall()
131 MachineIRBuilder &MIRBuilder) const { in packRegs()
134 const DataLayout &DL = MIRBuilder.getMF().getDataLayout(); in packRegs()
135 MachineRegisterInfo *MRI = MIRBuilder.getMRI(); in packRegs()
145 MIRBuilder.buildUndef(Dst); in packRegs()
148 MIRBuilder.buildInsert(NewDst, Dst, SrcRegs[i], Offsets[i]); in packRegs()
157 MachineIRBuilder &MIRBuilder) const { in unpackRegs()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86CallLowering.cpp99 OutgoingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, in OutgoingValueHandler()
101 : ValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB), in OutgoingValueHandler()
102 DL(MIRBuilder.getMF().getDataLayout()), in OutgoingValueHandler()
103 STI(MIRBuilder.getMF().getSubtarget<X86Subtarget>()) {} in OutgoingValueHandler()
112 MIRBuilder.buildCopy(SPReg, STI.getRegisterInfo()->getStackRegister()); in getStackAddress()
115 MIRBuilder.buildConstant(OffsetReg, Offset); in getStackAddress()
118 MIRBuilder.buildPtrAdd(AddrReg, SPReg, OffsetReg); in getStackAddress()
120 MPO = MachinePointerInfo::getStack(MIRBuilder.getMF(), Offset); in getStackAddress()
141 auto MIB = MIRBuilder.buildAnyExt(LLT::scalar(PhysRegSize), ValVReg); in assignValueToReg()
146 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
[all …]
/external/llvm-project/llvm/lib/Target/X86/
DX86CallLowering.cpp99 X86OutgoingValueHandler(MachineIRBuilder &MIRBuilder, in X86OutgoingValueHandler()
102 : IncomingValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB), in X86OutgoingValueHandler()
103 DL(MIRBuilder.getMF().getDataLayout()), in X86OutgoingValueHandler()
104 STI(MIRBuilder.getMF().getSubtarget<X86Subtarget>()) {} in X86OutgoingValueHandler()
111 MIRBuilder.buildCopy(p0, STI.getRegisterInfo()->getStackRegister()); in getStackAddress()
113 auto OffsetReg = MIRBuilder.buildConstant(SType, Offset); in getStackAddress()
115 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); in getStackAddress()
117 MPO = MachinePointerInfo::getStack(MIRBuilder.getMF(), Offset); in getStackAddress()
140 MIRBuilder.buildAnyExt(LLT::scalar(PhysRegSize), ValVReg).getReg(0); in assignValueToReg()
144 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
[all …]
/external/llvm-project/llvm/lib/Target/Mips/
DMipsLegalizerInfo.cpp335 MachineIRBuilder &MIRBuilder = Helper.MIRBuilder; in legalizeCustom() local
336 MachineRegisterInfo &MRI = *MIRBuilder.getMRI(); in legalizeCustom()
365 MachineFunction &MF = MIRBuilder.getMF(); in legalizeCustom()
373 Val = MIRBuilder.buildAnyExt(s32, Val).getReg(0); in legalizeCustom()
375 Val = MIRBuilder.buildAnyExt(s64, Val).getReg(0); in legalizeCustom()
377 auto C_P2HalfMemSize = MIRBuilder.buildConstant(s32, P2HalfMemSize); in legalizeCustom()
378 auto Addr = MIRBuilder.buildPtrAdd(PtrTy, BaseAddr, C_P2HalfMemSize); in legalizeCustom()
381 MIRBuilder.buildStore(Val, BaseAddr, *P2HalfMemOp); in legalizeCustom()
382 auto C_P2Half_InBits = MIRBuilder.buildConstant(s32, P2HalfMemSize * 8); in legalizeCustom()
383 auto Shift = MIRBuilder.buildLShr(s32, Val, C_P2Half_InBits); in legalizeCustom()
[all …]
DMipsCallLowering.cpp51 if (!MIRBuilder.getMF().getDataLayout().isLittleEndian()) in setLeastSignificantFirst()
59 const Function &F = MIRBuilder.getMF().getFunction(); in handle()
62 MIRBuilder.getMF().getSubtarget().getTargetLowering()); in handle()
92 MipsIncomingValueHandler(MachineIRBuilder &MIRBuilder, in MipsIncomingValueHandler() argument
94 : MipsHandler(MIRBuilder, MRI) {} in MipsIncomingValueHandler()
110 MIRBuilder.getMRI()->addLiveIn(PhysReg); in markPhysRegUsed()
111 MIRBuilder.getMBB().addLiveIn(PhysReg); in markPhysRegUsed()
117 return MIRBuilder.buildLoad(Res, Addr, *MMO); in buildLoad()
123 CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, in CallReturnHandler() argument
125 : MipsIncomingValueHandler(MIRBuilder, MRI), MIB(MIB) {} in CallReturnHandler()
[all …]
DMipsCallLowering.h29 MipsHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI) in MipsHandler() argument
30 : MIRBuilder(MIRBuilder), MRI(MRI) {} in MipsHandler()
43 MachineIRBuilder &MIRBuilder; variable
66 bool lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val,
69 bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F,
72 bool lowerCall(MachineIRBuilder &MIRBuilder,
/external/llvm-project/llvm/lib/Target/ARM/
DARMCallLowering.cpp89 ARMOutgoingValueHandler(MachineIRBuilder &MIRBuilder, in ARMOutgoingValueHandler()
92 : OutgoingValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB) {} in ARMOutgoingValueHandler()
101 auto SPReg = MIRBuilder.buildCopy(p0, Register(ARM::SP)); in getStackAddress()
103 auto OffsetReg = MIRBuilder.buildConstant(s32, Offset); in getStackAddress()
105 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); in getStackAddress()
107 MPO = MachinePointerInfo::getStack(MIRBuilder.getMF(), Offset); in getStackAddress()
120 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
130 auto MMO = MIRBuilder.getMF().getMachineMemOperand( in assignValueToAddress()
133 MIRBuilder.buildStore(ExtReg, Addr, *MMO); in assignValueToAddress()
159 MIRBuilder.buildUnmerge(NewRegs, Arg.Regs[0]); in assignCustomValue()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMCallLowering.cpp89 OutgoingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, in OutgoingValueHandler()
91 : ValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB) {} in OutgoingValueHandler()
103 MIRBuilder.buildCopy(SPReg, Register(ARM::SP)); in getStackAddress()
106 MIRBuilder.buildConstant(OffsetReg, Offset); in getStackAddress()
109 MIRBuilder.buildPtrAdd(AddrReg, SPReg, OffsetReg); in getStackAddress()
111 MPO = MachinePointerInfo::getStack(MIRBuilder.getMF(), Offset); in getStackAddress()
124 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
134 auto MMO = MIRBuilder.getMF().getMachineMemOperand( in assignValueToAddress()
137 MIRBuilder.buildStore(ExtReg, Addr, *MMO); in assignValueToAddress()
160 MIRBuilder.buildUnmerge(NewRegs, Arg.Regs[0]); in assignCustomValue()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64CallLowering.cpp56 IncomingArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, in IncomingArgHandler()
58 : ValueHandler(MIRBuilder, MRI, AssignFn), StackUsed(0) {} in IncomingArgHandler()
62 auto &MFI = MIRBuilder.getMF().getFrameInfo(); in getStackAddress()
64 MPO = MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI); in getStackAddress()
66 MIRBuilder.buildFrameIndex(AddrReg, FI); in getStackAddress()
76 MIRBuilder.buildCopy(ValVReg, PhysReg); in assignValueToReg()
81 auto Copy = MIRBuilder.buildCopy(LLT{VA.getLocVT()}, PhysReg); in assignValueToReg()
82 MIRBuilder.buildTrunc(ValVReg, Copy); in assignValueToReg()
91 auto MMO = MIRBuilder.getMF().getMachineMemOperand( in assignValueToAddress()
94 MIRBuilder.buildLoad(ValVReg, Addr, *MMO); in assignValueToAddress()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsLegalizerInfo.cpp261 MachineIRBuilder &MIRBuilder, in legalizeCustom() argument
266 MIRBuilder.setInstr(MI); in legalizeCustom()
268 static_cast<const MipsSubtarget &>(MIRBuilder.getMF().getSubtarget()); in legalizeCustom()
291 MachineInstrBuilder Bitcast = MIRBuilder.buildInstr( in legalizeCustom()
293 {Src, MIRBuilder.buildConstant(s32, UINT32_C(0x43300000))}); in legalizeCustom()
294 Bitcast.constrainAllUses(MIRBuilder.getTII(), *STI.getRegisterInfo(), in legalizeCustom()
297 MachineInstrBuilder TwoP52FP = MIRBuilder.buildFConstant( in legalizeCustom()
301 MIRBuilder.buildFSub(Dst, Bitcast, TwoP52FP); in legalizeCustom()
303 MachineInstrBuilder ResF64 = MIRBuilder.buildFSub(s64, Bitcast, TwoP52FP); in legalizeCustom()
304 MIRBuilder.buildFPTrunc(Dst, ResF64); in legalizeCustom()
[all …]
DMipsCallLowering.cpp51 if (!MIRBuilder.getMF().getDataLayout().isLittleEndian()) in setLeastSignificantFirst()
59 const Function &F = MIRBuilder.getMF().getFunction(); in handle()
62 MIRBuilder.getMF().getSubtarget().getTargetLowering()); in handle()
92 IncomingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI) in IncomingValueHandler() argument
93 : MipsHandler(MIRBuilder, MRI) {} in IncomingValueHandler()
109 MIRBuilder.getMRI()->addLiveIn(PhysReg); in markPhysRegUsed()
110 MIRBuilder.getMBB().addLiveIn(PhysReg); in markPhysRegUsed()
116 MIRBuilder.buildLoad(Val, Addr, *MMO); in buildLoad()
122 CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, in CallReturnHandler() argument
124 : IncomingValueHandler(MIRBuilder, MRI), MIB(MIB) {} in CallReturnHandler()
[all …]
DMipsCallLowering.h28 MipsHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI) in MipsHandler() argument
29 : MIRBuilder(MIRBuilder), MRI(MRI) {} in MipsHandler()
42 MachineIRBuilder &MIRBuilder; variable
65 bool lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val,
68 bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F,
71 bool lowerCall(MachineIRBuilder &MIRBuilder,
/external/llvm-project/llvm/lib/Target/AArch64/GISel/
DAArch64CallLowering.cpp56 IncomingArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, in IncomingArgHandler()
58 : IncomingValueHandler(MIRBuilder, MRI, AssignFn), StackUsed(0) {} in IncomingArgHandler()
62 auto &MFI = MIRBuilder.getMF().getFrameInfo(); in getStackAddress()
64 MPO = MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI); in getStackAddress()
65 auto AddrReg = MIRBuilder.buildFrameIndex(LLT::pointer(0, 64), FI); in getStackAddress()
75 MIRBuilder.buildCopy(ValVReg, PhysReg); in assignValueToReg()
80 auto Copy = MIRBuilder.buildCopy(LLT{VA.getLocVT()}, PhysReg); in assignValueToReg()
81 MIRBuilder.buildTrunc(ValVReg, Copy); in assignValueToReg()
89 MachineFunction &MF = MIRBuilder.getMF(); in assignValueToAddress()
98 MIRBuilder.buildLoad(ValVReg, Addr, *MMO); in assignValueToAddress()
[all …]
/external/llvm/lib/Target/AArch64/
DAArch64CallLowering.cpp32 bool AArch64CallLowering::lowerReturn(MachineIRBuilder &MIRBuilder, in lowerReturn() argument
34 MachineInstr *Return = MIRBuilder.buildInstr(AArch64::RET_ReallyLR); in lowerReturn()
44 MIRBuilder.setInstr(*Return, /* Before */ true); in lowerReturn()
46 MIRBuilder.buildInstr(TargetOpcode::COPY, ResReg, VReg); in lowerReturn()
50 MachineInstrBuilder(MIRBuilder.getMF(), Return) in lowerReturn()
57 MachineIRBuilder &MIRBuilder, const Function::ArgumentListType &Args, in lowerFormalArguments() argument
59 MachineFunction &MF = MIRBuilder.getMF(); in lowerFormalArguments()
84 MIRBuilder.getMBB().addLiveIn(VA.getLocReg()); in lowerFormalArguments()
85 MIRBuilder.buildInstr(TargetOpcode::COPY, VRegs[i], VA.getLocReg()); in lowerFormalArguments()
/external/llvm-project/llvm/lib/Target/AMDGPU/
DAMDGPUCallLowering.cpp48 return MIRBuilder.buildAnyExt(LLT::scalar(32), ValVReg).getReg(0); in extendRegisterMin32()
82 auto ToSGPR = MIRBuilder.buildIntrinsic(Intrinsic::amdgcn_readfirstlane, in assignValueToReg()
88 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
110 auto &MFI = MIRBuilder.getMF().getFrameInfo(); in getStackAddress()
112 MPO = MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI); in getStackAddress()
113 auto AddrReg = MIRBuilder.buildFrameIndex( in getStackAddress()
126 auto Copy = MIRBuilder.buildCopy(LLT::scalar(32), PhysReg); in assignValueToReg()
127 MIRBuilder.buildTrunc(ValVReg, Copy); in assignValueToReg()
135 auto Copy = MIRBuilder.buildCopy(LLT{VA.getLocVT()}, PhysReg); in assignValueToReg()
136 MIRBuilder.buildTrunc(ValVReg, Copy); in assignValueToReg()
[all …]
/external/llvm/lib/CodeGen/GlobalISel/
DIRTranslator.cpp57 MachineFunction &MF = MIRBuilder.getMF(); in getOrCreateBB()
72 MIRBuilder.buildInstr(Opcode, Inst.getType(), Res, Op0, Op1); in translateBinaryOp()
82 return CLI->lowerReturn(MIRBuilder, Ret, !Ret ? 0 : getOrCreateVReg(*Ret)); in translateReturn()
91 MIRBuilder.buildInstr(TargetOpcode::G_BR, BrTgt.getType(), TgtBB); in translateBr()
96 MachineBasicBlock &CurBB = MIRBuilder.getMBB(); in translateBr()
103 MIRBuilder.setDebugLoc(Inst.getDebugLoc()); in translate()
132 MIRBuilder.setMF(MF); in runOnMachineFunction()
136 MIRBuilder.setMBB(MBB); in runOnMachineFunction()
141 CLI->lowerFormalArguments(MIRBuilder, F.getArgumentList(), VRegArgs); in runOnMachineFunction()
149 MIRBuilder.setMBB(MBB); in runOnMachineFunction()

1234