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/external/llvm-project/llvm/test/MC/AArch64/SVE/
Dldnf1b-diagnostics.s6 ldnf1b z23.b, p0/z, [x13, #-9, MUL VL]
11 ldnf1b z29.b, p0/z, [x3, #8, MUL VL]
16 ldnf1b z21.h, p4/z, [x17, #-9, MUL VL]
21 ldnf1b z10.h, p5/z, [x16, #8, MUL VL]
26 ldnf1b z30.s, p6/z, [x25, #-9, MUL VL]
31 ldnf1b z29.s, p5/z, [x15, #8, MUL VL]
36 ldnf1b z28.d, p2/z, [x28, #-9, MUL VL]
41 ldnf1b z27.d, p1/z, [x26, #8, MUL VL]
50 ldnf1b z27.b, p8/z, [x29, #1, MUL VL]
55 ldnf1b z9.h, p8/z, [x25, #1, MUL VL]
[all …]
Dldnf1sb-diagnostics.s6 ldnf1sb z23.b, p0/z, [x13, #1, MUL VL]
11 ldnf1sb z29.b, p0/z, [x3, #1, MUL VL]
20 ldnf1sb z21.h, p4/z, [x17, #-9, MUL VL]
25 ldnf1sb z10.h, p5/z, [x16, #8, MUL VL]
30 ldnf1sb z30.s, p6/z, [x25, #-9, MUL VL]
35 ldnf1sb z29.s, p5/z, [x15, #8, MUL VL]
40 ldnf1sb z28.d, p2/z, [x28, #-9, MUL VL]
45 ldnf1sb z27.d, p1/z, [x26, #8, MUL VL]
54 ldnf1sb z9.h, p8/z, [x25, #1, MUL VL]
59 ldnf1sb z12.s, p8/z, [x13, #1, MUL VL]
[all …]
Dldnf1h-diagnostics.s6 ldnf1h z21.h, p4/z, [x17, #-9, MUL VL]
11 ldnf1h z10.h, p5/z, [x16, #8, MUL VL]
16 ldnf1h z30.s, p6/z, [x25, #-9, MUL VL]
21 ldnf1h z29.s, p5/z, [x15, #8, MUL VL]
26 ldnf1h z28.d, p2/z, [x28, #-9, MUL VL]
31 ldnf1h z27.d, p1/z, [x26, #8, MUL VL]
40 ldnf1h z9.h, p8/z, [x25, #1, MUL VL]
45 ldnf1h z12.s, p8/z, [x13, #1, MUL VL]
50 ldnf1h z4.d, p8/z, [x11, #1, MUL VL]
59 ldnf1h { }, p0/z, [x1, #1, MUL VL]
[all …]
Dldnf1sh-diagnostics.s6 ldnf1sh z23.h, p0/z, [x13, #1, MUL VL]
11 ldnf1sh z29.h, p0/z, [x3, #1, MUL VL]
20 ldnf1sh z30.s, p6/z, [x25, #-9, MUL VL]
25 ldnf1sh z29.s, p5/z, [x15, #8, MUL VL]
30 ldnf1sh z28.d, p2/z, [x28, #-9, MUL VL]
35 ldnf1sh z27.d, p1/z, [x26, #8, MUL VL]
44 ldnf1sh z12.s, p8/z, [x13, #1, MUL VL]
49 ldnf1sh z4.d, p8/z, [x11, #1, MUL VL]
58 ldnf1sh { }, p0/z, [x1, #1, MUL VL]
63 ldnf1sh { z1.s, z2.s }, p0/z, [x1, #1, MUL VL]
[all …]
Dld1b-diagnostics.s6 ld1b z23.b, p0/z, [x13, #-9, MUL VL]
11 ld1b z29.b, p0/z, [x3, #8, MUL VL]
16 ld1b z21.h, p4/z, [x17, #-9, MUL VL]
21 ld1b z10.h, p5/z, [x16, #8, MUL VL]
26 ld1b z30.s, p6/z, [x25, #-9, MUL VL]
31 ld1b z29.s, p5/z, [x15, #8, MUL VL]
36 ld1b z28.d, p2/z, [x28, #-9, MUL VL]
41 ld1b z27.d, p1/z, [x26, #8, MUL VL]
50 ld1b z27.b, p8/z, [x29, #1, MUL VL]
55 ld1b z9.h, p8/z, [x25, #1, MUL VL]
[all …]
Dst1b-diagnostics.s6 st1b z10.b, p4, [x8, #-9, MUL VL]
11 st1b z18.b, p4, [x24, #8, MUL VL]
16 st1b z11.h, p0, [x23, #-9, MUL VL]
21 st1b z24.h, p3, [x1, #8, MUL VL]
26 st1b z6.s, p5, [x23, #-9, MUL VL]
31 st1b z16.s, p6, [x14, #8, MUL VL]
36 st1b z26.d, p2, [x7, #-9, MUL VL]
41 st1b z27.d, p1, [x12, #8, MUL VL]
49 st1b z12.b, p8, [x27, #6, MUL VL]
54 st1b z23.h, p8, [x20, #1, MUL VL]
[all …]
Dld1sb-diagnostics.s6 ld1sb z23.b, p0/z, [x13, #1, MUL VL]
11 ld1sb z29.b, p0/z, [x3, #1, MUL VL]
20 ld1sb z21.h, p4/z, [x17, #-9, MUL VL]
25 ld1sb z10.h, p5/z, [x16, #8, MUL VL]
30 ld1sb z30.s, p6/z, [x25, #-9, MUL VL]
35 ld1sb z29.s, p5/z, [x15, #8, MUL VL]
40 ld1sb z28.d, p2/z, [x28, #-9, MUL VL]
45 ld1sb z27.d, p1/z, [x26, #8, MUL VL]
54 ld1sb z9.h, p8/z, [x25, #1, MUL VL]
59 ld1sb z12.s, p8/z, [x13, #1, MUL VL]
[all …]
Dldnf1w-diagnostics.s6 ldnf1w z30.s, p6/z, [x25, #-9, MUL VL]
11 ldnf1w z29.s, p5/z, [x15, #8, MUL VL]
16 ldnf1w z28.d, p2/z, [x28, #-9, MUL VL]
21 ldnf1w z27.d, p1/z, [x26, #8, MUL VL]
30 ldnf1w z12.s, p8/z, [x13, #1, MUL VL]
35 ldnf1w z4.d, p8/z, [x11, #1, MUL VL]
44 ldnf1w { }, p0/z, [x1, #1, MUL VL]
49 ldnf1w { z1.s, z2.s }, p0/z, [x1, #1, MUL VL]
54 ldnf1w { v0.2d }, p0/z, [x1, #1, MUL VL]
Dldnf1sw-diagnostics.s6 ldnf1sw z23.s, p0/z, [x13, #1, MUL VL]
11 ldnf1sw z29.s, p0/z, [x3, #1, MUL VL]
20 ldnf1sw z28.d, p2/z, [x28, #-9, MUL VL]
25 ldnf1sw z27.d, p1/z, [x26, #8, MUL VL]
34 ldnf1sw z4.d, p8/z, [x11, #1, MUL VL]
43 ldnf1sw { }, p0/z, [x1, #1, MUL VL]
48 ldnf1sw { z1.d, z2.d }, p0/z, [x1, #1, MUL VL]
53 ldnf1sw { v0.2d }, p0/z, [x1, #1, MUL VL]
Dld1h-diagnostics.s6 ld1h z21.h, p4/z, [x17, #-9, MUL VL]
11 ld1h z10.h, p5/z, [x16, #8, MUL VL]
16 ld1h z30.s, p6/z, [x25, #-9, MUL VL]
21 ld1h z29.s, p5/z, [x15, #8, MUL VL]
26 ld1h z28.d, p2/z, [x28, #-9, MUL VL]
31 ld1h z27.d, p1/z, [x26, #8, MUL VL]
40 ld1h z9.h, p8/z, [x25, #1, MUL VL]
45 ld1h z12.s, p8/z, [x13, #1, MUL VL]
50 ld1h z4.d, p8/z, [x11, #1, MUL VL]
59 ld1h { }, p0/z, [x1, #1, MUL VL]
[all …]
Dst1h-diagnostics.s6 st1h z29.h, p5, [x7, #-9, MUL VL]
11 st1h z29.h, p5, [x4, #8, MUL VL]
16 st1h z21.s, p2, [x1, #-9, MUL VL]
21 st1h z17.s, p5, [x1, #8, MUL VL]
26 st1h z0.d, p1, [x14, #-9, MUL VL]
31 st1h z24.d, p3, [x16, #8, MUL VL]
39 st1h z15.h, p8, [x0, #8, MUL VL]
44 st1h z17.s, p8, [x20, #2, MUL VL]
49 st1h z15.d, p8, [x0, #8, MUL VL]
54 st1h z15.d, p7.b, [x0, #8, MUL VL]
[all …]
Dld1sh-diagnostics.s6 ld1sh z23.h, p0/z, [x13, #1, MUL VL]
11 ld1sh z29.h, p0/z, [x3, #1, MUL VL]
20 ld1sh z30.s, p6/z, [x25, #-9, MUL VL]
25 ld1sh z29.s, p5/z, [x15, #8, MUL VL]
30 ld1sh z28.d, p2/z, [x28, #-9, MUL VL]
35 ld1sh z27.d, p1/z, [x26, #8, MUL VL]
44 ld1sh z12.s, p8/z, [x13, #1, MUL VL]
49 ld1sh z4.d, p8/z, [x11, #1, MUL VL]
58 ld1sh { }, p0/z, [x1, #1, MUL VL]
63 ld1sh { z1.s, z2.s }, p0/z, [x1, #1, MUL VL]
[all …]
Dldnf1d-diagnostics.s6 ldnf1d z28.d, p2/z, [x28, #-9, MUL VL]
11 ldnf1d z27.d, p1/z, [x26, #8, MUL VL]
20 ldnf1d z4.d, p8/z, [x11, #1, MUL VL]
29 ldnf1d { }, p0/z, [x1, #1, MUL VL]
34 ldnf1d { z1.d, z2.d }, p0/z, [x1, #1, MUL VL]
39 ldnf1d { v0.2d }, p0/z, [x1, #1, MUL VL]
Dld1w-diagnostics.s6 ld1w z30.s, p6/z, [x25, #-9, MUL VL]
11 ld1w z29.s, p5/z, [x15, #8, MUL VL]
16 ld1w z28.d, p2/z, [x28, #-9, MUL VL]
21 ld1w z27.d, p1/z, [x26, #8, MUL VL]
30 ld1w z12.s, p8/z, [x13, #1, MUL VL]
35 ld1w z4.d, p8/z, [x11, #1, MUL VL]
44 ld1w { }, p0/z, [x1, #1, MUL VL]
49 ld1w { z1.s, z2.s }, p0/z, [x1, #1, MUL VL]
54 ld1w { v0.2d }, p0/z, [x1, #1, MUL VL]
Dst2d-diagnostics.s7 st2d {z12.d, z13.d}, p4, [x12, #-18, MUL VL]
12 st2d {z7.d, z8.d}, p3, [x1, #16, MUL VL]
21 st2d {z12.d, z13.d}, p4, [x12, #-7, MUL VL]
26 st2d {z7.d, z8.d}, p3, [x1, #5, MUL VL]
64 st2d {z2.d, z3.d}, p8, [x15, #10, MUL VL]
69 st2d {z2.d, z3.d}, p7.b, [x15, #10, MUL VL]
74 st2d {z2.d, z3.d}, p7.q, [x15, #10, MUL VL]
Dst2w-diagnostics.s7 st2w {z12.s, z13.s}, p4, [x12, #-18, MUL VL]
12 st2w {z7.s, z8.s}, p3, [x1, #16, MUL VL]
21 st2w {z12.s, z13.s}, p4, [x12, #-7, MUL VL]
26 st2w {z7.s, z8.s}, p3, [x1, #5, MUL VL]
64 st2w {z2.s, z3.s}, p8, [x15, #10, MUL VL]
69 st2w {z2.s, z3.s}, p7.b, [x15, #10, MUL VL]
74 st2w {z2.s, z3.s}, p7.q, [x15, #10, MUL VL]
Dst2h-diagnostics.s7 st2h {z12.h, z13.h}, p4, [x12, #-18, MUL VL]
12 st2h {z7.h, z8.h}, p3, [x1, #16, MUL VL]
21 st2h {z12.h, z13.h}, p4, [x12, #-7, MUL VL]
26 st2h {z7.h, z8.h}, p3, [x1, #5, MUL VL]
64 st2h {z2.h, z3.h}, p8, [x15, #10, MUL VL]
69 st2h {z2.h, z3.h}, p7.b, [x15, #10, MUL VL]
74 st2h {z2.h, z3.h}, p7.q, [x15, #10, MUL VL]
Dst2b-diagnostics.s7 st2b {z12.b, z13.b}, p4, [x12, #-18, MUL VL]
12 st2b {z7.b, z8.b}, p3, [x1, #16, MUL VL]
21 st2b {z12.b, z13.b}, p4, [x12, #-7, MUL VL]
26 st2b {z7.b, z8.b}, p3, [x1, #5, MUL VL]
59 st2b {z2.b, z3.b}, p8, [x15, #10, MUL VL]
64 st2b {z2.b, z3.b}, p7.b, [x15, #10, MUL VL]
69 st2b {z2.b, z3.b}, p7.q, [x15, #10, MUL VL]
/external/virglrenderer/tests/
Dlarge_shader.h36 4: MUL TEMP[1].xy, TEMP[0].xyyy, TEMP[1].xyyy
40 8: MUL TEMP[3].x, CONST[0].xxxx, TEMP[3].xxxx
41 9: MUL TEMP[2].x, TEMP[1].xxxx, TEMP[3].xxxx
42 10: MUL TEMP[2].xyz, TEMP[2].xxxx, IMM[0].zzww
47 15: MUL TEMP[1].xyz, TEMP[1].xyzz, TEMP[2].xxxx
59 27: MUL TEMP[8].x, TEMP[8].xxxx, TEMP[7].xxxx
62 30: MUL TEMP[10].xyz, TEMP[2].xyzz, IMM[2].wwww
66 34: MUL TEMP[14].xyz, TEMP[13].xyzz, TEMP[13].xyzz
67 35: MUL TEMP[15].xyz, IMM[0].xxxx, TEMP[13].xyzz
69 37: MUL TEMP[17].xyz, TEMP[14].xyzz, TEMP[16].xyzz
[all …]
/external/llvm-project/llvm/test/Transforms/InstCombine/
Dvector-mul.ll30 ; CHECK-NEXT: [[MUL:%.*]] = shl <4 x i8> [[INVEC:%.*]], <i8 1, i8 1, i8 1, i8 1>
31 ; CHECK-NEXT: ret <4 x i8> [[MUL]]
41 ; CHECK-NEXT: [[MUL:%.*]] = shl <4 x i8> [[INVEC:%.*]], <i8 2, i8 2, i8 2, i8 2>
42 ; CHECK-NEXT: ret <4 x i8> [[MUL]]
52 ; CHECK-NEXT: [[MUL:%.*]] = shl <4 x i8> [[INVEC:%.*]], <i8 3, i8 3, i8 3, i8 3>
53 ; CHECK-NEXT: ret <4 x i8> [[MUL]]
63 ; CHECK-NEXT: [[MUL:%.*]] = shl <4 x i8> [[INVEC:%.*]], <i8 0, i8 1, i8 2, i8 3>
64 ; CHECK-NEXT: ret <4 x i8> [[MUL]]
74 ; CHECK-NEXT: [[MUL:%.*]] = mul <4 x i8> [[INVEC:%.*]], <i8 3, i8 3, i8 3, i8 3>
75 ; CHECK-NEXT: ret <4 x i8> [[MUL]]
[all …]
Dfmul-pow.ll9 ; CHECK-NEXT: [[MUL:%.*]] = fmul double [[TMP1]], [[A]]
10 ; CHECK-NEXT: ret double [[MUL]]
20 ; CHECK-NEXT: [[MUL:%.*]] = fmul reassoc double [[TMP1]], [[A]]
21 ; CHECK-NEXT: ret double [[MUL]]
31 ; CHECK-NEXT: [[MUL:%.*]] = fdiv reassoc double [[TMP1]], [[A]]
32 ; CHECK-NEXT: ret double [[MUL]]
44 ; CHECK-NEXT: [[MUL:%.*]] = fmul double [[TMP2]], [[TMP1]]
45 ; CHECK-NEXT: ret double [[MUL]]
57 ; CHECK-NEXT: [[MUL:%.*]] = fmul reassoc double [[TMP2]], [[TMP1]]
58 ; CHECK-NEXT: ret double [[MUL]]
[all …]
Dfmul.ll7 ; CHECK-NEXT: [[MUL:%.*]] = fmul ninf float [[X:%.*]], -2.000000e+01
8 ; CHECK-NEXT: ret float [[MUL]]
17 ; CHECK-NEXT: [[MUL:%.*]] = fmul ninf float [[X:%.*]], -2.000000e+01
18 ; CHECK-NEXT: ret float [[MUL]]
27 ; CHECK-NEXT: [[MUL:%.*]] = fmul ninf <2 x float> [[X:%.*]], <float -2.000000e+00, float -3.0000…
28 ; CHECK-NEXT: ret <2 x float> [[MUL]]
37 ; CHECK-NEXT: [[MUL:%.*]] = fmul ninf <2 x float> [[X:%.*]], <float -2.000000e+00, float -3.0000…
38 ; CHECK-NEXT: ret <2 x float> [[MUL]]
47 ; CHECK-NEXT: [[MUL:%.*]] = fmul ninf <2 x float> [[X:%.*]], <float -2.000000e+00, float -3.0000…
48 ; CHECK-NEXT: ret <2 x float> [[MUL]]
[all …]
Dpow-exp.ll6 ; CHECK-NEXT: [[MUL:%.*]] = fmul fast float [[X:%.*]], [[Y:%.*]]
7 ; CHECK-NEXT: [[EXP:%.*]] = call fast float @llvm.exp.f32(float [[MUL]])
17 ; CHECK-NEXT: [[MUL:%.*]] = fmul fast float [[X:%.*]], [[Y:%.*]]
18 ; CHECK-NEXT: [[EXPF:%.*]] = call fast float @expf(float [[MUL]])
28 ; CHECK-NEXT: [[MUL:%.*]] = fmul fast double [[X:%.*]], [[Y:%.*]]
29 ; CHECK-NEXT: [[EXP:%.*]] = call fast double @llvm.exp.f64(double [[MUL]])
39 ; CHECK-NEXT: [[MUL:%.*]] = fmul fast double [[X:%.*]], [[Y:%.*]]
40 ; CHECK-NEXT: [[EXP:%.*]] = call fast double @llvm.exp.f64(double [[MUL]])
50 ; CHECK-NEXT: [[MUL:%.*]] = fmul fast fp128 [[X:%.*]], [[Y:%.*]]
51 ; CHECK-NEXT: [[EXP:%.*]] = call fast fp128 @llvm.exp.f128(fp128 [[MUL]])
[all …]
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Damdgpu-codegenprepare-mul24.ll11 ; SI-NEXT: [[MUL:%.*]] = trunc i32 [[TMP3]] to i16
12 ; SI-NEXT: ret i16 [[MUL]]
15 ; VI-NEXT: [[MUL:%.*]] = mul i16 [[LHS:%.*]], [[RHS:%.*]]
16 ; VI-NEXT: ret i16 [[MUL]]
19 ; DISABLED-NEXT: [[MUL:%.*]] = mul i16 [[LHS:%.*]], [[RHS:%.*]]
20 ; DISABLED-NEXT: ret i16 [[MUL]]
32 ; SI-NEXT: [[MUL:%.*]] = call i32 @llvm.amdgcn.mul.i24(i32 [[LHS24]], i32 [[RHS24]])
33 ; SI-NEXT: ret i32 [[MUL]]
40 ; VI-NEXT: [[MUL:%.*]] = call i32 @llvm.amdgcn.mul.i24(i32 [[LHS24]], i32 [[RHS24]])
41 ; VI-NEXT: ret i32 [[MUL]]
[all …]
/external/llvm-project/llvm/test/Transforms/Reassociate/
Dwrap-flags.ll11 ; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[I:%.*]], -2147483648
12 ; CHECK-NEXT: [[MUL2:%.*]] = add i32 [[MUL]], 1
25 ; CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[I:%.*]], 1073741824
26 ; CHECK-NEXT: [[MUL2:%.*]] = add i32 [[MUL]], 1
39 ; CHECK-NEXT: [[MUL:%.*]] = mul nuw i32 [[I:%.*]], 4
40 ; CHECK-NEXT: [[MUL2:%.*]] = add i32 [[MUL]], 1
53 ; CHECK-NEXT: [[MUL:%.*]] = mul nuw nsw i32 [[I:%.*]], 4
54 ; CHECK-NEXT: [[MUL2:%.*]] = add i32 [[MUL]], 1
67 ; CHECK-NEXT: [[MUL:%.*]] = mul nuw nsw i32 [[I:%.*]], -2147483648
68 ; CHECK-NEXT: [[MUL2:%.*]] = add i32 [[MUL]], 1

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