| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | RegAllocFast.cpp | 87 MCPhysReg PhysReg = 0; ///< Currently held here. member
140 void setPhysRegState(MCPhysReg PhysReg, unsigned NewState);
143 void markRegUsedInInstr(MCPhysReg PhysReg) { in markRegUsedInInstr() argument
144 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) in markRegUsedInInstr()
149 bool isRegUsedInInstr(MCPhysReg PhysReg) const { in isRegUsedInInstr()
150 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) in isRegUsedInInstr()
198 void definePhysReg(MachineBasicBlock::iterator MI, MCPhysReg PhysReg,
200 unsigned calcSpillCost(MCPhysReg PhysReg) const;
201 void assignVirtToPhysReg(LiveReg &, MCPhysReg PhysReg);
218 bool setPhysReg(MachineInstr &MI, MachineOperand &MO, MCPhysReg PhysReg);
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| D | LiveRegMatrix.cpp | 81 LiveInterval &VRegInterval, unsigned PhysReg, in foreachUnit() argument
84 for (MCRegUnitMaskIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { in foreachUnit()
96 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { in foreachUnit()
104 void LiveRegMatrix::assign(LiveInterval &VirtReg, unsigned PhysReg) { in assign() argument
106 << printReg(PhysReg, TRI) << ':'); in assign()
108 VRM->assignVirt2Phys(VirtReg.reg, PhysReg); in assign()
111 TRI, VirtReg, PhysReg, [&](unsigned Unit, const LiveRange &Range) { in assign()
122 Register PhysReg = VRM->getPhys(VirtReg.reg); in unassign() local
124 << printReg(PhysReg, TRI) << ':'); in unassign()
127 foreachUnit(TRI, VirtReg, PhysReg, in unassign()
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| D | ReachingDefAnalysis.cpp | 43 for (MCRegUnitIterator Unit(LI.PhysReg, TRI); Unit.isValid(); ++Unit) { in enterBasicBlock()
172 int ReachingDefAnalysis::getReachingDef(MachineInstr *MI, int PhysReg) { in getReachingDef() argument
180 for (MCRegUnitIterator Unit(PhysReg, TRI); Unit.isValid(); ++Unit) { in getReachingDef()
191 MachineInstr* ReachingDefAnalysis::getReachingMIDef(MachineInstr *MI, int PhysReg) { in getReachingMIDef() argument
192 return getInstFromId(MI->getParent(), getReachingDef(MI, PhysReg)); in getReachingMIDef()
196 int PhysReg) { in hasSameReachingDef() argument
202 return getReachingDef(A, PhysReg) == getReachingDef(B, PhysReg); in hasSameReachingDef()
222 int ReachingDefAnalysis::getClearance(MachineInstr *MI, MCPhysReg PhysReg) { in getClearance() argument
224 return InstIds[MI] - getReachingDef(MI, PhysReg); in getClearance()
227 void ReachingDefAnalysis::getReachingLocalUses(MachineInstr *Def, int PhysReg, in getReachingLocalUses() argument
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| D | RegAllocGreedy.cpp | 323 void addEviction(unsigned PhysReg, unsigned Evictor, unsigned Evictee) { in addEviction() argument
325 Evictees[Evictee].second = PhysReg; in addEviction()
357 unsigned PhysReg; member
370 PhysReg = Reg; in reset()
469 bool canEvictInterferenceInRange(LiveInterval &VirtReg, unsigned PhysReg,
477 bool mayRecolorAllInterferences(unsigned PhysReg, LiveInterval &VirtReg,
503 unsigned PhysReg, unsigned &CostPerUseLimit,
531 unsigned PhysReg; member
533 HintInfo(BlockFrequency Freq, unsigned Reg, unsigned PhysReg) in HintInfo()
534 : Freq(Freq), Reg(Reg), PhysReg(PhysReg) {} in HintInfo()
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| D | RegisterClassInfo.cpp | 111 unsigned PhysReg = RawOrder[i]; in compute() local
113 if (Reserved.test(PhysReg)) in compute()
115 unsigned Cost = TRI->getCostPerUse(PhysReg); in compute()
118 if (CalleeSavedAliases[PhysReg] && in compute()
119 !STI.ignoreCSRForAllocationOrder(*MF, PhysReg)) in compute()
121 CSRAlias.push_back(PhysReg); in compute()
125 RCI.Order[N++] = PhysReg; in compute()
134 unsigned PhysReg = CSRAlias[i]; in compute() local
135 unsigned Cost = TRI->getCostPerUse(PhysReg); in compute()
138 RCI.Order[N++] = PhysReg; in compute()
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| /external/llvm-project/llvm/lib/CodeGen/ |
| D | ReachingDefAnalysis.cpp | 32 static bool isValidRegUseOf(const MachineOperand &MO, MCRegister PhysReg) { in isValidRegUseOf() argument
33 return isValidRegUse(MO) && MO.getReg() == PhysReg; in isValidRegUseOf()
40 static bool isValidRegDefOf(const MachineOperand &MO, MCRegister PhysReg) { in isValidRegDefOf() argument
41 return isValidRegDef(MO) && MO.getReg() == PhysReg; in isValidRegDefOf()
61 for (MCRegUnitIterator Unit(LI.PhysReg, TRI); Unit.isValid(); ++Unit) { in enterBasicBlock()
257 MCRegister PhysReg) const { in getReachingDef()
265 for (MCRegUnitIterator Unit(PhysReg, TRI); Unit.isValid(); ++Unit) { in getReachingDef()
278 MCRegister PhysReg) const { in getReachingLocalMIDef()
279 return hasLocalDefBefore(MI, PhysReg) in getReachingLocalMIDef()
280 ? getInstFromId(MI->getParent(), getReachingDef(MI, PhysReg)) in getReachingLocalMIDef()
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| D | RegAllocFast.cpp | 91 MCPhysReg PhysReg = 0; ///< Currently held here. member
148 void setPhysRegState(MCPhysReg PhysReg, unsigned NewState);
149 bool isPhysRegFree(MCPhysReg PhysReg) const;
152 void markRegUsedInInstr(MCPhysReg PhysReg) { in markRegUsedInInstr() argument
153 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) in markRegUsedInInstr()
158 bool isRegUsedInInstr(MCPhysReg PhysReg, bool LookAtPhysRegUses) const { in isRegUsedInInstr() argument
159 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { in isRegUsedInInstr()
170 void markPhysRegUsedInInstr(MCPhysReg PhysReg) { in markPhysRegUsedInInstr() argument
171 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) in markPhysRegUsedInInstr()
176 void unmarkRegUsedInInstr(MCPhysReg PhysReg) { in unmarkRegUsedInInstr() argument
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| D | LiveRegMatrix.cpp | 81 LiveInterval &VRegInterval, MCRegister PhysReg, in foreachUnit() argument
84 for (MCRegUnitMaskIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { in foreachUnit()
96 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { in foreachUnit()
104 void LiveRegMatrix::assign(LiveInterval &VirtReg, MCRegister PhysReg) { in assign() argument
106 << printReg(PhysReg, TRI) << ':'); in assign()
108 VRM->assignVirt2Phys(VirtReg.reg(), PhysReg); in assign()
111 TRI, VirtReg, PhysReg, [&](unsigned Unit, const LiveRange &Range) { in assign()
122 Register PhysReg = VRM->getPhys(VirtReg.reg()); in unassign() local
124 << " from " << printReg(PhysReg, TRI) << ':'); in unassign()
127 foreachUnit(TRI, VirtReg, PhysReg, in unassign()
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| D | RegAllocGreedy.cpp | 318 void addEviction(MCRegister PhysReg, Register Evictor, Register Evictee) { in addEviction() argument
320 Evictees[Evictee].second = PhysReg; in addEviction()
352 MCRegister PhysReg; member
365 PhysReg = Reg; in reset()
470 bool canEvictInterferenceInRange(LiveInterval &VirtReg, MCRegister PhysReg,
478 bool mayRecolorAllInterferences(MCRegister PhysReg, LiveInterval &VirtReg,
503 AllocationOrder &Order, MCRegister PhysReg,
532 MCRegister PhysReg; member
534 HintInfo(BlockFrequency Freq, Register Reg, MCRegister PhysReg) in HintInfo()
535 : Freq(Freq), Reg(Reg), PhysReg(PhysReg) {} in HintInfo()
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| D | RegisterClassInfo.cpp | 111 unsigned PhysReg = RawOrder[i]; in compute() local
113 if (Reserved.test(PhysReg)) in compute()
115 unsigned Cost = TRI->getCostPerUse(PhysReg); in compute()
118 if (CalleeSavedAliases[PhysReg] && in compute()
119 !STI.ignoreCSRForAllocationOrder(*MF, PhysReg)) in compute()
121 CSRAlias.push_back(PhysReg); in compute()
125 RCI.Order[N++] = PhysReg; in compute()
134 unsigned PhysReg = CSRAlias[i]; in compute() local
135 unsigned Cost = TRI->getCostPerUse(PhysReg); in compute()
138 RCI.Order[N++] = PhysReg; in compute()
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| /external/llvm/lib/CodeGen/ |
| D | RegAllocFast.cpp | 72 unsigned PhysReg; // Currently held here. member
77 : LastUse(nullptr), VirtReg(v), PhysReg(0), LastOpNum(0), Dirty(false){} in LiveReg()
123 void markRegUsedInInstr(unsigned PhysReg) { in markRegUsedInInstr() argument
124 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) in markRegUsedInInstr()
129 bool isRegUsedInInstr(unsigned PhysReg) const { in isRegUsedInInstr()
130 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) in isRegUsedInInstr()
181 void definePhysReg(MachineInstr &MI, unsigned PhysReg, RegState NewState);
182 unsigned calcSpillCost(unsigned PhysReg) const;
183 void assignVirtToPhysReg(LiveReg&, unsigned PhysReg);
190 LiveRegMap::iterator assignVirtToPhysReg(unsigned VReg, unsigned PhysReg);
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| D | LiveRegMatrix.cpp | 75 unsigned PhysReg, Callable Func) { in foreachUnit() argument
77 for (MCRegUnitMaskIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { in foreachUnit()
89 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { in foreachUnit()
97 void LiveRegMatrix::assign(LiveInterval &VirtReg, unsigned PhysReg) { in assign() argument
99 << " to " << PrintReg(PhysReg, TRI) << ':'); in assign()
101 VRM->assignVirt2Phys(VirtReg.reg, PhysReg); in assign()
103 foreachUnit(TRI, VirtReg, PhysReg, [&](unsigned Unit, in assign()
115 unsigned PhysReg = VRM->getPhys(VirtReg.reg); in unassign() local
117 << " from " << PrintReg(PhysReg, TRI) << ':'); in unassign()
120 foreachUnit(TRI, VirtReg, PhysReg, [&](unsigned Unit, in unassign()
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| D | RegAllocGreedy.cpp | 263 unsigned PhysReg; member
276 PhysReg = Reg; in reset()
357 unsigned canReassign(LiveInterval &VirtReg, unsigned PhysReg);
362 bool mayRecolorAllInterferences(unsigned PhysReg, LiveInterval &VirtReg,
384 unsigned PhysReg, unsigned &CostPerUseLimit,
411 unsigned PhysReg; member
412 HintInfo(BlockFrequency Freq, unsigned Reg, unsigned PhysReg) in HintInfo()
413 : Freq(Freq), Reg(Reg), PhysReg(PhysReg) {} in HintInfo()
419 bool isUnusedCalleeSavedReg(unsigned PhysReg) const;
622 unsigned PhysReg; in tryAssign() local
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| D | VirtRegMap.cpp | 168 void addLiveInsForSubRanges(const LiveInterval &LI, unsigned PhysReg) const;
245 unsigned PhysReg) const { in addLiveInsForSubRanges()
283 MBB->addLiveIn(PhysReg, LaneMask); in addLiveInsForSubRanges()
299 unsigned PhysReg = VRM->getPhys(VirtReg); in addMBBLiveIns() local
300 assert(PhysReg != VirtRegMap::NO_PHYS_REG && "Unmapped virtual register."); in addMBBLiveIns()
303 addLiveInsForSubRanges(LI, PhysReg); in addMBBLiveIns()
313 MBB->addLiveIn(PhysReg); in addMBBLiveIns()
399 unsigned PhysReg = VRM->getPhys(VirtReg); in rewrite() local
400 assert(PhysReg != VirtRegMap::NO_PHYS_REG && in rewrite()
402 assert(!MRI->isReserved(PhysReg) && "Reserved register assignment"); in rewrite()
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| D | RegisterClassInfo.cpp | 99 unsigned PhysReg = RawOrder[i]; in compute() local
101 if (Reserved.test(PhysReg)) in compute()
103 unsigned Cost = TRI->getCostPerUse(PhysReg); in compute()
106 if (CSRNum[PhysReg]) in compute()
108 CSRAlias.push_back(PhysReg); in compute()
112 RCI.Order[N++] = PhysReg; in compute()
121 unsigned PhysReg = CSRAlias[i]; in compute() local
122 unsigned Cost = TRI->getCostPerUse(PhysReg); in compute()
125 RCI.Order[N++] = PhysReg; in compute()
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| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | ReachingDefAnalysis.h | 142 int getReachingDef(MachineInstr *MI, MCRegister PhysReg) const;
146 MCRegister PhysReg) const;
150 bool isReachingDefLiveOut(MachineInstr *MI, MCRegister PhysReg) const;
155 MCRegister PhysReg) const;
160 MCRegister PhysReg) const;
172 bool hasLocalDefBefore(MachineInstr *MI, MCRegister PhysReg) const;
176 bool isRegUsedAfter(MachineInstr *MI, MCRegister PhysReg) const;
179 bool isRegDefinedAfter(MachineInstr *MI, MCRegister PhysReg) const;
183 int getClearance(MachineInstr *MI, MCRegister PhysReg) const;
187 void getReachingLocalUses(MachineInstr *MI, MCRegister PhysReg,
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| D | LiveRegMatrix.h | 107 InterferenceKind checkInterference(LiveInterval &VirtReg, MCRegister PhysReg);
114 bool checkInterference(SlotIndex Start, SlotIndex End, MCRegister PhysReg);
119 void assign(LiveInterval &VirtReg, MCRegister PhysReg);
127 bool isPhysRegUsed(MCRegister PhysReg) const;
140 MCRegister PhysReg = MCRegister::NoRegister);
145 bool checkRegUnitInterference(LiveInterval &VirtReg, MCRegister PhysReg);
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| /external/llvm-project/llvm/tools/llvm-exegesis/lib/ |
| D | RegisterAliasing.cpp | 17 for (const size_t PhysReg : SourceBits.set_bits()) { in getAliasedBits() local
19 for (auto Itr = RegAliasItr(PhysReg, &RegInfo, true); Itr.isValid(); in getAliasedBits()
35 for (MCPhysReg PhysReg : RegClass) in RegisterAliasingTracker() local
36 if (!ReservedReg[PhysReg]) // Removing reserved registers. in RegisterAliasingTracker()
37 SourceBits.set(PhysReg); in RegisterAliasingTracker()
42 const MCPhysReg PhysReg) in RegisterAliasingTracker() argument
44 SourceBits.set(PhysReg); in RegisterAliasingTracker()
51 for (const size_t PhysReg : SourceBits.set_bits()) { in FillOriginAndAliasedBits() local
52 for (auto Itr = RegAliasItr(PhysReg, &RegInfo, true); Itr.isValid(); in FillOriginAndAliasedBits()
55 Origins[*Itr] = PhysReg; in FillOriginAndAliasedBits()
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | ReachingDefAnalysis.h | 96 int getReachingDef(MachineInstr *MI, int PhysReg);
100 MachineInstr *getReachingMIDef(MachineInstr *MI, int PhysReg);
107 bool hasSameReachingDef(MachineInstr *A, MachineInstr *B, int PhysReg);
111 bool isReachingDefLiveOut(MachineInstr *MI, int PhysReg);
116 int PhysReg);
120 bool isRegUsedAfter(MachineInstr *MI, int PhysReg);
123 MachineInstr *getInstWithUseBefore(MachineInstr *MI, int PhysReg);
126 void getAllInstWithUseBefore(MachineInstr *MI, int PhysReg,
131 int getClearance(MachineInstr *MI, MCPhysReg PhysReg);
135 void getReachingLocalUses(MachineInstr *MI, int PhysReg,
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| D | LiveRegMatrix.h | 107 InterferenceKind checkInterference(LiveInterval &VirtReg, unsigned PhysReg);
114 bool checkInterference(SlotIndex Start, SlotIndex End, unsigned PhysReg);
119 void assign(LiveInterval &VirtReg, unsigned PhysReg);
127 bool isPhysRegUsed(unsigned PhysReg) const;
139 bool checkRegMaskInterference(LiveInterval &VirtReg, unsigned PhysReg = 0);
144 bool checkRegUnitInterference(LiveInterval &VirtReg, unsigned PhysReg);
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| /external/mesa3d/src/amd/compiler/ |
| D | aco_ir.h | 369 struct PhysReg { struct
370 constexpr PhysReg() = default;
371 explicit constexpr PhysReg(unsigned r) : reg_b(r << 2) {} in PhysReg() argument
375 constexpr bool operator==(PhysReg other) const { return reg_b == other.reg_b; } argument
376 constexpr bool operator!=(PhysReg other) const { return reg_b != other.reg_b; }
377 constexpr bool operator <(PhysReg other) const { return reg_b < other.reg_b; }
378 …constexpr PhysReg advance(int bytes) const { PhysReg res = *this; res.reg_b += bytes; return res; } in advance() argument
384 static constexpr PhysReg m0{124}; argument
385 static constexpr PhysReg vcc{106};
386 static constexpr PhysReg vcc_hi{107};
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| D | aco_lower_to_hw_instr.cpp | 199 void emit_int64_dpp_op(lower_context *ctx, PhysReg dst_reg, PhysReg src0_reg, PhysReg src1_reg, in emit_int64_dpp_op()
200 PhysReg vtmp_reg, ReduceOp op, in emit_int64_dpp_op()
205 Definition dst[] = {Definition(dst_reg, v1), Definition(PhysReg{dst_reg+1}, v1)}; in emit_int64_dpp_op()
206 Definition vtmp_def[] = {Definition(vtmp_reg, v1), Definition(PhysReg{vtmp_reg+1}, v1)}; in emit_int64_dpp_op()
207 Operand src0[] = {Operand(src0_reg, v1), Operand(PhysReg{src0_reg+1}, v1)}; in emit_int64_dpp_op()
208 Operand src1[] = {Operand(src1_reg, v1), Operand(PhysReg{src1_reg+1}, v1)}; in emit_int64_dpp_op()
210 Operand vtmp_op[] = {Operand(vtmp_reg, v1), Operand(PhysReg{vtmp_reg+1}, v1)}; in emit_int64_dpp_op()
308 void emit_int64_op(lower_context *ctx, PhysReg dst_reg, PhysReg src0_reg, PhysReg src1_reg, PhysReg… in emit_int64_op()
311 Definition dst[] = {Definition(dst_reg, v1), Definition(PhysReg{dst_reg+1}, v1)}; in emit_int64_op()
313 Operand src0[] = {Operand(src0_reg, src0_rc), Operand(PhysReg{src0_reg+1}, src0_rc)}; in emit_int64_op()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIPreAllocateWWMRegs.cpp | 107 for (unsigned PhysReg : RegClassInfo.getOrder(MRI->getRegClass(Reg))) { in processDef() local
108 if (!MRI->isPhysRegUsed(PhysReg) && in processDef()
109 Matrix->checkInterference(LI, PhysReg) == LiveRegMatrix::IK_Free) { in processDef()
110 Matrix->assign(LI, PhysReg); in processDef()
111 assert(PhysReg != 0); in processDef()
135 Register PhysReg = VRM->getPhys(VirtReg); in rewriteRegs() local
138 PhysReg = TRI->getSubReg(PhysReg, SubReg); in rewriteRegs()
142 MO.setReg(PhysReg); in rewriteRegs()
153 const Register PhysReg = VRM->getPhys(Reg); in rewriteRegs() local
154 assert(PhysReg != 0); in rewriteRegs()
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | SIPreAllocateWWMRegs.cpp | 106 for (MCRegister PhysReg : RegClassInfo.getOrder(MRI->getRegClass(Reg))) { in processDef() local
107 if (!MRI->isPhysRegUsed(PhysReg) && in processDef()
108 Matrix->checkInterference(LI, PhysReg) == LiveRegMatrix::IK_Free) { in processDef()
109 Matrix->assign(LI, PhysReg); in processDef()
110 assert(PhysReg != 0); in processDef()
134 Register PhysReg = VRM->getPhys(VirtReg); in rewriteRegs() local
137 PhysReg = TRI->getSubReg(PhysReg, SubReg); in rewriteRegs()
141 MO.setReg(PhysReg); in rewriteRegs()
152 const Register PhysReg = VRM->getPhys(Reg); in rewriteRegs() local
153 assert(PhysReg != 0); in rewriteRegs()
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| /external/mesa3d/src/amd/compiler/tests/ |
| D | test_assembler.cpp | 37 bld.smem(aco_opcode::s_memtime, bld.def(s2)).def(0).setFixed(PhysReg{0});
50 bld.sopp(aco_opcode::s_branch, Definition(PhysReg(0), s2), 1);
73 bld.sopp(aco_opcode::s_branch, Definition(PhysReg(0), s2), 2);
104 bld.sopp(aco_opcode::s_cbranch_scc0, Definition(PhysReg(0), s2), 2);
141 bld.sopp(aco_opcode::s_branch, Definition(PhysReg(0), s2), 0);
170 bld.sopp(aco_opcode::s_cbranch_execnz, Definition(PhysReg(0), s2), 0);
189 bld.sopp(aco_opcode::s_branch, Definition(PhysReg(0), s2), 1);
193 bld.sopp(aco_opcode::s_branch, Definition(PhysReg(0), s2), 2);
212 bld.sopp(aco_opcode::s_branch, Definition(PhysReg(0), s2), 2);
223 bld.sop1(aco_opcode::p_constaddr, Definition(PhysReg(0), s2), Operand(0u));
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