| /external/llvm-project/llvm/lib/Target/PowerPC/GISel/ |
| D | PPCInstructionSelector.cpp | 36 const PPCRegisterBankInfo &RBI);
48 const PPCRegisterBankInfo &RBI; member in __anon83597b350111::PPCInstructionSelector
67 const PPCRegisterBankInfo &RBI) in PPCInstructionSelector() argument
69 TRI(*STI.getRegisterInfo()), RBI(RBI), in PPCInstructionSelector()
89 const PPCRegisterBankInfo &RBI) { in createPPCInstructionSelector() argument
90 return new PPCInstructionSelector(TM, Subtarget, RBI); in createPPCInstructionSelector()
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| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMInstructionSelector.cpp | 36 const ARMRegisterBankInfo &RBI);
76 const ARMRegisterBankInfo &RBI; member in __anon9959c9ef0111::ARMInstructionSelector
162 const ARMRegisterBankInfo &RBI) { in createARMInstructionSelector() argument
163 return new ARMInstructionSelector(TM, STI, RBI); in createARMInstructionSelector()
173 const ARMRegisterBankInfo &RBI) in ARMInstructionSelector() argument
175 TRI(*STI.getRegisterInfo()), TM(TM), RBI(RBI), STI(STI), Opcodes(STI), in ARMInstructionSelector()
188 const RegisterBankInfo &RBI) { in guessRegClass() argument
189 const RegisterBank *RegBank = RBI.getRegBank(Reg, MRI, TRI); in guessRegClass()
213 const RegisterBankInfo &RBI) { in selectCopy() argument
218 const TargetRegisterClass *RC = guessRegClass(DstReg, MRI, TRI, RBI); in selectCopy()
[all …]
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| /external/llvm-project/llvm/lib/Target/RISCV/ |
| D | RISCVInstructionSelector.cpp | 36 const RISCVRegisterBankInfo &RBI);
47 const RISCVRegisterBankInfo &RBI; member in __anonec89487d0111::RISCVInstructionSelector
71 const RISCVRegisterBankInfo &RBI) in RISCVInstructionSelector() argument
73 TRI(*STI.getRegisterInfo()), RBI(RBI), in RISCVInstructionSelector()
101 RISCVRegisterBankInfo &RBI) { in createRISCVInstructionSelector() argument
102 return new RISCVInstructionSelector(TM, Subtarget, RBI); in createRISCVInstructionSelector()
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| D | RISCVSubtarget.cpp | 63 auto *RBI = new RISCVRegisterBankInfo(*getRegisterInfo()); in RISCVSubtarget() local
64 RegBankInfo.reset(RBI); in RISCVSubtarget()
66 *static_cast<const RISCVTargetMachine *>(&TM), *this, *RBI)); in RISCVSubtarget()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
| D | RISCVInstructionSelector.cpp | 35 const RISCVRegisterBankInfo &RBI);
46 const RISCVRegisterBankInfo &RBI; member in __anon46b094710111::RISCVInstructionSelector
70 const RISCVRegisterBankInfo &RBI) in RISCVInstructionSelector() argument
72 TRI(*STI.getRegisterInfo()), RBI(RBI), in RISCVInstructionSelector()
100 RISCVRegisterBankInfo &RBI) { in createRISCVInstructionSelector() argument
101 return new RISCVInstructionSelector(TM, Subtarget, RBI); in createRISCVInstructionSelector()
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| D | RISCVSubtarget.cpp | 59 auto *RBI = new RISCVRegisterBankInfo(*getRegisterInfo()); in RISCVSubtarget() local
60 RegBankInfo.reset(RBI); in RISCVSubtarget()
62 *static_cast<const RISCVTargetMachine *>(&TM), *this, *RBI)); in RISCVSubtarget()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMInstructionSelector.cpp | 36 const ARMRegisterBankInfo &RBI);
76 const ARMRegisterBankInfo &RBI; member in __anon71f13be30111::ARMInstructionSelector
162 const ARMRegisterBankInfo &RBI) { in createARMInstructionSelector() argument
163 return new ARMInstructionSelector(TM, STI, RBI); in createARMInstructionSelector()
175 const ARMRegisterBankInfo &RBI) in ARMInstructionSelector() argument
177 TRI(*STI.getRegisterInfo()), TM(TM), RBI(RBI), STI(STI), Opcodes(STI), in ARMInstructionSelector()
190 const RegisterBankInfo &RBI) { in guessRegClass() argument
191 const RegisterBank *RegBank = RBI.getRegBank(Reg, MRI, TRI); in guessRegClass()
215 const RegisterBankInfo &RBI) { in selectCopy() argument
220 const TargetRegisterClass *RC = guessRegClass(DstReg, MRI, TRI, RBI); in selectCopy()
[all …]
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| /external/llvm-project/llvm/lib/Target/Mips/ |
| D | MipsInstructionSelector.cpp | 36 const MipsRegisterBankInfo &RBI);
63 const MipsRegisterBankInfo &RBI; member in __anon06c298e10111::MipsInstructionSelector
82 const MipsRegisterBankInfo &RBI) in MipsInstructionSelector() argument
84 TRI(*STI.getRegisterInfo()), RBI(RBI), in MipsInstructionSelector()
97 return RBI.getRegBank(Reg, MRI, TRI)->getID() == Mips::GPRBRegBankID; in isRegInGprb()
102 return RBI.getRegBank(Reg, MRI, TRI)->getID() == Mips::FPRBRegBankID; in isRegInFprb()
112 if (!RBI.constrainGenericRegister(DstReg, *RC, MRI)) { in selectCopy()
152 return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI); in materialize32BitImm()
158 return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI); in materialize32BitImm()
165 return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI); in materialize32BitImm()
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64InstructionSelector.cpp | 53 const AArch64RegisterBankInfo &RBI);
294 const AArch64RegisterBankInfo &RBI; member in __anonb1ac26350111::AArch64InstructionSelector
317 const AArch64RegisterBankInfo &RBI) in AArch64InstructionSelector() argument
319 TRI(*STI.getRegisterInfo()), RBI(RBI), in AArch64InstructionSelector()
333 const RegisterBankInfo &RBI, in getRegClassForTypeOnBank() argument
431 const AArch64RegisterBankInfo &RBI, in unsupportedBinOp() argument
457 const RegisterBank *OpBank = RBI.getRegBank(MO.getReg(), MRI, TRI); in unsupportedBinOp()
586 const RegisterBankInfo &RBI) { in isValidCopy() argument
589 const unsigned DstSize = RBI.getSizeInBits(DstReg, MRI, TRI); in isValidCopy()
590 const unsigned SrcSize = RBI.getSizeInBits(SrcReg, MRI, TRI); in isValidCopy()
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsInstructionSelector.cpp | 36 const MipsRegisterBankInfo &RBI);
57 const MipsRegisterBankInfo &RBI; member in __anon62fe57d50111::MipsInstructionSelector
76 const MipsRegisterBankInfo &RBI) in MipsInstructionSelector() argument
78 TRI(*STI.getRegisterInfo()), RBI(RBI), in MipsInstructionSelector()
91 return RBI.getRegBank(Reg, MRI, TRI)->getID() == Mips::GPRBRegBankID; in isRegInGprb()
96 return RBI.getRegBank(Reg, MRI, TRI)->getID() == Mips::FPRBRegBankID; in isRegInFprb()
106 if (!RBI.constrainGenericRegister(DstReg, *RC, MRI)) { in selectCopy()
146 return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI); in materialize32BitImm()
152 return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI); in materialize32BitImm()
159 return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI); in materialize32BitImm()
[all …]
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| /external/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| D | AArch64InstructionSelector.cpp | 59 const AArch64RegisterBankInfo &RBI);
415 const AArch64RegisterBankInfo &RBI; member in __anon128cdb240111::AArch64InstructionSelector
443 const AArch64RegisterBankInfo &RBI) in AArch64InstructionSelector() argument
445 TRI(*STI.getRegisterInfo()), RBI(RBI), in AArch64InstructionSelector()
459 const RegisterBankInfo &RBI, in getRegClassForTypeOnBank() argument
590 const AArch64RegisterBankInfo &RBI, in unsupportedBinOp() argument
616 const RegisterBank *OpBank = RBI.getRegBank(MO.getReg(), MRI, TRI); in unsupportedBinOp()
745 const RegisterBankInfo &RBI) { in isValidCopy() argument
748 const unsigned DstSize = RBI.getSizeInBits(DstReg, MRI, TRI); in isValidCopy()
749 const unsigned SrcSize = RBI.getSizeInBits(SrcReg, MRI, TRI); in isValidCopy()
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86InstructionSelector.cpp | 62 const X86RegisterBankInfo &RBI);
135 const X86RegisterBankInfo &RBI; member in __anonee8a962f0111::X86InstructionSelector
154 const X86RegisterBankInfo &RBI) in X86InstructionSelector() argument
156 TRI(*STI.getRegisterInfo()), RBI(RBI), in X86InstructionSelector()
199 const RegisterBank &RegBank = *RBI.getRegBank(Reg, MRI, TRI); in getRegClass()
234 const unsigned DstSize = RBI.getSizeInBits(DstReg, MRI, TRI); in selectCopy()
235 const RegisterBank &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI); in selectCopy()
238 const unsigned SrcSize = RBI.getSizeInBits(SrcReg, MRI, TRI); in selectCopy()
239 const RegisterBank &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI); in selectCopy()
274 DstSize <= RBI.getSizeInBits(SrcReg, MRI, TRI))) && in selectCopy()
[all …]
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| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86InstructionSelector.cpp | 63 const X86RegisterBankInfo &RBI);
136 const X86RegisterBankInfo &RBI; member in __anon15f3243b0111::X86InstructionSelector
155 const X86RegisterBankInfo &RBI) in X86InstructionSelector() argument
157 TRI(*STI.getRegisterInfo()), RBI(RBI), in X86InstructionSelector()
200 const RegisterBank &RegBank = *RBI.getRegBank(Reg, MRI, TRI); in getRegClass()
235 const unsigned DstSize = RBI.getSizeInBits(DstReg, MRI, TRI); in selectCopy()
236 const RegisterBank &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI); in selectCopy()
239 const unsigned SrcSize = RBI.getSizeInBits(SrcReg, MRI, TRI); in selectCopy()
240 const RegisterBank &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI); in selectCopy()
275 DstSize <= RBI.getSizeInBits(SrcReg, MRI, TRI))) && in selectCopy()
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUInstructionSelector.cpp | 50 const GCNSubtarget &STI, const AMDGPURegisterBankInfo &RBI, in AMDGPUInstructionSelector() argument
53 TRI(*STI.getRegisterInfo()), RBI(RBI), TM(TM), in AMDGPUInstructionSelector()
107 return RBI.constrainGenericRegister(DstReg, *RC, *MRI); in selectCOPY()
112 if (!RBI.constrainGenericRegister(DstReg, *TRI.getBoolRC(), *MRI)) in selectCOPY()
141 if (RC && !RBI.constrainGenericRegister(DstReg, *RC, *MRI)) in selectCOPY()
153 if (SrcRC && !RBI.constrainGenericRegister(SrcReg, *SrcRC, *MRI)) in selectCOPY()
168 RBI.constrainGenericRegister(MO.getReg(), *RC, *MRI); in selectCOPY()
200 return RBI.constrainGenericRegister(DefReg, *DefRC, *MRI); in selectPHI()
256 unsigned Size = RBI.getSizeInBits(DstReg, *MRI, TRI); in selectG_AND_OR_XOR()
258 const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI); in selectG_AND_OR_XOR()
[all …]
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUInstructionSelector.cpp | 56 const GCNSubtarget &STI, const AMDGPURegisterBankInfo &RBI, in AMDGPUInstructionSelector() argument
59 TRI(*STI.getRegisterInfo()), RBI(RBI), TM(TM), in AMDGPUInstructionSelector()
119 return RBI.constrainGenericRegister(Dst.getReg(), *DstRC, *MRI) && in constrainCopyLikeIntrin()
120 RBI.constrainGenericRegister(Src.getReg(), *SrcRC, *MRI); in constrainCopyLikeIntrin()
139 return RBI.constrainGenericRegister(DstReg, *RC, *MRI); in selectCOPY()
144 if (!RBI.constrainGenericRegister(DstReg, *TRI.getBoolRC(), *MRI)) in selectCOPY()
173 if (RC && !RBI.constrainGenericRegister(DstReg, *RC, *MRI)) in selectCOPY()
187 RBI.constrainGenericRegister(MO.getReg(), *RC, *MRI); in selectCOPY()
227 return RBI.constrainGenericRegister(DefReg, *DefRC, *MRI); in selectPHI()
280 unsigned Size = RBI.getSizeInBits(DstReg, *MRI, TRI); in selectG_AND_OR_XOR()
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | Utils.h | 47 const RegisterBankInfo &RBI, unsigned Reg,
61 const RegisterBankInfo &RBI,
79 const RegisterBankInfo &RBI,
95 const RegisterBankInfo &RBI);
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| /external/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | Utils.h | 49 const RegisterBankInfo &RBI, Register Reg,
63 const RegisterBankInfo &RBI,
81 const RegisterBankInfo &RBI,
97 const RegisterBankInfo &RBI);
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/Scalar/ |
| D | MergedLoadStoreMotion.cpp | 307 for (BasicBlock::reverse_iterator RBI = Pred0->rbegin(), RBE = Pred0->rend(); in mergeStores() local
308 RBI != RBE;) { in mergeStores()
310 Instruction *I = &*RBI; in mergeStores()
311 ++RBI; in mergeStores()
339 RBI = Pred0->rbegin(); in mergeStores()
341 LLVM_DEBUG(dbgs() << "Search again\n"; Instruction *I = &*RBI; I->dump()); in mergeStores()
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| /external/llvm-project/llvm/lib/Transforms/Scalar/ |
| D | MergedLoadStoreMotion.cpp | 307 for (BasicBlock::reverse_iterator RBI = Pred0->rbegin(), RBE = Pred0->rend(); in mergeStores() local
308 RBI != RBE;) { in mergeStores()
310 Instruction *I = &*RBI; in mergeStores()
311 ++RBI; in mergeStores()
339 RBI = Pred0->rbegin(); in mergeStores()
341 LLVM_DEBUG(dbgs() << "Search again\n"; Instruction *I = &*RBI; I->dump()); in mergeStores()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | Utils.cpp | 32 const RegisterBankInfo &RBI, unsigned Reg, in constrainRegToClass() argument
34 if (!RBI.constrainGenericRegister(Reg, RegClass, MRI)) in constrainRegToClass()
43 const RegisterBankInfo &RBI, MachineInstr &InsertPt, in constrainOperandRegClass() argument
50 unsigned ConstrainedReg = constrainRegToClass(MRI, TII, RBI, Reg, RegClass); in constrainOperandRegClass()
73 const RegisterBankInfo &RBI, MachineInstr &InsertPt, const MCInstrDesc &II, in constrainOperandRegClass() argument
107 return constrainOperandRegClass(MF, TRI, MRI, TII, RBI, InsertPt, *RegClass, in constrainOperandRegClass()
114 const RegisterBankInfo &RBI) { in constrainSelectedInstRegOperands() argument
144 MO.setReg(constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, I.getDesc(), in constrainSelectedInstRegOperands()
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| D | RegBankSelect.cpp | 83 RBI = MF.getSubtarget().getRegBankInfo(); in init()
84 assert(RBI && "Cannot work without RegisterBankInfo"); in init()
121 const RegisterBank *CurRegBank = RBI->getRegBank(Reg, *MRI, *TRI); in assignmentMatch()
244 const RegisterBank *CurRegBank = RBI->getRegBank(MO.getReg(), *MRI, *TRI); in getRepairCost()
260 return RBI->getBreakDownCost(ValMapping, CurRegBank); in getRepairCost()
279 unsigned Cost = RBI->copyCost(*DesiredRegBank, *CurRegBank, in getRepairCost()
280 RBI->getSizeInBits(MO.getReg(), *MRI, *TRI)); in getRepairCost()
618 RBI->applyMapping(OpdMapper); in applyMapping()
630 BestMapping = &RBI->getInstrMapping(MI); in assignInstr()
637 RBI->getInstrPossibleMappings(MI); in assignInstr()
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| D | InstructionSelector.cpp | 39 const RegisterBankInfo &RBI) const { in constrainOperandRegToRegClass()
44 return constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, RC, in constrainOperandRegToRegClass()
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| /external/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| D | RegBankSelect.cpp | 83 RBI = MF.getSubtarget().getRegBankInfo(); in init()
84 assert(RBI && "Cannot work without RegisterBankInfo"); in init()
121 const RegisterBank *CurRegBank = RBI->getRegBank(Reg, *MRI, *TRI); in assignmentMatch()
244 const RegisterBank *CurRegBank = RBI->getRegBank(MO.getReg(), *MRI, *TRI); in getRepairCost()
260 return RBI->getBreakDownCost(ValMapping, CurRegBank); in getRepairCost()
279 unsigned Cost = RBI->copyCost(*DesiredRegBank, *CurRegBank, in getRepairCost()
280 RBI->getSizeInBits(MO.getReg(), *MRI, *TRI)); in getRepairCost()
618 RBI->applyMapping(OpdMapper); in applyMapping()
630 BestMapping = &RBI->getInstrMapping(MI); in assignInstr()
637 RBI->getInstrPossibleMappings(MI); in assignInstr()
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| D | InstructionSelector.cpp | 39 const RegisterBankInfo &RBI) const { in constrainOperandRegToRegClass()
44 return constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, RC, in constrainOperandRegToRegClass()
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| /external/llvm/lib/CodeGen/GlobalISel/ |
| D | RegBankSelect.cpp | 48 : MachineFunctionPass(ID), RBI(nullptr), MRI(nullptr), TRI(nullptr), in RegBankSelect()
59 RBI = MF.getSubtarget().getRegBankInfo(); in init()
60 assert(RBI && "Cannot work without RegisterBankInfo"); in init()
93 const RegisterBank *CurRegBank = RBI->getRegBank(Reg, *MRI, *TRI); in assignmentMatch()
161 const RegisterBank *CurRegBank = RBI->getRegBank(MO.getReg(), *MRI, *TRI); in getRepairCost()
193 RBI->copyCost(*DesiredRegBrank, *CurRegBank, in getRepairCost()
506 RBI->applyMapping(OpdMapper); in applyMapping()
516 BestMapping = RBI->getInstrMapping(MI); in assignInstr()
523 RBI->getInstrPossibleMappings(MI); in assignInstr()
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