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Searched refs:RES (Results 1 – 25 of 319) sorted by relevance

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/external/tcpdump/tests/
D	lldp-infinite-loop-1.out	`29 RES: 0 31 Priority: 0, RES: 0, Sel: 0, Protocol ID: 0 32 Priority: 0, RES: 0, Sel: 0, Protocol ID: 0 33 Priority: 0, RES: 0, Sel: 0, Protocol ID: 128 34 Priority: 0, RES: 1, Sel: 4, Protocol ID: 3072 35 Priority: 0, RES: 0, Sel: 0, Protocol ID: 0 36 Priority: 0, RES: 0, Sel: 0, Protocol ID: 0 37 Priority: 4, RES: 0, Sel: 0, Protocol ID: 32962 38 Priority: 0, RES: 0, Sel: 0, Protocol ID: 0 39 Priority: 0, RES: 0, Sel: 0, Protocol ID: 0 [all …]`
/external/llvm-project/llvm/test/tools/gold/X86/
D	comdat.ll	`6 ; RUN: FileCheck --check-prefix=RES %s < %t3.o.resolution.txt 35 ; RES: 1.o,f1,plx{{$}} 36 ; RES: 1.o,v1,px{{$}} 37 ; RES: 1.o,r11,px{{$}} 38 ; RES: 1.o,r12,px{{$}} 39 ; RES: 1.o,a11,px{{$}} 40 ; RES: 1.o,a12,px{{$}} 41 ; RES: 1.o,a13,px{{$}} 42 ; RES: 1.o,a14,px{{$}} 43 ; RES: 1.o,a15,px{{$}} [all …]`
D	emit-llvm.ll	`11 ; RUN: FileCheck --check-prefix=RES %s < %t3.o.resolution.txt 100 ; RES: .o,f1,pl{{$}} 101 ; RES: .o,f2,pl{{$}} 102 ; RES: .o,f3,px{{$}} 103 ; RES: .o,f4,p{{$}} 104 ; RES: .o,f5,px{{$}} 105 ; RES: .o,f6,p{{$}} 106 ; RES: .o,f7,px{{$}} 107 ; RES: .o,f8,px{{$}} 108 ; RES: .o,g1,px{{$}} [all …]`
/external/eigen/blas/fortran/
D	complexdots.f	`4 COMPLEX RES local 7 CALL CDOTCW(N,CX,INCX,CY,INCY,RES) 8 CDOTC = RES 15 COMPLEX RES local 18 CALL CDOTUW(N,CX,INCX,CY,INCY,RES) 19 CDOTU = RES 26 DOUBLE COMPLEX RES local 29 CALL ZDOTCW(N,CX,INCX,CY,INCY,RES) 30 ZDOTC = RES 37 DOUBLE COMPLEX RES local [all …]`
/external/llvm-project/llvm/test/Instrumentation/PoisonChecking/
D	basic-flag-validation.ll	`8 ; CHECK-NEXT: [[RES:%.]] = add i32 [[A:%.]], [[B:%.]] 9 ; CHECK-NEXT: ret i32 [[RES]] 19 ; CHECK-NEXT: [[RES:%.]] = add nsw i32 [[A]], [[B]] 22 ; CHECK-NEXT: ret i32 [[RES]] 32 ; CHECK-NEXT: [[RES:%.]] = add nuw i32 [[A]], [[B]] 35 ; CHECK-NEXT: ret i32 [[RES]] 48 ; CHECK-NEXT: [[RES:%.]] = add nuw nsw i32 [[A]], [[B]] 51 ; CHECK-NEXT: ret i32 [[RES]] 59 ; CHECK-NEXT: [[RES:%.]] = sub i32 [[A:%.]], [[B:%.*]] 60 ; CHECK-NEXT: ret i32 [[RES]] [all …]`
/external/llvm-project/llvm/test/CodeGen/AArch64/
D	sve-fixed-length-splat-vector.ll	49 ; CHECK-DAG: mov [[RES:z[0-9]+]].b, w0 51 ; CHECK-NEXT: st1b { [[RES]].b }, [[PG]], [x1] 61 ; VBITS_GE_512-DAG: mov [[RES:z[0-9]+]].b, w0 63 ; VBITS_GE_512-NEXT: st1b { [[RES]].b }, [[PG]], [x1] 67 ; VBITS_EQ_256-DAG: mov [[RES:z[0-9]+]].b, w0 70 ; VBITS_EQ_256-DAG: st1b { [[RES]].b }, [[PG]], [x1] 71 ; VBITS_EQ_256-DAG: st1b { [[RES]].b }, [[PG]], [x1, x[[OFFSET_HI]] 81 ; VBITS_GE_1024-DAG: mov [[RES:z[0-9]+]].b, w0 83 ; VBITS_GE_1024-NEXT: st1b { [[RES]].b }, [[PG]], [x1] 93 ; VBITS_GE_2048-DAG: mov [[RES:z[0-9]+]].b, w0 [all …]
D	sve-fixed-length-fp-rounding.ll	49 ; CHECK-NEXT: frintp [[RES:z[0-9]+]].h, [[PG]]/m, [[OP]].h 50 ; CHECK-NEXT: st1h { [[RES]].h }, [[PG]], [x0] 62 ; VBITS_GE_512-NEXT: frintp [[RES:z[0-9]+]].h, [[PG]]/m, [[OP]].h 63 ; VBITS_GE_512-NEXT: st1h { [[RES]].h }, [[PG]], [x0] 86 ; VBITS_GE_1024-NEXT: frintp [[RES:z[0-9]+]].h, [[PG]]/m, [[OP]].h 87 ; VBITS_GE_1024-NEXT: st1h { [[RES]].h }, [[PG]], [x0] 99 ; VBITS_GE_2048-NEXT: frintp [[RES:z[0-9]+]].h, [[PG]]/m, [[OP]].h 100 ; VBITS_GE_2048-NEXT: st1h { [[RES]].h }, [[PG]], [x0] 130 ; CHECK-NEXT: frintp [[RES:z[0-9]+]].s, [[PG]]/m, [[OP]].s 131 ; CHECK-NEXT: st1w { [[RES]].s }, [[PG]], [x0] [all …]
D	sve-fixed-length-int-log.ll	55 ; CHECK: and [[RES:z[0-9]+]].d, [[OP1]].d, [[OP2]].d 56 ; CHECK: st1b { [[RES]].b }, [[PG]], [x0] 70 ; CHECK-DAG: and [[RES:z[0-9]+]].d, [[OP1]].d, [[OP2]].d 71 ; CHECK-DAG: st1b { [[RES]].b }, [[PG]], [x0] 90 ; CHECK-DAG: and [[RES:z[0-9]+]].d, [[OP1]].d, [[OP2]].d 91 ; CHECK-DAG: st1b { [[RES]].b }, [[PG]], [x0] 120 ; CHECK-DAG: and [[RES:z[0-9]+]].d, [[OP1]].d, [[OP2]].d 121 ; CHECK-DAG: st1b { [[RES]].b }, [[PG]], [x0] 188 ; CHECK: and [[RES:z[0-9]+]].d, [[OP1]].d, [[OP2]].d 189 ; CHECK: st1h { [[RES]].h }, [[PG]], [x0] [all …]
D	sve-fixed-length-fp-arith.ll	55 ; CHECK: fadd [[RES:z[0-9]+]].h, [[PG]]/m, [[OP1]].h, [[OP2]].h 56 ; CHECK: st1h { [[RES]].h }, [[PG]], [x0] 70 ; CHECK-DAG: fadd [[RES:z[0-9]+]].h, [[PG]]/m, [[OP1]].h, [[OP2]].h 71 ; CHECK-DAG: st1h { [[RES]].h }, [[PG]], [x0] 91 ; CHECK-DAG: fadd [[RES:z[0-9]+]].h, [[PG]]/m, [[OP1]].h, [[OP2]].h 92 ; CHECK-DAG: st1h { [[RES]].h }, [[PG]], [x0] 126 ; CHECK: fadd [[RES:z[0-9]+]].h, [[PG]]/m, [[OP1]].h, [[OP2]].h 127 ; CHECK: st1h { [[RES]].h }, [[PG]], [x0] 159 ; CHECK: fadd [[RES:z[0-9]+]].s, [[PG]]/m, [[OP1]].s, [[OP2]].s 160 ; CHECK: st1w { [[RES]].s }, [[PG]], [x0] [all …]
D	sve-fixed-length-int-arith.ll	55 ; CHECK: add [[RES:z[0-9]+]].b, [[PG]]/m, [[OP1]].b, [[OP2]].b 56 ; CHECK: st1b { [[RES]].b }, [[PG]], [x0] 70 ; CHECK-DAG: add [[RES:z[0-9]+]].b, [[PG]]/m, [[OP1]].b, [[OP2]].b 71 ; CHECK-DAG: st1b { [[RES]].b }, [[PG]], [x0] 90 ; CHECK-DAG: add [[RES:z[0-9]+]].b, [[PG]]/m, [[OP1]].b, [[OP2]].b 91 ; CHECK-DAG: st1b { [[RES]].b }, [[PG]], [x0] 120 ; CHECK-DAG: add [[RES:z[0-9]+]].b, [[PG]]/m, [[OP1]].b, [[OP2]].b 121 ; CHECK-DAG: st1b { [[RES]].b }, [[PG]], [x0] 188 ; CHECK: add [[RES:z[0-9]+]].h, [[PG]]/m, [[OP1]].h, [[OP2]].h 189 ; CHECK: st1h { [[RES]].h }, [[PG]], [x0] [all …]
/external/llvm-project/llvm/test/Transforms/InstCombine/
D	pow_fp_int.ll	9 ; CHECK-NEXT: [[RES:%.]] = fpext float [[TMP1]] to double 10 ; CHECK-NEXT: ret double [[RES]] 22 ; CHECK-NEXT: [[RES:%.]] = fpext float [[TMP2]] to double 23 ; CHECK-NEXT: ret double [[RES]] 55 ; CHECK-NEXT: [[RES:%.]] = fpext float [[LDEXPF]] to double 56 ; CHECK-NEXT: ret double [[RES]] 69 ; CHECK-NEXT: [[RES:%.]] = fpext float [[EXP2]] to double 70 ; CHECK-NEXT: ret double [[RES]] 82 ; CHECK-NEXT: [[RES:%.*]] = fpext float [[LDEXPF]] to double 83 ; CHECK-NEXT: ret double [[RES]] [all …]
D	strict-sub-underflow-check-to-comparison-of-sub-operands.ll	`14 ; CHECK-NEXT: [[RES:%.]] = icmp uge i8 [[BASE]], [[OFFSET]] 15 ; CHECK-NEXT: ret i1 [[RES]] 31 ; CHECK-NEXT: [[RES:%.]] = icmp ult i8 [[BASE]], [[OFFSET]] 32 ; CHECK-NEXT: ret i1 [[RES]] 49 ; CHECK-NEXT: [[RES:%.]] = icmp uge i8 [[BASE]], [[OFFSET]] 50 ; CHECK-NEXT: ret i1 [[RES]] 68 ; CHECK-NEXT: [[RES:%.]] = icmp ult i8 [[BASE]], [[OFFSET]] 69 ; CHECK-NEXT: ret i1 [[RES]] 86 ; CHECK-NEXT: [[RES:%.*]] = icmp ult i8 [[ADJUSTED]], [[BASE]] 87 ; CHECK-NEXT: ret i1 [[RES]] [all …]`
/external/llvm-project/llvm/test/CodeGen/Mips/msa/
D	elm_copy.ll	31 ; MIPS32-DAG: lw [[RES:\$[0-9]+]], %got(llvm_mips_copy_s_b_RES) 32 ; MIPS64-DAG: ld [[RES:\$[0-9]+]], %got_disp(llvm_mips_copy_s_b_RES) 33 ; MIPS-ANY-DAG: sw [[RD]], 0([[RES]]) 54 ; MIPS32-DAG: lw [[RES:\$[0-9]+]], %got(llvm_mips_copy_s_h_RES) 55 ; MIPS64-DAG: ld [[RES:\$[0-9]+]], %got_disp(llvm_mips_copy_s_h_RES) 56 ; MIPS-ANY-DAG: sw [[RD]], 0([[RES]]) 77 ; MIPS32-DAG: lw [[RES:\$[0-9]+]], %got(llvm_mips_copy_s_w_RES) 78 ; MIPS64-DAG: ld [[RES:\$[0-9]+]], %got_disp(llvm_mips_copy_s_w_RES) 79 ; MIPS-ANY-DAG: sw [[RD]], 0([[RES]]) 103 ; MIPS32-DAG: lw [[RES:\$[0-9]+]], %got(llvm_mips_copy_s_d_RES) [all …]
/external/llvm/test/CodeGen/Mips/msa/
D	elm_copy.ll	31 ; MIPS32-DAG: lw [[RES:\$[0-9]+]], %got(llvm_mips_copy_s_b_RES) 32 ; MIPS64-DAG: ld [[RES:\$[0-9]+]], %got_disp(llvm_mips_copy_s_b_RES) 33 ; MIPS-ANY-DAG: sw [[RD]], 0([[RES]]) 54 ; MIPS32-DAG: lw [[RES:\$[0-9]+]], %got(llvm_mips_copy_s_h_RES) 55 ; MIPS64-DAG: ld [[RES:\$[0-9]+]], %got_disp(llvm_mips_copy_s_h_RES) 56 ; MIPS-ANY-DAG: sw [[RD]], 0([[RES]]) 77 ; MIPS32-DAG: lw [[RES:\$[0-9]+]], %got(llvm_mips_copy_s_w_RES) 78 ; MIPS64-DAG: ld [[RES:\$[0-9]+]], %got_disp(llvm_mips_copy_s_w_RES) 79 ; MIPS-ANY-DAG: sw [[RD]], 0([[RES]]) 103 ; MIPS32-DAG: lw [[RES:\$[0-9]+]], %got(llvm_mips_copy_s_d_RES) [all …]
/external/llvm-project/llvm/test/Transforms/TypePromotion/ARM/
D	wrapping.ll	`9 ; CHECK-NEXT: [[RES:%.]] = select i1 [[CMP]], i16 2, i16 5 10 ; CHECK-NEXT: ret i16 [[RES]] 24 ; CHECK-NEXT: [[RES:%.]] = select i1 [[CMP]], i16 2, i16 5 25 ; CHECK-NEXT: ret i16 [[RES]] 39 ; CHECK-NEXT: [[RES:%.]] = select i1 [[CMP]], i16 2, i16 5 40 ; CHECK-NEXT: ret i16 [[RES]] 54 ; CHECK-NEXT: [[RES:%.]] = select i1 [[CMP]], i16 2, i16 5 55 ; CHECK-NEXT: ret i16 [[RES]] 68 ; CHECK-NEXT: [[RES:%.*]] = select i1 [[CMP]], i32 8, i32 16 69 ; CHECK-NEXT: ret i32 [[RES]] [all …]`
D	icmps.ll	`9 ; CHECK-NEXT: [[RES:%.]] = select i1 [[CMP]], i32 35, i32 47 10 ; CHECK-NEXT: ret i32 [[RES]] 24 ; CHECK-NEXT: [[RES:%.]] = select i1 [[CMP]], i32 35, i32 47 25 ; CHECK-NEXT: ret i32 [[RES]] 39 ; CHECK-NEXT: [[RES:%.]] = select i1 [[CMP]], i32 35, i32 47 40 ; CHECK-NEXT: ret i32 [[RES]] 54 ; CHECK-NEXT: [[RES:%.]] = select i1 [[CMP]], i32 35, i32 47 55 ; CHECK-NEXT: ret i32 [[RES]] 70 ; CHECK-NEXT: [[RES:%.*]] = select i1 [[CMP]], i32 35, i32 47 71 ; CHECK-NEXT: ret i32 [[RES]] [all …]`
/external/llvm-project/llvm/test/LTO/Resolution/X86/
D	alias-alias.ll	`5 ; RUN: FileCheck --check-prefix=RES %s < %t3.o.resolution.txt 14 ; RES: 1.o{{$}} 15 ; RES-NEXT: {{^}}-r={{.}}1.o,c,p{{$}} 16 ; RES-NEXT: {{^}}-r={{.}}1.o,a,p{{$}} 17 ; RES-NEXT: {{^}}-r={{.}}1.o,b,{{$}} 18 ; RES-NEXT: 2.o{{$}} 19 ; RES-NEXT: {{^}}-r={{.}}2.o,a,{{$}} 20 ; RES-NEXT: {{^}}-r={{.*}}2.o,d,px{{$}}`
D	alias.ll	`5 ; RUN: FileCheck --check-prefix=RES %s < %t3.o.resolution.txt 12 ; RES: 2.o{{$}} 13 ; RES: {{^}}-r={{.}}2.o,a,px{{$}} 14 ; RES: 1.o{{$}} 15 ; RES: {{^}}-r={{.}}1.o,b,px{{$}} 16 ; RES: {{^}}-r={{.*}}1.o,a,{{$}}`
/external/llvm/test/CodeGen/Mips/Fast-ISel/
D	logopm.ll	`42 ; CHECK: andi $[[RES:[0-9]+]], $[[RES1]], 1 43 ; CHECK: sb $[[RES]], 0($[[UB_ADDR]]) 63 ; CHECK: andi $[[RES:[0-9]+]], $[[RES1]], 1 64 ; CHECK: sb $[[RES]], 0($[[UB_ADDR]]) 87 ; CHECK: andi $[[RES:[0-9]+]], $[[RES1]], 1 88 ; CHECK: sb $[[RES]], 0($[[UB_ADDR]]) 113 ; CHECK: andi $[[RES:[0-9]+]], $[[RES1]], 1 114 ; CHECK: sb $[[RES]], 0($[[UB_ADDR]]) 133 ; CHECK: andi $[[RES:[0-9]+]], $[[UB1]], 1 134 ; CHECK: sb $[[RES]], 0($[[UB_ADDR]]) [all …]`
D	shftopm.ll	`28 ; CHECK: sllv $[[RES:[0-9]+]], $[[S1]], $[[S2]] 29 ; CHECK: sh $[[RES]], 0($[[S3_ADDR]]) 45 ; CHECK: sll $[[RES:[0-9]+]], $[[S1]], 5 46 ; CHECK: sh $[[RES]], 0($[[S3_ADDR]]) 66 ; CHECK: srlv $[[RES:[0-9]+]], $[[US1]], $[[US2]] 67 ; CHECK: sh $[[RES]], 0($[[S3_ADDR]]) 82 ; CHECK: srl $[[RES:[0-9]+]], $[[US1]], 4 83 ; CHECK: sh $[[RES]], 0($[[S3_ADDR]]) 102 ; CHECK: srav $[[RES:[0-9]+]], $[[S1]], $[[S2]] 103 ; CHECK: sh $[[RES]], 0($[[S3_ADDR]]) [all …]`
/external/llvm-project/llvm/test/CodeGen/Mips/Fast-ISel/
D	logopm.ll	`42 ; CHECK: andi $[[RES:[0-9]+]], $[[RES1]], 1 43 ; CHECK: sb $[[RES]], 0($[[UB_ADDR]]) 63 ; CHECK: andi $[[RES:[0-9]+]], $[[RES1]], 1 64 ; CHECK: sb $[[RES]], 0($[[UB_ADDR]]) 87 ; CHECK: andi $[[RES:[0-9]+]], $[[RES1]], 1 88 ; CHECK: sb $[[RES]], 0($[[UB_ADDR]]) 113 ; CHECK: andi $[[RES:[0-9]+]], $[[RES1]], 1 114 ; CHECK: sb $[[RES]], 0($[[UB_ADDR]]) 133 ; CHECK: andi $[[RES:[0-9]+]], $[[UB1]], 1 134 ; CHECK: sb $[[RES]], 0($[[UB_ADDR]]) [all …]`
D	shftopm.ll	`28 ; CHECK: sllv $[[RES:[0-9]+]], $[[S1]], $[[S2]] 29 ; CHECK: sh $[[RES]], 0($[[S3_ADDR]]) 45 ; CHECK: sll $[[RES:[0-9]+]], $[[S1]], 5 46 ; CHECK: sh $[[RES]], 0($[[S3_ADDR]]) 66 ; CHECK: srlv $[[RES:[0-9]+]], $[[US1]], $[[US2]] 67 ; CHECK: sh $[[RES]], 0($[[S3_ADDR]]) 82 ; CHECK: srl $[[RES:[0-9]+]], $[[US1]], 4 83 ; CHECK: sh $[[RES]], 0($[[S3_ADDR]]) 102 ; CHECK: srav $[[RES:[0-9]+]], $[[S1]], $[[S2]] 103 ; CHECK: sh $[[RES]], 0($[[S3_ADDR]]) [all …]`
/external/selinux/scripts/
D	Lindent	3 RES=`indent --version` 4 V1=`echo $RES \| cut -d' ' -f3 \| cut -d'.' -f1` 5 V2=`echo $RES \| cut -d' ' -f3 \| cut -d'.' -f2` 6 V3=`echo $RES \| cut -d' ' -f3 \| cut -d'.' -f3`
/external/llvm/test/CodeGen/ARM/
D	vector-promotion.ll	128 ; IR-NORMAL-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = udiv i32 [[EXTRACT]], 7 131 ; IR-STRESS-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = extractelement <2 x i32> [[DIV]], i32 1 133 ; IR-BOTH-NEXT: store i32 [[RES]], i32* %dest 147 ; IR-NORMAL-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = urem i32 [[EXTRACT]], 7 150 ; IR-STRESS-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = extractelement <2 x i32> [[DIV]], i32 1 152 ; IR-BOTH-NEXT: store i32 [[RES]], i32* %dest 166 ; IR-NORMAL-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = sdiv i32 [[EXTRACT]], 7 169 ; IR-STRESS-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = extractelement <2 x i32> [[DIV]], i32 1 171 ; IR-BOTH-NEXT: store i32 [[RES]], i32* %dest 185 ; IR-NORMAL-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = srem i32 [[EXTRACT]], 7 [all …]
/external/llvm-project/llvm/test/CodeGen/ARM/
D	vector-promotion.ll	128 ; IR-NORMAL-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = udiv i32 [[EXTRACT]], 7 131 ; IR-STRESS-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = extractelement <2 x i32> [[DIV]], i32 1 133 ; IR-BOTH-NEXT: store i32 [[RES]], i32* %dest 147 ; IR-NORMAL-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = urem i32 [[EXTRACT]], 7 150 ; IR-STRESS-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = extractelement <2 x i32> [[DIV]], i32 1 152 ; IR-BOTH-NEXT: store i32 [[RES]], i32* %dest 166 ; IR-NORMAL-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = sdiv i32 [[EXTRACT]], 7 169 ; IR-STRESS-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = extractelement <2 x i32> [[DIV]], i32 1 171 ; IR-BOTH-NEXT: store i32 [[RES]], i32* %dest 185 ; IR-NORMAL-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = srem i32 [[EXTRACT]], 7 [all …]

12 3 4 5 6 7 8 9 10 >>...13

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