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Searched refs:Requires (Results 1 – 25 of 794) sorted by relevance

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/external/llvm-project/llvm/lib/Target/Hexagon/
DHexagonDepMapAsm2Intrin.td15 (C2_tfrpr (C2_cmpeq IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>;
17 (C2_tfrpr (C2_cmpgt IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>;
19 (C2_tfrpr (C2_cmpgtu IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>;
21 (C2_tfrpr (C2_cmpeqp DoubleRegs:$src1, DoubleRegs:$src2))>, Requires<[HasV5]>;
23 (C2_tfrpr (C2_cmpgtp DoubleRegs:$src1, DoubleRegs:$src2))>, Requires<[HasV5]>;
25 (C2_tfrpr (C2_cmpgtup DoubleRegs:$src1, DoubleRegs:$src2))>, Requires<[HasV5]>;
27 (A4_rcmpeqi IntRegs:$src1, s32_0ImmPred_timm:$src2)>, Requires<[HasV5]>;
29 (A4_rcmpneqi IntRegs:$src1, s32_0ImmPred_timm:$src2)>, Requires<[HasV5]>;
31 (A4_rcmpeq IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;
33 (A4_rcmpneq IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;
[all …]
DHexagonMapAsm2IntrinV65.gen.td9 …c1, DoubleRegs:$src2), (A6_vcmpbeq_notany DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV65]>;
10 …:$src3), (V6_vasruwuhsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV65, UseHVX]>;
11 …:$src3), (V6_vasruwuhsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV65, UseHVX]>;
12 …:$src3), (V6_vasruhubsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV65, UseHVX]>;
13 …:$src3), (V6_vasruhubsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV65, UseHVX]>;
14 …rc3), (V6_vasruhubrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV65, UseHVX]>;
15 …rc3), (V6_vasruhubrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV65, UseHVX]>;
16 def: Pat<(int_hexagon_V6_vabsb HvxVR:$src1), (V6_vabsb HvxVR:$src1)>, Requires<[HasV65, UseHVX]>;
17 def: Pat<(int_hexagon_V6_vabsb_128B HvxVR:$src1), (V6_vabsb HvxVR:$src1)>, Requires<[HasV65, UseHVX…
18 def: Pat<(int_hexagon_V6_vabsb_sat HvxVR:$src1), (V6_vabsb_sat HvxVR:$src1)>, Requires<[HasV65, Use…
[all …]
DHexagonDepMappings.td156 …= vcmp.eq($Vu32.ub,$Vv32.ub)", (V6_veqb HvxQR:$Qd4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
157 …mp.eq($Vu32.ub,$Vv32.ub)", (V6_veqb_and HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
158 …cmp.eq($Vu32.ub,$Vv32.ub)", (V6_veqb_or HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
159 …mp.eq($Vu32.ub,$Vv32.ub)", (V6_veqb_xor HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
160 …= vcmp.eq($Vu32.uh,$Vv32.uh)", (V6_veqh HvxQR:$Qd4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
161 …mp.eq($Vu32.uh,$Vv32.uh)", (V6_veqh_and HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
162 …cmp.eq($Vu32.uh,$Vv32.uh)", (V6_veqh_or HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
163 …mp.eq($Vu32.uh,$Vv32.uh)", (V6_veqh_xor HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
164 …= vcmp.eq($Vu32.uw,$Vv32.uw)", (V6_veqw HvxQR:$Qd4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
165 …mp.eq($Vu32.uw,$Vv32.uw)", (V6_veqw_and HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
[all …]
DHexagonIntrinsics.td209 Requires<[UseHVX]>;
214 Requires<[UseHVX]>;
267 Requires<[UseHVX]>;
271 Requires<[UseHVX]>;
275 Requires<[UseHVX]>;
279 Requires<[UseHVX]>;
286 Requires<[UseHVX]>;
291 Requires<[UseHVX]>;
295 Requires<[UseHVX]>;
302 Requires<[UseHVX]>;
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonDepMapAsm2Intrin.td15 (S2_asr_r_p_or DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;
17 (S2_vsatwh DoubleRegs:$src1)>, Requires<[HasV5]>;
19 (M2_mpysu_up IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;
21 (M2_mpyud_acc_ll_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;
23 (M2_mpyud_acc_ll_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;
25 (M2_cmpysc_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;
27 (M2_cmpysc_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;
29 (M4_cmpyi_whc DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;
31 (M2_mpy_sat_rnd_lh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;
33 (M2_mpy_sat_rnd_lh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;
[all …]
DHexagonMapAsm2IntrinV65.gen.td9 …c1, DoubleRegs:$src2), (A6_vcmpbeq_notany DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV65]>;
10 …:$src3), (V6_vasruwuhsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV65, UseHVX]>;
11 …:$src3), (V6_vasruwuhsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV65, UseHVX]>;
12 …:$src3), (V6_vasruhubsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV65, UseHVX]>;
13 …:$src3), (V6_vasruhubsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV65, UseHVX]>;
14 …rc3), (V6_vasruhubrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV65, UseHVX]>;
15 …rc3), (V6_vasruhubrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV65, UseHVX]>;
16 def: Pat<(int_hexagon_V6_vabsb HvxVR:$src1), (V6_vabsb HvxVR:$src1)>, Requires<[HasV65, UseHVX]>;
17 def: Pat<(int_hexagon_V6_vabsb_128B HvxVR:$src1), (V6_vabsb HvxVR:$src1)>, Requires<[HasV65, UseHVX…
18 def: Pat<(int_hexagon_V6_vabsb_sat HvxVR:$src1), (V6_vabsb_sat HvxVR:$src1)>, Requires<[HasV65, Use…
[all …]
DHexagonDepMappings.td154 …= vcmp.eq($Vu32.ub,$Vv32.ub)", (V6_veqb HvxQR:$Qd4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
155 …mp.eq($Vu32.ub,$Vv32.ub)", (V6_veqb_and HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
156 …cmp.eq($Vu32.ub,$Vv32.ub)", (V6_veqb_or HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
157 …mp.eq($Vu32.ub,$Vv32.ub)", (V6_veqb_xor HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
158 …= vcmp.eq($Vu32.uh,$Vv32.uh)", (V6_veqh HvxQR:$Qd4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
159 …mp.eq($Vu32.uh,$Vv32.uh)", (V6_veqh_and HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
160 …cmp.eq($Vu32.uh,$Vv32.uh)", (V6_veqh_or HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
161 …mp.eq($Vu32.uh,$Vv32.uh)", (V6_veqh_xor HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
162 …= vcmp.eq($Vu32.uw,$Vv32.uw)", (V6_veqw HvxQR:$Qd4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
163 …mp.eq($Vu32.uw,$Vv32.uw)", (V6_veqw_and HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
[all …]
DHexagonIntrinsics.td209 Requires<[UseHVX]>;
214 Requires<[UseHVX]>;
265 Requires<[UseHVX]>;
269 Requires<[UseHVX]>;
273 Requires<[UseHVX]>;
277 Requires<[UseHVX]>;
282 Requires<[UseHVX]>;
286 Requires<[UseHVX]>;
290 Requires<[UseHVX]>;
294 Requires<[UseHVX]>;
[all …]
/external/llvm/lib/Target/Hexagon/
DHexagonInstrFormatsV60.td46 OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
52 OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
58 OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
64 Requires<[HasV60T, UseHVX]>;
70 OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
76 OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
82 OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
88 OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
94 OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
100 OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
[all …]
DHexagonIntrinsicsV60.td67 Requires<[UseHVXSgl]>;
71 Requires<[UseHVXSgl]>;
76 Requires<[UseHVXDbl]>;
81 Requires<[UseHVXDbl]>;
87 Requires<[UseHVXSgl]>;
92 Requires<[UseHVXSgl]>;
97 Requires<[UseHVXSgl]>;
102 Requires<[UseHVXSgl]>;
107 Requires<[UseHVXSgl]>;
112 Requires<[UseHVXSgl]>;
[all …]
DHexagonInstrAlias.td283 Requires<[UseMEMOP]>;
287 Requires<[UseMEMOP]>;
291 Requires<[UseMEMOP]>;
295 Requires<[UseMEMOP]>;
299 Requires<[UseMEMOP]>;
303 Requires<[UseMEMOP]>;
307 Requires<[UseMEMOP]>;
311 Requires<[UseMEMOP]>;
315 Requires<[UseMEMOP]>;
319 Requires<[UseMEMOP]>;
[all …]
/external/llvm/lib/Target/X86/
DX86InstrMPX.td19 Requires<[HasMPX, Not64BitMode]>;
22 Requires<[HasMPX, In64BitMode]>;
30 Requires<[HasMPX, Not64BitMode]>;
33 Requires<[HasMPX, In64BitMode]>;
36 Requires<[HasMPX, Not64BitMode]>;
39 Requires<[HasMPX, In64BitMode]>;
47 Requires<[HasMPX]>;
50 Requires<[HasMPX, Not64BitMode]>;
53 Requires<[HasMPX, In64BitMode]>;
57 Requires<[HasMPX]>;
[all …]
DX86InstrTSX.td24 Requires<[HasRTM]>;
28 "xbegin\t$dst", []>, OpSize16, Requires<[HasRTM]>;
30 "xbegin\t$dst", []>, OpSize32, Requires<[HasRTM]>;
34 "xend", [(int_x86_xend)]>, TB, Requires<[HasRTM]>;
38 "xtest", [(set EFLAGS, (X86xtest))]>, TB, Requires<[HasTSX]>;
42 [(int_x86_xabort imm:$imm)]>, Requires<[HasRTM]>;
47 def XACQUIRE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "xacquire", []>, Requires<[HasHLE]>;
48 def XRELEASE_PREFIX : I<0xF3, RawFrm, (outs), (ins), "xrelease", []>, Requires<[HasHLE]>;
DX86InstrVMX.td21 Requires<[Not64BitMode]>;
24 Requires<[In64BitMode]>;
28 Requires<[Not64BitMode]>;
31 Requires<[In64BitMode]>;
47 "vmread{q}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[In64BitMode]>;
49 "vmread{q}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[In64BitMode]>;
51 "vmread{l}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[Not64BitMode]>;
53 "vmread{l}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[Not64BitMode]>;
55 "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[In64BitMode]>;
57 "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[In64BitMode]>;
[all …]
DX86InstrSVM.td34 "vmrun\t{%eax|eax}", []>, TB, Requires<[Not64BitMode]>;
37 "vmrun\t{%rax|rax}", []>, TB, Requires<[In64BitMode]>;
42 "vmload\t{%eax|eax}", []>, TB, Requires<[Not64BitMode]>;
45 "vmload\t{%rax|rax}", []>, TB, Requires<[In64BitMode]>;
50 "vmsave\t{%eax|eax}", []>, TB, Requires<[Not64BitMode]>;
53 "vmsave\t{%rax|rax}", []>, TB, Requires<[In64BitMode]>;
58 "invlpga\t{%ecx, %eax|eax, ecx}", []>, TB, Requires<[Not64BitMode]>;
61 "invlpga\t{%ecx, %rax|rax, ecx}", []>, TB, Requires<[In64BitMode]>;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/
DWebAssemblyInstrCall.td35 Requires<preds>;
44 Requires<preds>;
54 Requires<preds>;
83 Requires<[HasTailCall]>;
107 Requires<[HasTailCall]>;
116 Requires<[HasTailCall]>;
131 (CALL_v16i8 tglobaladdr:$callee)>, Requires<[HasSIMD128]>;
133 (CALL_v8i16 tglobaladdr:$callee)>, Requires<[HasSIMD128]>;
135 (CALL_v4i32 tglobaladdr:$callee)>, Requires<[HasSIMD128]>;
137 (CALL_v2i64 tglobaladdr:$callee)>, Requires<[HasSIMD128]>;
[all …]
/external/llvm-project/llvm/lib/Target/X86/
DX86InstrVMX.td21 Requires<[Not64BitMode]>;
24 Requires<[In64BitMode]>;
29 Requires<[Not64BitMode]>;
32 Requires<[In64BitMode]>;
52 "vmread{q}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[In64BitMode]>,
55 "vmread{l}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[Not64BitMode]>,
60 "vmread{q}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[In64BitMode]>,
63 "vmread{l}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[Not64BitMode]>,
68 "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[In64BitMode]>,
71 "vmwrite{l}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[Not64BitMode]>,
[all …]
DX86InstrSystem.td47 def INTO : I<0xce, RawFrm, (outs), (ins), "into", []>, Requires<[Not64BitMode]>;
66 Requires<[In64BitMode]>;
72 Requires<[In64BitMode]>;
76 (INT3)>, Requires<[NotPS4]>;
78 (INT (i8 0x41))>, Requires<[IsPS4]>;
130 Requires<[Not64BitMode]>;
133 Requires<[In64BitMode]>;
137 Requires<[Not64BitMode]>;
140 Requires<[In64BitMode]>;
149 Requires<[Not64BitMode]>;
[all …]
DX86InstrControl.td24 "ret{l}", []>, OpSize32, Requires<[Not64BitMode]>;
26 "ret{q}", []>, OpSize32, Requires<[In64BitMode]>;
30 "ret{l}\t$amt", []>, OpSize32, Requires<[Not64BitMode]>;
32 "ret{q}\t$amt", []>, OpSize32, Requires<[In64BitMode]>;
38 "{l}ret{|f}q", []>, Requires<[In64BitMode]>;
44 "{l}ret{|f}q\t$amt", []>, Requires<[In64BitMode]>;
54 def IRET64 : RI <0xcf, RawFrm, (outs), (ins), "iretq", []>, Requires<[In64BitMode]>;
115 "jcxz\t$dst", []>, AdSize16, Requires<[Not64BitMode]>;
122 "jrcxz\t$dst", []>, AdSize64, Requires<[In64BitMode]>;
128 [(brind GR16:$dst)]>, Requires<[Not64BitMode]>,
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86InstrVMX.td21 Requires<[Not64BitMode]>;
24 Requires<[In64BitMode]>;
29 Requires<[Not64BitMode]>;
32 Requires<[In64BitMode]>;
52 "vmread{q}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[In64BitMode]>,
55 "vmread{l}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[Not64BitMode]>,
60 "vmread{q}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[In64BitMode]>,
63 "vmread{l}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[Not64BitMode]>,
68 "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[In64BitMode]>,
71 "vmwrite{l}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[Not64BitMode]>,
[all …]
DX86InstrSystem.td34 def INTO : I<0xce, RawFrm, (outs), (ins), "into", []>, Requires<[Not64BitMode]>;
52 Requires<[In64BitMode]>;
58 Requires<[In64BitMode]>;
62 (INT3)>, Requires<[NotPS4]>;
64 (INT (i8 0x41))>, Requires<[IsPS4]>;
116 Requires<[Not64BitMode]>;
119 Requires<[In64BitMode]>;
123 Requires<[Not64BitMode]>;
126 Requires<[In64BitMode]>;
135 Requires<[Not64BitMode]>;
[all …]
DX86InstrControl.td24 "ret{l}", []>, OpSize32, Requires<[Not64BitMode]>;
26 "ret{q}", []>, OpSize32, Requires<[In64BitMode]>;
30 "ret{l}\t$amt", []>, OpSize32, Requires<[Not64BitMode]>;
32 "ret{q}\t$amt", []>, OpSize32, Requires<[In64BitMode]>;
38 "{l}ret{|f}q", []>, Requires<[In64BitMode]>;
44 "{l}ret{|f}q\t$amt", []>, Requires<[In64BitMode]>;
54 def IRET64 : RI <0xcf, RawFrm, (outs), (ins), "iretq", []>, Requires<[In64BitMode]>;
115 "jcxz\t$dst", []>, AdSize16, Requires<[Not64BitMode]>;
122 "jrcxz\t$dst", []>, AdSize64, Requires<[In64BitMode]>;
128 [(brind GR16:$dst)]>, Requires<[Not64BitMode]>,
[all …]
/external/llvm/lib/Target/Sparc/
DSparcInstrAliases.td76 (BPICC brtarget:$imm, condVal)>, Requires<[HasV9]>;
80 (BPICC brtarget:$imm, condVal)>, Requires<[HasV9]>;
84 (BPICCA brtarget:$imm, condVal)>, Requires<[HasV9]>;
88 (BPICCA brtarget:$imm, condVal)>, Requires<[HasV9]>;
92 (BPICCNT brtarget:$imm, condVal)>, Requires<[HasV9]>;
96 (BPICCANT brtarget:$imm, condVal)>, Requires<[HasV9]>;
100 (BPXCC brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
104 (BPXCC brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
108 (BPXCCA brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
112 (BPXCCA brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/
DSparcInstrAliases.td75 (BPICC brtarget:$imm, condVal)>, Requires<[HasV9]>;
79 (BPICC brtarget:$imm, condVal)>, Requires<[HasV9]>;
83 (BPICCA brtarget:$imm, condVal)>, Requires<[HasV9]>;
87 (BPICCA brtarget:$imm, condVal)>, Requires<[HasV9]>;
91 (BPICCNT brtarget:$imm, condVal)>, Requires<[HasV9]>;
95 (BPICCANT brtarget:$imm, condVal)>, Requires<[HasV9]>;
99 (BPXCC brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
103 (BPXCC brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
107 (BPXCCA brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
111 (BPXCCA brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
[all …]
/external/llvm-project/llvm/lib/Target/Sparc/
DSparcInstrAliases.td75 (BPICC brtarget:$imm, condVal)>, Requires<[HasV9]>;
79 (BPICC brtarget:$imm, condVal)>, Requires<[HasV9]>;
83 (BPICCA brtarget:$imm, condVal)>, Requires<[HasV9]>;
87 (BPICCA brtarget:$imm, condVal)>, Requires<[HasV9]>;
91 (BPICCNT brtarget:$imm, condVal)>, Requires<[HasV9]>;
95 (BPICCANT brtarget:$imm, condVal)>, Requires<[HasV9]>;
99 (BPXCC brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
103 (BPXCC brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
107 (BPXCCA brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
111 (BPXCCA brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
[all …]

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