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/external/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td121 def : IC<"IALLUIS", 0b000, 0b0111, 0b0001, 0b000, 0>;
123 def : IC<"IVAU", 0b000, 0b0111, 0b0001, 0b000, 1>;
312 def : ROSysReg<"MDCCSR_EL0", 0b10, 0b011, 0b0000, 0b0001, 0b000>;
314 def : ROSysReg<"MDRAR_EL1", 0b10, 0b000, 0b0001, 0b0000, 0b000>;
315 def : ROSysReg<"OSLSR_EL1", 0b10, 0b000, 0b0001, 0b0001, 0b100>;
327 def : ROSysReg<"ID_PFR0_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b000>;
328 def : ROSysReg<"ID_PFR1_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b001>;
329 def : ROSysReg<"ID_DFR0_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b010>;
330 def : ROSysReg<"ID_AFR0_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b011>;
331 def : ROSysReg<"ID_MMFR0_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b100>;
[all …]
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td173 def : IC<"IALLUIS", 0b000, 0b0111, 0b0001, 0b000, 0>;
444 def : TLBI<"VMALLE1OS", 0b000, 0b1000, 0b0001, 0b000, 0>;
445 def : TLBI<"VAE1OS", 0b000, 0b1000, 0b0001, 0b001>;
446 def : TLBI<"ASIDE1OS", 0b000, 0b1000, 0b0001, 0b010>;
447 def : TLBI<"VAAE1OS", 0b000, 0b1000, 0b0001, 0b011>;
448 def : TLBI<"VALE1OS", 0b000, 0b1000, 0b0001, 0b101>;
449 def : TLBI<"VAALE1OS", 0b000, 0b1000, 0b0001, 0b111>;
452 def : TLBI<"VAE2OS", 0b100, 0b1000, 0b0001, 0b001>;
453 def : TLBI<"VALE2OS", 0b100, 0b1000, 0b0001, 0b101>;
454 def : TLBI<"VMALLS12E1OS", 0b100, 0b1000, 0b0001, 0b110, 0>;
[all …]
DAArch64SVEInstrInfo.td410 …defm FSUB_ZPmZ : sve_fp_2op_p_zds<0b0001, "fsub", "FSUB_ZPZZ", int_aarch64_sve_fsub, Destructive…
642 defm BIC_PPzPP : sve_int_pred_log<0b0001, "bic", int_aarch64_sve_bic_z>;
683 defm LD1B_H_IMM : sve_mem_cld_si<0b0001, "ld1b", Z_h, ZPR16>;
729 defm LD1B_H : sve_mem_cld_ss<0b0001, "ld1b", Z_h, ZPR16, GPR64NoXZRshifted8>;
747 defm LDNF1B_H_IMM : sve_mem_cldnf_si<0b0001, "ldnf1b", Z_h, ZPR16>;
765 defm LDFF1B_H : sve_mem_cldff_ss<0b0001, "ldff1b", Z_h, ZPR16, GPR64shifted8>;
812 …defm GLDFF1SB_S : sve_mem_32b_gld_vs_32_unscaled<0b0001, "ldff1sb", AArch64ldff1s_gather_sxtw_z, A…
834 …defm GLDFF1SB_S : sve_mem_32b_gld_vi_32_ptrs<0b0001, "ldff1sb", imm0_31, AArch64ldff1s_gather_imm_…
847 …defm GLDFF1SB_D : sve_mem_64b_gld_vi_64_ptrs<0b0001, "ldff1sb", imm0_31, AArch64ldff1s_gather_imm_…
864 …defm GLDFF1SB_D : sve_mem_64b_gld_vs2_64_unscaled<0b0001, "ldff1sb", AArch64ldff1s_gather_z, nxv2i…
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td168 def : IC<"IALLUIS", 0b000, 0b0111, 0b0001, 0b000, 0>;
439 def : TLBI<"VMALLE1OS", 0b000, 0b1000, 0b0001, 0b000, 0>;
440 def : TLBI<"VAE1OS", 0b000, 0b1000, 0b0001, 0b001>;
441 def : TLBI<"ASIDE1OS", 0b000, 0b1000, 0b0001, 0b010>;
442 def : TLBI<"VAAE1OS", 0b000, 0b1000, 0b0001, 0b011>;
443 def : TLBI<"VALE1OS", 0b000, 0b1000, 0b0001, 0b101>;
444 def : TLBI<"VAALE1OS", 0b000, 0b1000, 0b0001, 0b111>;
447 def : TLBI<"VAE2OS", 0b100, 0b1000, 0b0001, 0b001>;
448 def : TLBI<"VALE2OS", 0b100, 0b1000, 0b0001, 0b101>;
449 def : TLBI<"VMALLS12E1OS", 0b100, 0b1000, 0b0001, 0b110, 0>;
[all …]
DAArch64SVEInstrInfo.td194 defm FSUB_ZPmZ : sve_fp_2op_p_zds<0b0001, "fsub", int_aarch64_sve_fsub>;
314 defm BIC_PPzPP : sve_int_pred_log<0b0001, "bic", int_aarch64_sve_bic_z>;
343 defm LD1B_H_IMM : sve_mem_cld_si<0b0001, "ld1b", Z_h, ZPR16>;
389 defm LD1B_H : sve_mem_cld_ss<0b0001, "ld1b", Z_h, ZPR16, GPR64NoXZRshifted8>;
407 defm LDNF1B_H_IMM : sve_mem_cldnf_si<0b0001, "ldnf1b", Z_h, ZPR16>;
425 defm LDFF1B_H : sve_mem_cldff_ss<0b0001, "ldff1b", Z_h, ZPR16, GPR64shifted8>;
472 …defm GLDFF1SB_S : sve_mem_32b_gld_vs_32_unscaled<0b0001, "ldff1sb", null_frag, nul…
494 …defm GLDFF1SB_S : sve_mem_32b_gld_vi_32_ptrs<0b0001, "ldff1sb", imm0_31, null_frag, …
507 …defm GLDFF1SB_D : sve_mem_64b_gld_vi_64_ptrs<0b0001, "ldff1sb", imm0_31, null_frag, …
524 defm GLDFF1SB_D : sve_mem_64b_gld_vs2_64_unscaled<0b0001, "ldff1sb", null_frag, nxv2i8>;
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/external/llvm/lib/Target/Sparc/
DSparcInstrAliases.td272 defm : int_cond_alias<"e", 0b0001>;
289 defm : int_cond_alias<"eq", 0b0001>; // same as e
290 defm : int_cond_alias<"z", 0b0001>; // same as e
302 defm : fp_cond_alias<"ne", 0b0001>;
313 defm : fp_cond_alias<"nz", 0b0001>; // same as ne
325 defm : cp_cond_alias<"123", 0b0001>;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/
DSparcInstrAliases.td271 defm : int_cond_alias<"e", 0b0001>;
288 defm : int_cond_alias<"eq", 0b0001>; // same as e
289 defm : int_cond_alias<"z", 0b0001>; // same as e
301 defm : fp_cond_alias<"ne", 0b0001>;
312 defm : fp_cond_alias<"nz", 0b0001>; // same as ne
324 defm : cp_cond_alias<"123", 0b0001>;
/external/llvm-project/llvm/lib/Target/Sparc/
DSparcInstrAliases.td271 defm : int_cond_alias<"e", 0b0001>;
288 defm : int_cond_alias<"eq", 0b0001>; // same as e
289 defm : int_cond_alias<"z", 0b0001>; // same as e
301 defm : fp_cond_alias<"ne", 0b0001>;
312 defm : fp_cond_alias<"nz", 0b0001>; // same as ne
324 defm : cp_cond_alias<"123", 0b0001>;
/external/deqp/external/vulkancts/modules/vulkan/conditional_rendering/
DvktConditionalDrawAndClearTests.cpp128 b0001 = 0x1, enumerator
147 { false, false, false, b0001, b1000, b1111, false, NONE },
148 { true, false, false, b0001, b1000, b0000, false, NONE },
149 { true, false, false, b0001, b0001, b1110, false, NONE },
154 { true, true, true, b0010, b1000, b0001, false, NONE },
/external/llvm-project/llvm/lib/Target/ARM/Utils/
DARMBaseInfo.h113 TTTT = 0b0001,
/external/llvm-project/llvm/test/TableGen/
DDAGDefaultOps.td46 def AddRRI : RRI<"add", 0b0001>;
/external/llvm/lib/Target/Hexagon/
DHexagonInstrEnc.td312 class V6_vL32b_cur_ai_enc : Enc_COPROC_VMEM_vL32_b_ai<0b0001>;
331 class V6_vL32b_cur_ai_128B_enc : Enc_COPROC_VMEM_vL32_b_ai_128B<0b0001>;
490 class V6_vL32b_cur_pi_enc : Enc_COPROC_VMEM_vL32_b_pi<0b0001>;
509 class V6_vL32b_cur_pi_128B_enc : Enc_COPROC_VMEM_vL32_b_pi_128B<0b0001>;
820 class V6_vlalignb_enc : Enc_COPROC_VX_4op_r<0b0001>;
/external/llvm-project/llvm/lib/Target/RISCV/Utils/
DRISCVBaseInfo.h57 VS2Constraint = 0b0001,
/external/llvm/lib/Target/ARM/
DARMInstrNEON.td1001 def VLD4q8 : VLD4D<0b0001, {0,0,?,?}, "8">;
1002 def VLD4q16 : VLD4D<0b0001, {0,1,?,?}, "16">;
1003 def VLD4q32 : VLD4D<0b0001, {1,0,?,?}, "32">;
1004 def VLD4q8_UPD : VLD4DWB<0b0001, {0,0,?,?}, "8">;
1005 def VLD4q16_UPD : VLD4DWB<0b0001, {0,1,?,?}, "16">;
1006 def VLD4q32_UPD : VLD4DWB<0b0001, {1,0,?,?}, "32">;
1144 def VLD2LNd8 : VLD2LN<0b0001, {?,?,?,?}, "8"> {
1180 def VLD2LNd8_UPD : VLD2LNWB<0b0001, {?,?,?,?}, "8"> {
2003 def VST4q8 : VST4D<0b0001, {0,0,?,?}, "8">;
2004 def VST4q16 : VST4D<0b0001, {0,1,?,?}, "16">;
[all …]
DARMInstrVFP.td846 def VNEGD : ADuI<0b11101, 0b11, 0b0001, 0b01, 0,
851 def VNEGS : ASuIn<0b11101, 0b11, 0b0001, 0b01, 0,
860 def VNEGH : AHuI<0b11101, 0b11, 0b0001, 0b01, 0,
946 def VSQRTD : ADuI<0b11101, 0b11, 0b0001, 0b11, 0,
951 def VSQRTS : ASuI<0b11101, 0b11, 0b0001, 0b11, 0,
956 def VSQRTH : AHuI<0b11101, 0b11, 0b0001, 0b11, 0,
2073 def FMSTAT : MovFromVFP<0b0001 /* fpscr */, (outs), (ins),
2078 def VMRS : MovFromVFP<0b0001 /* fpscr */, (outs GPR:$Rt), (ins),
2123 def VMSR : MovToVFP<0b0001 /* fpscr */, (outs), (ins GPR:$src),
DARMInstrThumb2.td1069 let Inst{26-23} = 0b0001;
2138 def t2QADD16 : T2I_pam<0b001, 0b0001, "qadd16">;
2139 def t2QADD8 : T2I_pam<0b000, 0b0001, "qadd8">;
2140 def t2QASX : T2I_pam<0b010, 0b0001, "qasx">;
2145 def t2QSAX : T2I_pam<0b110, 0b0001, "qsax">;
2149 def t2QSUB16 : T2I_pam<0b101, 0b0001, "qsub16">;
2150 def t2QSUB8 : T2I_pam<0b100, 0b0001, "qsub8">;
2363 defm t2BIC : T2I_bin_w_irs<0b0001, "bic",
2566 let Inst{7-4} = 0b0001; // Multiply and Subtract
2625 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMInstrNEON.td983 def VLD4q8 : VLD4D<0b0001, {0,0,?,?}, "8">;
984 def VLD4q16 : VLD4D<0b0001, {0,1,?,?}, "16">;
985 def VLD4q32 : VLD4D<0b0001, {1,0,?,?}, "32">;
986 def VLD4q8_UPD : VLD4DWB<0b0001, {0,0,?,?}, "8">;
987 def VLD4q16_UPD : VLD4DWB<0b0001, {0,1,?,?}, "16">;
988 def VLD4q32_UPD : VLD4DWB<0b0001, {1,0,?,?}, "32">;
1151 def VLD2LNd8 : VLD2LN<0b0001, {?,?,?,?}, "8"> {
1187 def VLD2LNd8_UPD : VLD2LNWB<0b0001, {?,?,?,?}, "8"> {
2062 def VST4q8 : VST4D<0b0001, {0,0,?,?}, "8">;
2063 def VST4q16 : VST4D<0b0001, {0,1,?,?}, "16">;
[all …]
DARMInstrVFP.td922 def VNEGD : ADuI<0b11101, 0b11, 0b0001, 0b01, 0,
927 def VNEGS : ASuIn<0b11101, 0b11, 0b0001, 0b01, 0,
936 def VNEGH : AHuI<0b11101, 0b11, 0b0001, 0b01, 0,
1023 def VSQRTD : ADuI<0b11101, 0b11, 0b0001, 0b11, 0,
1029 def VSQRTS : ASuI<0b11101, 0b11, 0b0001, 0b11, 0,
1035 def VSQRTH : AHuI<0b11101, 0b11, 0b0001, 0b11, 0,
2341 def FMSTAT : MovFromVFP<0b0001 /* fpscr */, (outs), (ins),
2346 def VMRS : MovFromVFP<0b0001 /* fpscr */, (outs GPRnopc:$Rt), (ins),
2426 def VMSR : MovToVFP<0b0001 /* fpscr */, (outs), (ins GPRnopc:$Rt),
2733 defm VSTR_FPSCR : vfp_vstrldr_sysreg<0b0,0b0001, "fpscr">;
[all …]
DARMInstrThumb2.td1267 let Inst{26-23} = 0b0001;
2418 def t2QADD16 : T2I_pam_intrinsics<0b001, 0b0001, "qadd16", int_arm_qadd16>;
2419 def t2QADD8 : T2I_pam_intrinsics<0b000, 0b0001, "qadd8", int_arm_qadd8>;
2420 def t2QASX : T2I_pam_intrinsics<0b010, 0b0001, "qasx", int_arm_qasx>;
2422 def t2QSAX : T2I_pam_intrinsics<0b110, 0b0001, "qsax", int_arm_qsax>;
2423 def t2QSUB16 : T2I_pam_intrinsics<0b101, 0b0001, "qsub16", int_arm_qsub16>;
2424 def t2QSUB8 : T2I_pam_intrinsics<0b100, 0b0001, "qsub8", int_arm_qsub8>;
2670 defm t2BIC : T2I_bin_w_irs<0b0001, "bic",
2882 def t2MLS: T2FourRegMLA<0b0001, "mls",
2921 T2SMMUL<0b0001, "smmulr",
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/external/llvm-project/llvm/lib/Target/ARM/
DARMInstrNEON.td959 def VLD4q8 : VLD4D<0b0001, {0,0,?,?}, "8">;
960 def VLD4q16 : VLD4D<0b0001, {0,1,?,?}, "16">;
961 def VLD4q32 : VLD4D<0b0001, {1,0,?,?}, "32">;
962 def VLD4q8_UPD : VLD4DWB<0b0001, {0,0,?,?}, "8">;
963 def VLD4q16_UPD : VLD4DWB<0b0001, {0,1,?,?}, "16">;
964 def VLD4q32_UPD : VLD4DWB<0b0001, {1,0,?,?}, "32">;
1133 def VLD2LNd8 : VLD2LN<0b0001, {?,?,?,?}, "8"> {
1169 def VLD2LNd8_UPD : VLD2LNWB<0b0001, {?,?,?,?}, "8"> {
2044 def VST4q8 : VST4D<0b0001, {0,0,?,?}, "8">;
2045 def VST4q16 : VST4D<0b0001, {0,1,?,?}, "16">;
[all …]
DARMInstrVFP.td991 def VNEGD : ADuI<0b11101, 0b11, 0b0001, 0b01, 0,
996 def VNEGS : ASuIn<0b11101, 0b11, 0b0001, 0b01, 0,
1005 def VNEGH : AHuI<0b11101, 0b11, 0b0001, 0b01, 0,
1092 def VSQRTD : ADuI<0b11101, 0b11, 0b0001, 0b11, 0,
1098 def VSQRTS : ASuI<0b11101, 0b11, 0b0001, 0b11, 0,
1104 def VSQRTH : AHuI<0b11101, 0b11, 0b0001, 0b11, 0,
2437 def FMSTAT : MovFromVFP<0b0001 /* fpscr */, (outs), (ins),
2442 def VMRS : MovFromVFP<0b0001 /* fpscr */, (outs GPRnopc:$Rt), (ins),
2522 def VMSR : MovToVFP<0b0001 /* fpscr */, (outs), (ins GPRnopc:$Rt),
2834 defm VSTR_FPSCR : vfp_vstrldr_sysreg<0b0,0b0001, "fpscr">;
[all …]
DARMInstrThumb2.td1268 let Inst{26-23} = 0b0001;
2467 def t2QADD16 : T2I_pam_intrinsics<0b001, 0b0001, "qadd16", int_arm_qadd16>;
2468 def t2QADD8 : T2I_pam_intrinsics<0b000, 0b0001, "qadd8", int_arm_qadd8>;
2469 def t2QASX : T2I_pam_intrinsics<0b010, 0b0001, "qasx", int_arm_qasx>;
2471 def t2QSAX : T2I_pam_intrinsics<0b110, 0b0001, "qsax", int_arm_qsax>;
2472 def t2QSUB16 : T2I_pam_intrinsics<0b101, 0b0001, "qsub16", int_arm_qsub16>;
2473 def t2QSUB8 : T2I_pam_intrinsics<0b100, 0b0001, "qsub8", int_arm_qsub8>;
2735 defm t2BIC : T2I_bin_w_irs<0b0001, "bic",
2951 def t2MLS: T2FourRegMLA<0b0001, "mls",
2990 T2SMMUL<0b0001, "smmulr",
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/external/llvm/lib/Target/AVR/
DAVRInstrInfo.td349 def ADCRdRr : FRdRr<0b0001,
390 def SUBRdRr : FRdRr<0b0001,
826 def CPSE : FRdRr<0b0001,
833 def CPRdRr : FRdRr<0b0001,
1575 def ROLRd : FRdRr<0b0001,
/external/llvm-project/llvm/lib/Target/RISCV/
DRISCVInstrFormats.td56 def VS2Constraint : RISCVVConstraint<0b0001>;
/external/llvm/lib/Target/Mips/
DMipsMSAInstrInfo.td655 class FCOR_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011100>;
656 class FCOR_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011100>;
667 class FCUN_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011010>;
668 class FCUN_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011010>;
759 class FSUB_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011011>;
760 class FSUB_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011011>;
1018 class SPLATI_B_ENC : MSA_ELM_B_FMT<0b0001, 0b011001>;
1019 class SPLATI_H_ENC : MSA_ELM_H_FMT<0b0001, 0b011001>;
1020 class SPLATI_W_ENC : MSA_ELM_W_FMT<0b0001, 0b011001>;
1021 class SPLATI_D_ENC : MSA_ELM_D_FMT<0b0001, 0b011001>;

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