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Searched refs:cmplt (Results 1 – 25 of 28) sorted by relevance

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/external/llvm-project/llvm/test/MC/AArch64/SVE/
Dcmplt.s10 cmplt p0.b, p0/z, z0.b, z1.b label
16 cmplt p0.h, p0/z, z0.h, z1.h label
22 cmplt p0.s, p0/z, z0.s, z1.s label
28 cmplt p0.d, p0/z, z0.d, z1.d label
34 cmplt p0.b, p0/z, z0.b, z0.d label
40 cmplt p0.h, p0/z, z0.h, z0.d label
46 cmplt p0.s, p0/z, z0.s, z0.d label
52 cmplt p0.b, p0/z, z0.b, #-16 label
58 cmplt p0.h, p0/z, z0.h, #-16 label
64 cmplt p0.s, p0/z, z0.s, #-16 label
[all …]
Dcmplt-diagnostics.s6 cmplt p0.b, p8/z, z0.b, z0.b label
15 cmplt p0.b, p0/m, z0.b, z0.b label
24 cmplt p0.b, p0/z, z0.b, z0.h label
29 cmplt p0.h, p0/z, z0.h, z0.s label
34 cmplt p0.s, p0/z, z0.s, z0.h label
39 cmplt p0.d, p0/z, z0.d, z0.s label
44 cmplt p0.b, p0/z, z0.h, z0.h label
49 cmplt p0.h, p0/z, z0.s, z0.s label
54 cmplt p0.s, p0/z, z0.h, z0.h label
59 cmplt p0.d, p0/z, z0.s, z0.s label
[all …]
/external/llvm-project/llvm/test/CodeGen/AArch64/
Dsve-setcc.ll10 ; CHECK: cmplt p1.h, p0/z, z0.h, #0
14 …%0 = tail call <vscale x 8 x i1> @llvm.aarch64.sve.cmplt.wide.nxv8i16(<vscale x 8 x i1> %pg, <vsca…
28 declare <vscale x 8 x i1> @llvm.aarch64.sve.cmplt.wide.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16…
Dsve-intrinsics-int-compares-with-imm.ll529 ; CHECK: cmplt p0.b, p0/z, z0.b, #4
539 ; CHECK: cmplt p0.b, p0/z, z0.b, #4
551 ; CHECK: cmplt p0.b, p0/z, z0.b, #4
555 %out = call <vscale x 16 x i1> @llvm.aarch64.sve.cmplt.wide.nxv16i8(<vscale x 16 x i1> %pg,
563 ; CHECK: cmplt p0.h, p0/z, z0.h, #-16
573 ; CHECK: cmplt p0.h, p0/z, z0.h, #-16
585 ; CHECK: cmplt p0.h, p0/z, z0.h, #-16
589 %out = call <vscale x 8 x i1> @llvm.aarch64.sve.cmplt.wide.nxv8i16(<vscale x 8 x i1> %pg,
597 ; CHECK: cmplt p0.s, p0/z, z0.s, #15
607 ; CHECK: cmplt p0.s, p0/z, z0.s, #15
[all …]
Dsve-intrinsics-int-compares.ll809 ; CHECK: cmplt p0.b, p0/z, z0.b, z1.d
811 %out = call <vscale x 16 x i1> @llvm.aarch64.sve.cmplt.wide.nxv16i8(<vscale x 16 x i1> %pg,
819 ; CHECK: cmplt p0.h, p0/z, z0.h, z1.d
821 %out = call <vscale x 8 x i1> @llvm.aarch64.sve.cmplt.wide.nxv8i16(<vscale x 8 x i1> %pg,
829 ; CHECK: cmplt p0.s, p0/z, z0.s, z1.d
831 %out = call <vscale x 4 x i1> @llvm.aarch64.sve.cmplt.wide.nxv4i32(<vscale x 4 x i1> %pg,
1023 declare <vscale x 16 x i1> @llvm.aarch64.sve.cmplt.wide.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x …
1024 declare <vscale x 8 x i1> @llvm.aarch64.sve.cmplt.wide.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16…
1025 declare <vscale x 4 x i1> @llvm.aarch64.sve.cmplt.wide.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32…
/external/llvm/test/CodeGen/Hexagon/
Dcmp.ll46 define i32 @cmplt(i32 %i) #0 {
51 %1 = call i32 @llvm.hexagon.C2.cmplt(i32 %0, i32 4)
57 declare i32 @llvm.hexagon.C2.cmplt(i32, i32) #1
/external/llvm-project/llvm/test/CodeGen/Hexagon/
Dcmp.ll46 define i32 @cmplt(i32 %i) #0 {
51 %1 = call i32 @llvm.hexagon.C2.cmplt(i32 %0, i32 4)
57 declare i32 @llvm.hexagon.C2.cmplt(i32, i32) #1
/external/llvm/test/CodeGen/ARM/
D2013-05-05-IfConvertBug.ll117 ; CHECK-NOT: cmplt
/external/llvm-project/llvm/test/CodeGen/ARM/
D2013-05-05-IfConvertBug.ll116 ; CHECK-NOT: cmplt
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64SVEInstrInfo.td791 defm CMPLT_WIDE_PPzZZ : sve_int_cmp_1_wide<0b010, "cmplt", int_aarch64_sve_cmplt_wide>;
800 defm CMPLT_PPzZI : sve_int_scmp_vi<0b010, "cmplt", SETLT, null_frag, int_aarch64_sve_cmpgt>;
1055 def : InstAlias<"cmplt $Zd, $Pg/z, $Zm, $Zn",
1057 def : InstAlias<"cmplt $Zd, $Pg/z, $Zm, $Zn",
1059 def : InstAlias<"cmplt $Zd, $Pg/z, $Zm, $Zn",
1061 def : InstAlias<"cmplt $Zd, $Pg/z, $Zm, $Zn",
/external/vixl/test/aarch64/
Dtest-disasm-sve-aarch64.cc2491 COMPARE_PREFIX(cmplt(p3.VnB(), p7.Zeroing(), z15.VnB(), 11), in TEST()
2493 COMPARE_PREFIX(cmplt(p3.VnH(), p7.Zeroing(), z15.VnH(), 3), in TEST()
2495 COMPARE_PREFIX(cmplt(p3.VnS(), p7.Zeroing(), z15.VnS(), -10), in TEST()
2497 COMPARE_PREFIX(cmplt(p3.VnD(), p7.Zeroing(), z15.VnD(), -7), in TEST()
2641 COMPARE_PREFIX(cmplt(p6.VnB(), p6.Zeroing(), z4.VnB(), z8.VnD()), in TEST()
2643 COMPARE_PREFIX(cmplt(p6.VnH(), p6.Zeroing(), z4.VnH(), z8.VnD()), in TEST()
2645 COMPARE_PREFIX(cmplt(p6.VnS(), p6.Zeroing(), z4.VnS(), z8.VnD()), in TEST()
2685 COMPARE_PREFIX(cmplt(p14.VnB(), p1.Zeroing(), z24.VnB(), z30.VnB()), in TEST()
2687 COMPARE_PREFIX(cmplt(p14.VnH(), p1.Zeroing(), z24.VnH(), z30.VnH()), in TEST()
2689 COMPARE_PREFIX(cmplt(p14.VnS(), p1.Zeroing(), z24.VnS(), z30.VnS()), in TEST()
[all …]
/external/llvm/test/Transforms/GVN/
D2007-07-31-NoDomInherit.ll103 declare i32 @cmplt(i32, i32, i32)
/external/llvm-project/llvm/test/Transforms/GVN/
D2007-07-31-NoDomInherit.ll103 declare i32 @cmplt(i32, i32, i32)
/external/llvm-project/llvm/test/Transforms/NewGVN/
D2007-07-31-NoDomInherit-xfail.ll104 declare i32 @cmplt(i32, i32, i32)
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/
DAArch64GenAsmMatcher.inc12489 "\005cmple\005cmplo\005cmpls\005cmplt\005cmpne\004cmpp\005cmtst\004cneg\004"
13365 …{ 717 /* cmplt */, AArch64::CMPLT_PPzZI_H, Convert__SVEPredicateHReg1_0__SVEPredicate3bAnyReg1_1__…
13366 …{ 717 /* cmplt */, AArch64::CMPGT_PPzZZ_H, Convert__SVEPredicateHReg1_0__SVEPredicate3bAnyReg1_1__…
13367 …{ 717 /* cmplt */, AArch64::CMPLT_WIDE_PPzZZ_H, Convert__SVEPredicateHReg1_0__SVEPredicate3bAnyReg…
13368 …{ 717 /* cmplt */, AArch64::CMPLT_PPzZI_S, Convert__SVEPredicateSReg1_0__SVEPredicate3bAnyReg1_1__…
13369 …{ 717 /* cmplt */, AArch64::CMPGT_PPzZZ_S, Convert__SVEPredicateSReg1_0__SVEPredicate3bAnyReg1_1__…
13370 …{ 717 /* cmplt */, AArch64::CMPLT_WIDE_PPzZZ_S, Convert__SVEPredicateSReg1_0__SVEPredicate3bAnyReg…
13371 …{ 717 /* cmplt */, AArch64::CMPLT_PPzZI_D, Convert__SVEPredicateDReg1_0__SVEPredicate3bAnyReg1_1__…
13372 …{ 717 /* cmplt */, AArch64::CMPGT_PPzZZ_D, Convert__SVEPredicateDReg1_0__SVEPredicate3bAnyReg1_1__…
13373 …{ 717 /* cmplt */, AArch64::CMPLT_PPzZI_B, Convert__SVEPredicateBReg1_0__SVEPredicate3bAnyReg1_1__…
[all …]
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64SVEInstrInfo.td1237 defm CMPLT_WIDE_PPzZZ : sve_int_cmp_1_wide<0b010, "cmplt", int_aarch64_sve_cmplt_wide>;
1246 defm CMPLT_PPzZI : sve_int_scmp_vi<0b010, "cmplt", SETLT, SETGT>;
1583 def : InstAlias<"cmplt $Zd, $Pg/z, $Zm, $Zn",
1585 def : InstAlias<"cmplt $Zd, $Pg/z, $Zm, $Zn",
1587 def : InstAlias<"cmplt $Zd, $Pg/z, $Zm, $Zn",
1589 def : InstAlias<"cmplt $Zd, $Pg/z, $Zm, $Zn",
/external/vixl/src/aarch64/
Dassembler-sve-aarch64.cc2768 cmplt(pd, pg, zn, zm); in cmp()
2852 void Assembler::cmplt(const PRegisterWithLaneSize& pd, in cmplt() function in vixl::aarch64::Assembler
3079 void Assembler::cmplt(const PRegisterWithLaneSize& pd, in cmplt() function in vixl::aarch64::Assembler
Dassembler-aarch64.h3897 void cmplt(const PRegisterWithLaneSize& pd,
3903 void cmplt(const PRegisterWithLaneSize& pd,
Dmacro-assembler-aarch64.h3895 cmplt(pd, pg, zn, zm); in Cmplt()
3905 cmplt(pd, pg, zn, imm5); in Cmplt()
/external/llvm-project/llvm/test/tools/llvm-mca/ARM/
Dcortex-a57-thumb.s99 cmplt r7, #243
/external/llvm/lib/Target/Hexagon/
DHexagonInstrInfoV4.td3178 // Map cmplt(Rs, Imm) -> !cmpgt(Rs, Imm-1).
DHexagonInstrInfo.td4998 // Map cmplt(Rs, Imm) -> !cmpge(Rs, Imm).
/external/swiftshader/third_party/llvm-10.0/configs/common/include/llvm/IR/
DIntrinsicImpl.inc548 "llvm.aarch64.sve.cmplt.wide",
2144 "llvm.hexagon.C2.cmplt",
10681 1, // llvm.aarch64.sve.cmplt.wide
12277 1, // llvm.hexagon.C2.cmplt
/external/swiftshader/third_party/llvm-subzero/build/Android/include/llvm/IR/
DIntrinsics.gen929 hexagon_C2_cmplt, // llvm.hexagon.C2.cmplt
6987 "llvm.hexagon.C2.cmplt",
14927 1, // llvm.hexagon.C2.cmplt
/external/swiftshader/third_party/llvm-subzero/build/Linux/include/llvm/IR/
DIntrinsics.gen929 hexagon_C2_cmplt, // llvm.hexagon.C2.cmplt
6987 "llvm.hexagon.C2.cmplt",
14927 1, // llvm.hexagon.C2.cmplt

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