Home
last modified time | relevance | path

Searched refs:idxen (Results 1 – 25 of 97) sorted by relevance

1234

/external/llvm-project/llvm/test/MC/AMDGPU/
Dmtbuf-gfx10.s42 tbuffer_load_format_xyzw v[0:3], v0, s[0:3], format:78, 0 idxen
51 tbuffer_load_format_xyzw v[0:3], v[0:1], s[0:3], format:78, 0 idxen offen
60 tbuffer_store_format_d16_x v0, v1, s[4:7], format:33, 0 idxen
63 tbuffer_store_format_d16_xy v0, v1, s[4:7], format:33, 0 idxen
66 tbuffer_store_format_d16_xyzw v[0:1], v2, s[4:7], format:33, 0 idxen
87 tbuffer_store_format_xyzw v[0:3], v4, s[0:3], format:47, 0 idxen
93 tbuffer_store_format_xyzw v[0:3], v[4:5], s[0:3], format:70, 0 idxen offen
96 tbuffer_store_format_xyzw v[0:3], v4, s[0:3], format:63, 0 idxen
99 tbuffer_store_format_xyzw v[0:3], v6, s[0:3], format:46, 0 idxen
102 tbuffer_store_format_x v0, v1, s[0:3], format:125, 0 idxen
[all …]
Dmubuf.s93 buffer_load_dword v1, v2, s[4:7], s1 idxen
97 buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4
101 buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 glc
105 buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 slc
109 buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 tfe
113 buffer_load_dword v1, v2, s[4:7], s1 idxen glc tfe
117 buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 glc slc tfe
121 buffer_load_dword v1, v2, ttmp[4:7], s1 idxen offset:4 glc slc tfe
129 buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen
133 buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4
[all …]
Dmubuf-gfx10.s18 buffer_atomic_fcmpswap_x2 v[0:3], v0, s[0:3], s0 idxen offset:4095
33 buffer_atomic_fmax_x2 v[0:1], v0, s[0:3], s0 idxen offset:4095
45 buffer_atomic_fmin_x2 v[0:1], v0, s[0:3], s0 idxen offset:4095
/external/llvm/test/MC/AMDGPU/
Dmubuf.s93 buffer_load_dword v1, v2, s[4:7], s1 idxen
97 buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4
101 buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 glc
105 buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 slc
109 buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 tfe
113 buffer_load_dword v1, v2, s[4:7], s1 idxen glc tfe
117 buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 glc slc tfe
121 buffer_load_dword v1, v2, ttmp[4:7], s1 idxen offset:4 glc slc tfe
129 buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen
133 buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4
[all …]
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dllvm.amdgcn.struct.tbuffer.store.ll7 …zw v[0:3], [[ZEROREG]], s[0:3], 0 format:[BUF_DATA_FORMAT_16_16_16_16,BUF_NUM_FORMAT_USCALED] idxen
8 …w v[4:7], [[ZEROREG]], s[0:3], 0 format:[BUF_DATA_FORMAT_32_32_32,BUF_NUM_FORMAT_SSCALED] idxen glc
9 … v[8:11], [[ZEROREG]], s[0:3], 0 format:[BUF_DATA_FORMAT_32_32_32_32,BUF_NUM_FORMAT_UINT] idxen slc
10 … v[8:11], [[ZEROREG]], s[0:3], 0 format:[BUF_DATA_FORMAT_32_32_32_32,BUF_NUM_FORMAT_UINT] idxen glc
11 …0: tbuffer_store_format_xyzw v[0:3], [[ZEROREG]], s[0:3], 0 format:[BUF_FMT_10_10_10_2_UNORM] idxen
12 …0: tbuffer_store_format_xyzw v[4:7], [[ZEROREG]], s[0:3], 0 format:[BUF_FMT_8_8_8_8_SINT] idxen glc
13 ; GFX10: tbuffer_store_format_xyzw v[8:11], [[ZEROREG]], s[0:3], 0 format:78 idxen slc
14 ; GFX10: tbuffer_store_format_xyzw v[8:11], [[ZEROREG]], s[0:3], 0 format:78 idxen glc dlc
29 … v[0:3], [[ZEROREG]], s[0:3], 0 format:[BUF_DATA_FORMAT_16_16,BUF_NUM_FORMAT_FLOAT] idxen offset:42
30 ; GFX10: tbuffer_store_format_xyzw v[0:3], [[ZEROREG]], s[0:3], 0 format:117 idxen offset:42
[all …]
Dllvm.amdgcn.struct.tbuffer.load.ll7 …ZEROREG]], {{s\[[0-9]+:[0-9]+\]}}, 0 format:[BUF_DATA_FORMAT_32_32_32_32,BUF_NUM_FORMAT_UINT] idxen
8 …]], {{s\[[0-9]+:[0-9]+\]}}, 0 format:[BUF_DATA_FORMAT_RESERVED_15,BUF_NUM_FORMAT_SSCALED] idxen glc
9 …ROREG]], {{s\[[0-9]+:[0-9]+\]}}, 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM] idxen slc
10 …ROREG]], {{s\[[0-9]+:[0-9]+\]}}, 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM] idxen glc
11 …fer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, [[ZEROREG]], {{s\[[0-9]+:[0-9]+\]}}, 0 format:78 idxen
12 …{v\[[0-9]+:[0-9]+\]}}, [[ZEROREG]], {{s\[[0-9]+:[0-9]+\]}}, 0 format:[BUF_FMT_32_32_SINT] idxen glc
13 … {{v\[[0-9]+:[0-9]+\]}}, [[ZEROREG]], {{s\[[0-9]+:[0-9]+\]}}, 0 format:[BUF_FMT_32_FLOAT] idxen slc
14 …\[[0-9]+:[0-9]+\]}}, [[ZEROREG]], {{s\[[0-9]+:[0-9]+\]}}, 0 format:[BUF_FMT_32_FLOAT] idxen glc dlc
34 … {{s\[[0-9]+:[0-9]+\]}}, 0 format:[BUF_DATA_FORMAT_32_32_32_32,BUF_NUM_FORMAT_UINT] idxen offset:42
35 …ormat_xyzw {{v\[[0-9]+:[0-9]+\]}}, [[ZEROREG]], {{s\[[0-9]+:[0-9]+\]}}, 0 format:78 idxen offset:42
[all …]
Dllvm.amdgcn.struct.buffer.atomic.ll6 ;CHECK: buffer_atomic_swap v0, {{v[0-9]+}}, s[0:3], 0 idxen glc
8 ;CHECK: buffer_atomic_swap v0, {{v[0-9]+}}, s[0:3], 0 idxen glc
11 ;CHECK: buffer_atomic_swap v0, {{v\[[0-9]+:[0-9]+\]}}, s[0:3], 0 idxen offen glc
13 ;CHECK: buffer_atomic_swap v0, {{v\[[0-9]+:[0-9]+\]}}, s[0:3], 0 idxen offen glc
15 ;CHECK: buffer_atomic_swap v0, v[1:2], s[0:3], 0 idxen offen offset:42 glc
17 ;CHECK: buffer_atomic_swap v0, {{v[0-9]+}}, s[0:3], [[SOFS]] idxen offset:4 glc
19 ;CHECK: buffer_atomic_swap v0, {{v[0-9]+}}, s[0:3], 0 idxen{{$}}
20 ;CHECK: buffer_atomic_swap v0, {{v[0-9]+}}, s[0:3], 0 idxen glc
38 ;CHECK: buffer_atomic_add v0, v1, s[0:3], 0 idxen glc{{$}}
40 ;CHECK: buffer_atomic_sub v0, v1, s[0:3], 0 idxen glc slc
[all …]
Dllvm.amdgcn.struct.tbuffer.load.d16.ll8 …, [[ZEROREG]], s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM] idxen
9 …load_format_d16_x v{{[0-9]+}}, [[ZEROREG]], s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_FMT_32_FLOAT] idxen
18 …, [[ZEROREG]], s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM] idxen
21 …, [[ZEROREG]], s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM] idxen
22 …ormat_d16_xy v[[FULL:[0-9]+]], [[ZEROREG]], s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_FMT_32_FLOAT] idxen
33 …, [[ZEROREG]], s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM] idxen
36 …, [[ZEROREG]], s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM] idxen
37 …{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, [[ZEROREG]], s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_FMT_32_FLOAT] idxen
48 …, [[ZEROREG]], s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM] idxen
51 …, [[ZEROREG]], s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM] idxen
[all …]
Dllvm.amdgcn.struct.buffer.store.ll6 ;CHECK: buffer_store_dwordx4 v[0:3], {{v[0-9]+}}, s[0:3], 0 idxen
7 ;CHECK: buffer_store_dwordx4 v[4:7], {{v[0-9]+}}, s[0:3], 0 idxen glc
8 ;CHECK: buffer_store_dwordx4 v[8:11], {{v[0-9]+}}, s[0:3], 0 idxen slc
19 ;CHECK: buffer_store_dwordx4 v[0:3], {{v[0-9]+}}, s[0:3], 0 idxen offset:42
28 ;CHECK: buffer_store_dwordx4 v[0:3], v4, s[0:3], 0 idxen
37 ;CHECK: buffer_store_dwordx4 v[0:3], v[4:5], s[0:3], 0 idxen offen
46 ;CHECK: buffer_store_dwordx4 v[0:3], v[4:5], s[0:3], 0 idxen offen
56 ;CHECK: buffer_store_dwordx4 v[0:3], v[5:6], s[0:3], 0 idxen offen
67 ;CHECK: buffer_store_dwordx4 v[0:3], v4, s[0:3], 0 idxen
69 ;CHECK: buffer_load_dwordx4 v[0:3], v5, s[0:3], 0 idxen
[all …]
Dllvm.amdgcn.struct.buffer.store.format.ll6 ;CHECK: buffer_store_format_xyzw v[0:3], {{v[0-9]+}}, s[0:3], 0 idxen
7 ;CHECK: buffer_store_format_xyzw v[4:7], {{v[0-9]+}}, s[0:3], 0 idxen glc
8 ;CHECK: buffer_store_format_xyzw v[8:11], {{v[0-9]+}}, s[0:3], 0 idxen slc
19 ;CHECK: buffer_store_format_xyzw v[0:3], {{v[0-9]+}}, s[0:3], 0 idxen offset:42
28 ;CHECK: buffer_store_format_xyzw v[0:3], v4, s[0:3], 0 idxen
37 ;CHECK: buffer_store_format_xyzw v[0:3], v[4:5], s[0:3], 0 idxen offen
46 ;CHECK: buffer_store_format_xyzw v[0:3], v[4:5], s[0:3], 0 idxen offen
56 ;CHECK: buffer_store_format_xyzw v[0:3], v[5:6], s[0:3], 0 idxen offen
67 ;CHECK: buffer_store_format_xyzw v[0:3], v4, s[0:3], 0 idxen
69 ;CHECK: buffer_load_format_xyzw v[0:3], v5, s[0:3], 0 idxen
[all …]
Dllvm.amdgcn.struct.buffer.load.format.ll5 ;CHECK: buffer_load_format_xyzw v[0:3], {{v[0-9]+}}, s[0:3], 0 idxen
6 ;CHECK: buffer_load_format_xyzw v[4:7], {{v[0-9]+}}, s[0:3], 0 idxen glc
7 ;CHECK: buffer_load_format_xyzw v[8:11], {{v[0-9]+}}, s[0:3], 0 idxen slc
21 ;CHECK: buffer_load_format_xyzw v[0:3], {{v[0-9]+}}, s[0:3], 0 idxen offset:42
30 ;CHECK-DAG: buffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, s[0:3], 60 idxen offset:40…
32 ;CHECK-DAG: buffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, s[0:3], [[OFS1]] idxen off…
34 ;CHECK-DAG: buffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, s[0:3], [[OFS2]] idxen off…
47 ;CHECK: buffer_load_format_xyzw v[0:3], v0, s[0:3], 0 idxen
56 ;CHECK: buffer_load_format_xyzw v[0:3], v[0:1], s[0:3], 0 idxen offen
65 ;CHECK: buffer_load_format_xyzw v[0:3], v[0:1], s[0:3], 0 idxen offen offset:60
[all …]
Dllvm.amdgcn.struct.buffer.load.ll5 ;CHECK: buffer_load_dwordx4 v[0:3], {{v[0-9]+}}, s[0:3], 0 idxen
6 ;CHECK: buffer_load_dwordx4 v[4:7], {{v[0-9]+}}, s[0:3], 0 idxen glc
7 ;CHECK: buffer_load_dwordx4 v[8:11], {{v[0-9]+}}, s[0:3], 0 idxen slc
21 ;CHECK: buffer_load_dwordx4 v[0:3], {{v[0-9]+}}, s[0:3], 0 idxen offset:40
31 ;CHECK: buffer_load_dwordx4 v[0:3], {{v[0-9]+}}, s[0:3], [[OFFSET]] idxen offset:4
40 ;CHECK: buffer_load_dwordx4 v[0:3], v0, s[0:3], 0 idxen
49 ;CHECK: buffer_load_dwordx4 v[0:3], v[0:1], s[0:3], 0 idxen offen
58 ;CHECK: buffer_load_dwordx4 v[0:3], v[0:1], s[0:3], 0 idxen offen offset:60
68 ;CHECK: buffer_load_dwordx4 v[0:3], v[0:1], s[0:3], 0 idxen offen
78 ;CHECK: buffer_load_dwordx4 v[0:3], v[1:2], s[0:3], 0 idxen offen
[all …]
Dllvm.amdgcn.struct.tbuffer.store.d16.ll11 …_format_d16_x v[[V_LO]], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_NUM_FORMAT_USCALED] idxen
12 …ormat_d16_x v[[V_LO]], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_FMT_10_11_11_SSCALED] idxen
25 …[[V_LO]]:[[V_HI]]{{\]}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_NUM_FORMAT_USCALED] idxen
27 …rmat_d16_xy v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_NUM_FORMAT_USCALED] idxen
28 …at_d16_xy v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_FMT_10_11_11_SSCALED] idxen
45 …\[}}[[LO]]:[[HI]]{{\]}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_NUM_FORMAT_USCALED] idxen
50 …\[}}[[LO]]:[[HI]]{{\]}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_NUM_FORMAT_USCALED] idxen
51 …}}[[LO]]:[[HI]]{{\]}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_FMT_10_11_11_SSCALED] idxen
70 …\[}}[[LO]]:[[HI]]{{\]}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_NUM_FORMAT_USCALED] idxen
74 …\[}}[[LO]]:[[HI]]{{\]}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_NUM_FORMAT_USCALED] idxen
[all …]
Dllvm.amdgcn.struct.buffer.load.format.d16.ll6 ; GCN: buffer_load_format_d16_x v{{[0-9]+}}, {{v[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen
14 …oad_format_d16_xy v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, {{v[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen
17 ; PACKED: buffer_load_format_d16_xy v[[FULL:[0-9]+]], {{v[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen
27 …ad_format_d16_xyz v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, {{v[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen
30 …ad_format_d16_xyz v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, {{v[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen
40 …d_format_d16_xyzw v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, {{v[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen
43 …d_format_d16_xyzw v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, {{v[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen
53 ; GCN: buffer_load_format_d16_x v{{[0-9]+}}, {{v[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen
Dllvm.amdgcn.buffer.atomic.ll9 ;CHECK: buffer_atomic_swap v0, v1, s[0:3], 0 idxen glc
13 ;CHECK: buffer_atomic_swap v0, v[1:2], s[0:3], 0 idxen offen glc
41 ;CHECK: buffer_atomic_swap_x2 v[3:4], v1, s[0:3], 0 idxen glc
45 ;CHECK: buffer_atomic_swap_x2 v[3:4], v[1:2], s[0:3], 0 idxen offen glc
71 ;CHECK: buffer_atomic_add v0, v1, s[0:3], 0 idxen glc
73 ;CHECK: buffer_atomic_sub v0, v1, s[0:3], 0 idxen glc
75 ;CHECK: buffer_atomic_smin v0, v1, s[0:3], 0 idxen glc
77 ;CHECK: buffer_atomic_umin v0, v1, s[0:3], 0 idxen glc
79 ;CHECK: buffer_atomic_smax v0, v1, s[0:3], 0 idxen glc
81 ;CHECK: buffer_atomic_umax v0, v1, s[0:3], 0 idxen glc
[all …]
Dllvm.amdgcn.struct.buffer.store.format.d16.ll8 ; GCN: buffer_store_format_d16_x v[[V_LO]], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen
22 …ffer_store_format_d16_xy v{{\[}}[[V_LO]]:[[V_HI]]{{\]}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen
24 ; PACKED: buffer_store_format_d16_xy v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen
42 … buffer_store_format_d16_xyz v{{\[}}[[LO]]:[[HI]]{{\]}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen
48 … buffer_store_format_d16_xyz v{{\[}}[[LO]]:[[HI]]{{\]}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen
68 …buffer_store_format_d16_xyzw v{{\[}}[[LO]]:[[HI]]{{\]}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen
73 …buffer_store_format_d16_xyzw v{{\[}}[[LO]]:[[HI]]{{\]}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen
83 ; GCN: buffer_store_format_d16_x v[[V_LO]], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen
Dllvm.amdgcn.buffer.store.format.ll28 ;CHECK: buffer_store_format_xyzw v[0:3], v4, s[0:3], 0 idxen
46 ;CHECK: buffer_store_format_xyzw v[0:3], v[4:5], s[0:3], 0 idxen offen
56 ;CHECK: buffer_store_format_xyzw v[0:3], v[5:6], s[0:3], 0 idxen offen
67 ;CHECK: buffer_store_format_xyzw v[0:3], v4, s[0:3], 0 idxen
69 ;CHECK: buffer_load_format_xyzw v[0:3], v5, s[0:3], 0 idxen
71 ;CHECK: buffer_store_format_xyzw v[0:3], v6, s[0:3], 0 idxen
82 ;CHECK: buffer_store_format_x v0, v1, s[0:3], 0 idxen
91 ;CHECK: buffer_store_format_xy v[0:1], v2, s[0:3], 0 idxen
Dllvm.amdgcn.tbuffer.store.d16.ll9 …_format_d16_x v[[V_LO]], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_NUM_FORMAT_USCALED] idxen
22 …[[V_LO]]:[[V_HI]]{{\]}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_NUM_FORMAT_USCALED] idxen
24 …rmat_d16_xy v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_NUM_FORMAT_USCALED] idxen
41 …\[}}[[LO]]:[[HI]]{{\]}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_NUM_FORMAT_USCALED] idxen
46 …\[}}[[LO]]:[[HI]]{{\]}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_NUM_FORMAT_USCALED] idxen
64 …\[}}[[LO]]:[[HI]]{{\]}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_NUM_FORMAT_USCALED] idxen
68 …\[}}[[LO]]:[[HI]]{{\]}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_NUM_FORMAT_USCALED] idxen
/external/llvm-project/llvm/test/MC/Disassembler/AMDGPU/
Dmtbuf_gfx10.txt36 # GFX10: tbuffer_load_format_xyzw v[0:3], v0, s[0:3], 0 format:78 idxen
45 # GFX10: tbuffer_load_format_xyzw v[0:3], v[0:1], s[0:3], 0 format:78 idxen offen
54 # GFX10: tbuffer_store_format_d16_x v0, v1, s[4:7], 0 format:[BUF_FMT_10_11_11_SSCALED] idxen
57 # GFX10: tbuffer_store_format_d16_xy v0, v1, s[4:7], 0 format:[BUF_FMT_10_11_11_SSCALED] idxen
60 # GFX10: tbuffer_store_format_d16_xyzw v[0:1], v2, s[4:7], 0 format:[BUF_FMT_10_11_11_SSCALED] idxen
81 # GFX10: tbuffer_store_format_xyzw v[0:3], v4, s[0:3], 0 format:[BUF_FMT_10_10_10_2_SSCALED] idxen
87 …: tbuffer_store_format_xyzw v[0:3], v[4:5], s[0:3], 0 format:[BUF_FMT_16_16_16_16_SINT] idxen offen
90 # GFX10: tbuffer_store_format_xyzw v[0:3], v4, s[0:3], 0 format:[BUF_FMT_32_32_SINT] idxen
93 # GFX10: tbuffer_store_format_xyzw v[0:3], v6, s[0:3], 0 format:[BUF_FMT_10_10_10_2_USCALED] idxen
96 # GFX10: tbuffer_store_format_x v0, v1, s[0:3], 0 format:125 idxen
[all …]
Dmubuf_vi.txt45 # VI: buffer_load_dword v1, v2, s[4:7], s1 idxen ; encoding: [0x00,0x20,0x50,0xe0,0x02,0x01,0x01,…
48 # VI: buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 ; encoding: [0x04,0x20,0x50,0xe0,0x02,0…
51 # VI: buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 glc ; encoding: [0x04,0x60,0x50,0xe0,0x…
54 # VI: buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 slc ; encoding: [0x04,0x20,0x52,0xe0,0x…
57 # VI: buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 tfe ; encoding: [0x04,0x20,0x50,0xe0,0x…
60 # VI: buffer_load_dword v1, v2, s[4:7], s1 idxen glc tfe ; encoding: [0x00,0x60,0x50,0xe0,0x02,0x…
63 # VI: buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 glc slc tfe ; encoding: [0x04,0x60,0x52…
66 # VI: buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen ; encoding: [0x00,0x30,0x50,0xe0,0x02,…
69 # VI: buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 ; encoding: [0x04,0x30,0x50,0…
72 # VI: buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 glc ; encoding: [0x04,0x70,0x…
[all …]
/external/llvm/test/MC/Disassembler/AMDGPU/
Dmubuf_vi.txt45 # VI: buffer_load_dword v1, v2, s[4:7], s1 idxen ; encoding: [0x00,0x20,0x50,0xe0,0x02,0x01,0x01,…
48 # VI: buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 ; encoding: [0x04,0x20,0x50,0xe0,0x02,0…
51 # VI: buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 glc ; encoding: [0x04,0x60,0x50,0xe0,0x…
54 # VI: buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 slc ; encoding: [0x04,0x20,0x52,0xe0,0x…
57 # VI: buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 tfe ; encoding: [0x04,0x20,0x50,0xe0,0x…
60 # VI: buffer_load_dword v1, v2, s[4:7], s1 idxen glc tfe ; encoding: [0x00,0x60,0x50,0xe0,0x02,0x…
63 # VI: buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 glc slc tfe ; encoding: [0x04,0x60,0x52…
66 # VI: buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen ; encoding: [0x00,0x30,0x50,0xe0,0x02,…
69 # VI: buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 ; encoding: [0x04,0x30,0x50,0…
72 # VI: buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 glc ; encoding: [0x04,0x70,0x…
[all …]
/external/llvm/test/CodeGen/AMDGPU/
Dllvm.amdgcn.buffer.atomic.ll8 ;CHECK: buffer_atomic_swap v0, v1, s[0:3], 0 idxen glc
12 ;CHECK: buffer_atomic_swap v0, v[1:2], s[0:3], 0 idxen offen glc
35 ;CHECK: buffer_atomic_add v0, v1, s[0:3], 0 idxen glc
37 ;CHECK: buffer_atomic_sub v0, v1, s[0:3], 0 idxen glc
39 ;CHECK: buffer_atomic_smin v0, v1, s[0:3], 0 idxen glc
41 ;CHECK: buffer_atomic_umin v0, v1, s[0:3], 0 idxen glc
43 ;CHECK: buffer_atomic_smax v0, v1, s[0:3], 0 idxen glc
45 ;CHECK: buffer_atomic_umax v0, v1, s[0:3], 0 idxen glc
47 ;CHECK: buffer_atomic_and v0, v1, s[0:3], 0 idxen glc
49 ;CHECK: buffer_atomic_or v0, v1, s[0:3], 0 idxen glc
[all …]
Dllvm.amdgcn.buffer.store.ll25 ;CHECK: buffer_store_dwordx4 v[0:3], v4, s[0:3], 0 idxen
41 ;CHECK: buffer_store_dwordx4 v[0:3], v[4:5], s[0:3], 0 idxen offen
50 ;CHECK: buffer_store_dwordx4 v[0:3], v[5:6], s[0:3], 0 idxen offen
60 ;CHECK: buffer_store_dwordx4 v[0:3], v4, s[0:3], 0 idxen
62 ;CHECK: buffer_load_dwordx4 v[0:3], v5, s[0:3], 0 idxen
64 ;CHECK: buffer_store_dwordx4 v[0:3], v6, s[0:3], 0 idxen
74 ;CHECK: buffer_store_dword v0, v1, s[0:3], 0 idxen
82 ;CHECK: buffer_store_dwordx2 v[0:1], v2, s[0:3], 0 idxen
Dllvm.amdgcn.buffer.store.format.ll25 ;CHECK: buffer_store_format_xyzw v[0:3], v4, s[0:3], 0 idxen
41 ;CHECK: buffer_store_format_xyzw v[0:3], v[4:5], s[0:3], 0 idxen offen
50 ;CHECK: buffer_store_format_xyzw v[0:3], v[5:6], s[0:3], 0 idxen offen
60 ;CHECK: buffer_store_format_xyzw v[0:3], v4, s[0:3], 0 idxen
62 ;CHECK: buffer_load_format_xyzw v[0:3], v5, s[0:3], 0 idxen
64 ;CHECK: buffer_store_format_xyzw v[0:3], v6, s[0:3], 0 idxen
74 ;CHECK: buffer_store_format_x v0, v1, s[0:3], 0 idxen
82 ;CHECK: buffer_store_format_xy v[0:1], v2, s[0:3], 0 idxen
/external/llvm-project/llvm/docs/AMDGPU/
Dgfx7_addr_buf.rst15 …`addr64<amdgpu_synid_addr64>`, :ref:`offen<amdgpu_synid_offen>` and :ref:`idxen<amdgpu_synid_idxen…
18 * If only :ref:`idxen<amdgpu_synid_idxen>` is specified, this operand supplies an index. Size is 1 …
20 * If both :ref:`idxen<amdgpu_synid_idxen>` and :ref:`offen<amdgpu_synid_offen>` are specified, inde…

1234