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/external/llvm/test/MC/Mips/
Dmips-expansions.s144 # CHECK-BE: lbu $8, 1($zero) # encoding: [0x90,0x08,0x00,0x01]
148 # CHECK-LE: lbu $8, 0($zero) # encoding: [0x00,0x00,0x08,0x90]
154 # CHECK-BE: lbu $8, 3($zero) # encoding: [0x90,0x08,0x00,0x03]
158 # CHECK-LE: lbu $8, 2($zero) # encoding: [0x02,0x00,0x08,0x90]
165 # CHECK-BE: lbu $1, 1($1) # encoding: [0x90,0x21,0x00,0x01]
170 # CHECK-LE: lbu $1, 0($1) # encoding: [0x00,0x00,0x21,0x90]
176 # CHECK-BE: lbu $8, -32767($zero) # encoding: [0x90,0x08,0x80,0x01]
180 # CHECK-LE: lbu $8, -32768($zero) # encoding: [0x00,0x80,0x08,0x90]
187 # CHECK-BE: lbu $1, 1($1) # encoding: [0x90,0x21,0x00,0x01]
192 # CHECK-LE: lbu $1, 0($1) # encoding: [0x00,0x00,0x21,0x90]
[all …]
Dmips64-expansions.s104 # CHECK: lbu $8, 1($1) # encoding: [0x01,0x00,0x28,0x90]
105 # CHECK: lbu $1, 0($1) # encoding: [0x00,0x00,0x21,0x90]
116 # CHECK: lbu $8, 1($1) # encoding: [0x01,0x00,0x28,0x90]
117 # CHECK: lbu $1, 0($1) # encoding: [0x00,0x00,0x21,0x90]
127 # CHECK: lbu $8, 1($1) # encoding: [0x01,0x00,0x28,0x90]
128 # CHECK: lbu $1, 0($1) # encoding: [0x00,0x00,0x21,0x90]
139 # CHECK: lbu $8, 1($1) # encoding: [0x01,0x00,0x28,0x90]
140 # CHECK: lbu $1, 0($1) # encoding: [0x00,0x00,0x21,0x90]
151 # CHECK: lbu $8, 1($1) # encoding: [0x01,0x00,0x28,0x90]
152 # CHECK: lbu $1, 0($1) # encoding: [0x00,0x00,0x21,0x90]
[all …]
Dmips-memory-instructions.s28 # CHECK: lbu $4, 4($5) # encoding: [0x04,0x00,0xa4,0x90]
38 lbu $4, 4($5)
Dmicromips-loadstore-instructions.s13 # CHECK-EL: lbu $6, 8($4) # encoding: [0xc4,0x14,0x08,0x00]
59 # CHECK-EB: lbu $6, 8($4) # encoding: [0x14,0xc4,0x00,0x08]
102 lbu $6, 8($4)
/external/llvm-project/llvm/test/MC/Mips/
Dmips-expansions.s27 lbu $4, 0x8000
29 # CHECK-LE: lbu $4, -32768($4) # encoding: [0x00,0x80,0x84,0x90]
31 lbu $4, 0x20004($3)
34 # CHECK-LE: lbu $4, 4($4) # encoding: [0x04,0x00,0x84,0x90]
303 # CHECK-BE: lbu $8, 1($zero) # encoding: [0x90,0x08,0x00,0x01]
307 # CHECK-LE: lbu $8, 0($zero) # encoding: [0x00,0x00,0x08,0x90]
313 # CHECK-BE: lbu $8, 3($zero) # encoding: [0x90,0x08,0x00,0x03]
317 # CHECK-LE: lbu $8, 2($zero) # encoding: [0x02,0x00,0x08,0x90]
324 # CHECK-BE: lbu $1, 1($1) # encoding: [0x90,0x21,0x00,0x01]
329 # CHECK-LE: lbu $1, 0($1) # encoding: [0x00,0x00,0x21,0x90]
[all …]
Dmips64-expansions.s107 # CHECK: lbu $8, 1($1) # encoding: [0x01,0x00,0x28,0x90]
108 # CHECK: lbu $1, 0($1) # encoding: [0x00,0x00,0x21,0x90]
119 # CHECK: lbu $8, 1($1) # encoding: [0x01,0x00,0x28,0x90]
120 # CHECK: lbu $1, 0($1) # encoding: [0x00,0x00,0x21,0x90]
130 # CHECK: lbu $8, 1($1) # encoding: [0x01,0x00,0x28,0x90]
131 # CHECK: lbu $1, 0($1) # encoding: [0x00,0x00,0x21,0x90]
142 # CHECK: lbu $8, 1($1) # encoding: [0x01,0x00,0x28,0x90]
143 # CHECK: lbu $1, 0($1) # encoding: [0x00,0x00,0x21,0x90]
154 # CHECK: lbu $8, 1($1) # encoding: [0x01,0x00,0x28,0x90]
155 # CHECK: lbu $1, 0($1) # encoding: [0x00,0x00,0x21,0x90]
[all …]
Dmips-memory-instructions.s28 # CHECK: lbu $4, 4($5) # encoding: [0x04,0x00,0xa4,0x90]
38 lbu $4, 4($5)
/external/llvm/test/CodeGen/Mips/
Dunalignedload.ll20 ; MIPS32-EL-DAG: lbu $[[PART1:[0-9]+]], 2($[[R0]])
21 ; MIPS32-EL-DAG: lbu $[[PART2:[0-9]+]], 3($[[R0]])
25 ; MIPS32-EB-DAG: lbu $[[PART1:[0-9]+]], 2($[[R0]])
26 ; MIPS32-EB-DAG: lbu $[[PART2:[0-9]+]], 3($[[R0]])
45 ; MIPS32-EL-DAG: lbu $[[T0:[0-9]+]], 4($[[R2]])
46 ; MIPS32-EL-DAG: lbu $[[T1:[0-9]+]], 5($[[R2]])
47 ; MIPS32-EL-DAG: lbu $[[T2:[0-9]+]], 6($[[R2]])
55 ; MIPS32-EB-DAG: lbu $[[T0:[0-9]+]], 4($[[R2]])
56 ; MIPS32-EB-DAG: lbu $[[T1:[0-9]+]], 5($[[R2]])
57 ; MIPS32-EB-DAG: lbu $[[T2:[0-9]+]], 6($[[R2]])
[all …]
Dload-store-left-right.ll255 ; ALL-DAG: lbu $[[R1:[0-9]+]], 0($[[PTR]])
257 ; ALL-DAG: lbu $[[R1:[0-9]+]], 1($[[PTR]])
271 ; MIPS32-DAG: lbu $[[R1:[0-9]+]], 0($[[PTR]])
273 ; MIPS32-DAG: lbu $[[R1:[0-9]+]], 1($[[PTR]])
275 ; MIPS32-DAG: lbu $[[R1:[0-9]+]], 2($[[PTR]])
277 ; MIPS32-DAG: lbu $[[R1:[0-9]+]], 3($[[PTR]])
288 ; MIPS64-DAG: lbu $[[R1:[0-9]+]], 0($[[PTR]])
290 ; MIPS64-DAG: lbu $[[R1:[0-9]+]], 1($[[PTR]])
292 ; MIPS64-DAG: lbu $[[R1:[0-9]+]], 2($[[PTR]])
294 ; MIPS64-DAG: lbu $[[R1:[0-9]+]], 3($[[PTR]])
[all …]
/external/llvm-project/llvm/test/CodeGen/Mips/
Dunalignedload.ll20 ; MIPS32-EL-DAG: lbu $[[PART1:[0-9]+]], 2($[[R0]])
21 ; MIPS32-EL-DAG: lbu $[[PART2:[0-9]+]], 3($[[R0]])
25 ; MIPS32-EB-DAG: lbu $[[PART1:[0-9]+]], 2($[[R0]])
26 ; MIPS32-EB-DAG: lbu $[[PART2:[0-9]+]], 3($[[R0]])
45 ; MIPS32-EL-DAG: lbu $[[T0:[0-9]+]], 4($[[R2]])
46 ; MIPS32-EL-DAG: lbu $[[T1:[0-9]+]], 5($[[R2]])
47 ; MIPS32-EL-DAG: lbu $[[T2:[0-9]+]], 6($[[R2]])
55 ; MIPS32-EB-DAG: lbu $[[T0:[0-9]+]], 4($[[R2]])
56 ; MIPS32-EB-DAG: lbu $[[T1:[0-9]+]], 5($[[R2]])
57 ; MIPS32-EB-DAG: lbu $[[T2:[0-9]+]], 6($[[R2]])
[all …]
Dload-store-left-right.ll299 ; MIPS32-DAG: lbu $[[R1:[0-9]+]], 0($[[PTR]])
301 ; MIPS32-DAG: lbu $[[R2:[0-9]+]], 1($[[PTR]])
307 ; MIPS64-DAG: lbu $[[R1:[0-9]+]], 0($[[PTR]])
309 ; MIPS64-DAG: lbu $[[R2:[0-9]+]], 1($[[PTR]])
332 ; MIPS32-NOLEFTRIGHT-DAG: lbu $[[R1:[0-9]+]], 0($[[PTR]])
334 ; MIPS32-NOLEFTRIGHT-DAG: lbu $[[R1:[0-9]+]], 1($[[PTR]])
336 ; MIPS32-NOLEFTRIGHT-DAG: lbu $[[R1:[0-9]+]], 2($[[PTR]])
338 ; MIPS32-NOLEFTRIGHT-DAG: lbu $[[R1:[0-9]+]], 3($[[PTR]])
370 ; MIPS64-NOLEFTRIGHT-DAG: lbu $[[R1:[0-9]+]], 0($[[PTR]])
372 ; MIPS64-NOLEFTRIGHT-DAG: lbu $[[R1:[0-9]+]], 1($[[PTR]])
[all …]
/external/llvm-project/llvm/test/CodeGen/Mips/Fast-ISel/
Dloadstoreconv.ll39 ; CHECK: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
59 ; CHECK: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
80 ; mips32r2: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
82 ; mips32: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
137 ; CHECK: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
151 ; CHECK: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
170 ; mips32r2: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
172 ; mips32: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
Dlogopm.ll39 ; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]])
40 ; CHECK-DAG: lbu $[[UB2:[0-9]+]], 0($[[UB2_ADDR]])
61 ; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]])
85 ; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]])
110 ; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]])
111 ; CHECK-DAG: lbu $[[UB2:[0-9]+]], 0($[[UB2_ADDR]])
132 ; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]])
154 ; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]])
179 ; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]])
180 ; CHECK-DAG: lbu $[[UB2:[0-9]+]], 0($[[UB2_ADDR]])
[all …]
/external/llvm/test/CodeGen/Mips/Fast-ISel/
Dloadstoreconv.ll39 ; CHECK: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
59 ; CHECK: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
80 ; mips32r2: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
82 ; mips32: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
137 ; CHECK: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
151 ; CHECK: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
170 ; mips32r2: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
172 ; mips32: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
Dlogopm.ll39 ; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]])
40 ; CHECK-DAG: lbu $[[UB2:[0-9]+]], 0($[[UB2_ADDR]])
61 ; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]])
85 ; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]])
110 ; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]])
111 ; CHECK-DAG: lbu $[[UB2:[0-9]+]], 0($[[UB2_ADDR]])
132 ; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]])
154 ; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]])
179 ; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]])
180 ; CHECK-DAG: lbu $[[UB2:[0-9]+]], 0($[[UB2_ADDR]])
[all …]
/external/llvm-project/llvm/test/CodeGen/RISCV/
Dmem.ll50 define i32 @lbu(i8 *%a) nounwind {
51 ; RV32I-LABEL: lbu:
53 ; RV32I-NEXT: lbu a1, 4(a0)
54 ; RV32I-NEXT: lbu a0, 0(a0)
124 ; RV32I-NEXT: lbu a1, 1(a0)
125 ; RV32I-NEXT: lbu a2, 2(a0)
146 ; RV32I-NEXT: lbu a1, 1(a0)
147 ; RV32I-NEXT: lbu a2, 2(a0)
Dmem64.ll52 define i64 @lbu(i8 *%a) nounwind {
53 ; RV64I-LABEL: lbu:
55 ; RV64I-NEXT: lbu a1, 4(a0)
56 ; RV64I-NEXT: lbu a0, 0(a0)
169 ; RV64I-NEXT: lbu a1, 1(a0)
170 ; RV64I-NEXT: lbu a2, 2(a0)
191 ; RV64I-NEXT: lbu a1, 1(a0)
192 ; RV64I-NEXT: lbu a2, 2(a0)
Dzext-with-load-is-free.ll5 ; TODO: lbu and lhu should be selected to avoid the unnecessary masking.
13 ; RV32I-NEXT: lbu a1, %lo(bytes)(a0)
15 ; RV32I-NEXT: lbu a0, 1(a0)
/external/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/
DtruncStore_and_aExtLoad.ll7 ; MIPS32-NEXT: lbu $2, 0($4)
29 ; MIPS32-NEXT: lbu $1, 0($5)
43 ; MIPS32-NEXT: lbu $1, 0($5)
DzextLoad_and_sextLoad.ll7 ; MIPS32-NEXT: lbu $2, 0($4)
31 ; MIPS32-NEXT: lbu $2, 0($4)
43 ; MIPS32-NEXT: lbu $2, 0($4)
/external/llvm-project/llvm/test/CodeGen/Mips/cconv/
Dvector.ll65 ; MIPS32R5EB-NEXT: lbu $1, 49($sp)
67 ; MIPS32R5EB-NEXT: lbu $1, 48($sp)
69 ; MIPS32R5EB-NEXT: lbu $1, 53($sp)
71 ; MIPS32R5EB-NEXT: lbu $1, 52($sp)
94 ; MIPS64R5EB-NEXT: lbu $1, 89($sp)
96 ; MIPS64R5EB-NEXT: lbu $1, 88($sp)
102 ; MIPS64R5EB-NEXT: lbu $3, 81($sp)
104 ; MIPS64R5EB-NEXT: lbu $3, 80($sp)
169 ; MIPS32R5EL-NEXT: lbu $1, 49($sp)
171 ; MIPS32R5EL-NEXT: lbu $1, 48($sp)
[all …]
Dreturn.ll33 ; O32-DAG: lbu $2, %lo(byte)([[R1]])
35 ; N32-DAG: lbu $2, %lo(byte)([[R1]])
37 ; N64-DAG: lbu $2, %lo(byte)([[R1]])
/external/llvm/test/CodeGen/Mips/cconv/
Dreturn.ll33 ; O32-DAG: lbu $2, %lo(byte)([[R1]])
35 ; N32-DAG: lbu $2, %lo(byte)([[R1]])
37 ; N64-DAG: lbu $2, 0([[R1]])
/external/capstone/suite/MC/Mips/
Dmicromips-loadstore-instructions.s.cs3 0xc4,0x14,0x08,0x00 = lbu $a2, 8($a0)
Dmicromips-loadstore-instructions-EB.s.cs3 0x14,0xc4,0x00,0x08 = lbu $a2, 8($a0)

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