Home
last modified time | relevance | path

Searched refs:mxcsr (Results 1 – 25 of 72) sorted by relevance

123

/external/llvm-project/llvm/test/CodeGen/X86/
Devex-to-vex-compress.mir170 ; CHECK: $ymm0 = VMULPDYrm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
171 $ymm0 = VMULPDZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
172 ; CHECK: $ymm0 = VMULPDYrr $ymm0, $ymm1, implicit $mxcsr
173 $ymm0 = VMULPDZ256rr $ymm0, $ymm1, implicit $mxcsr
174 ; CHECK: $ymm0 = VMULPSYrm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
175 $ymm0 = VMULPSZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
176 ; CHECK: $ymm0 = VMULPSYrr $ymm0, $ymm1, implicit $mxcsr
177 $ymm0 = VMULPSZ256rr $ymm0, $ymm1, implicit $mxcsr
318 ; CHECK: $ymm0 = VADDPDYrm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
319 $ymm0 = VADDPDZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
[all …]
Dsqrt-fastmath-mir.ll12 ; CHECK: %1:fr32 = nofpexcept VSQRTSSr killed [[DEF]], [[COPY]], implicit $mxcsr
26 ; CHECK: %3:fr32 = ninf nofpexcept VMULSSrr [[COPY]], [[VRSQRTSSr]], implicit $mxcsr
28 … %5:fr32 = ninf nofpexcept VFMADD213SSr [[VRSQRTSSr]], killed %3, [[VMOVSSrm_alt]], implicit $mxcsr
30 ; CHECK: %7:fr32 = ninf nofpexcept VMULSSrr [[VRSQRTSSr]], [[VMOVSSrm_alt1]], implicit $mxcsr
31 ; CHECK: %8:fr32 = ninf nofpexcept VMULSSrr killed %7, killed %5, implicit $mxcsr
32 ; CHECK: %9:fr32 = ninf nofpexcept VMULSSrr [[COPY]], %8, implicit $mxcsr
33 ; CHECK: %10:fr32 = ninf nofpexcept VFMADD213SSr %8, %9, [[VMOVSSrm_alt]], implicit $mxcsr
34 ; CHECK: %11:fr32 = ninf nofpexcept VMULSSrr %9, [[VMOVSSrm_alt1]], implicit $mxcsr
35 ; CHECK: %12:fr32 = ninf nofpexcept VMULSSrr killed %11, killed %10, implicit $mxcsr
41 …CMPSSrm killed [[COPY3]], $rip, 1, $noreg, %const.3, $noreg, 1, implicit $mxcsr :: (load 4 from co…
[all …]
Dmxcsr-reg-usage.ll5 ; CHECK: MMX_CVTPS2PIirr %{{[0-9]}}, implicit $mxcsr
6 ; CHECK: MMX_CVTPI2PSirr %{{[0-9]}}, killed %{{[0-9]}}, implicit $mxcsr
7 ; CHECK: MMX_CVTTPS2PIirr killed %{{[0-9]}}, implicit $mxcsr
9 ; CHECK: MMX_CVTPD2PIirr killed %{{[0-9]}}, implicit $mxcsr
19 ; CHECK: VCVTPS2PH{{.*}}mxcsr
25 ; CHECK: VFMADD{{.*}}mxcsr
32 ; CHECK: VFMADD{{.*}}mxcsr
39 ; CHECK: VFMADD{{.*}}mxcsr
Dvector-constrained-fp-intrinsics-flags.ll6 …2 = ADDSSrm [[MOVSSrm_alt]], $rip, 1, $noreg, %const.1, $noreg, implicit $mxcsr :: (load 4 from co…
18 ; CHECK: [[ADDSSrr:%[0-9]+]]:fr32 = ADDSSrr [[MOVSSrm_alt]], killed [[FsFLD0SS]], implicit $mxcsr
19 …2 = ADDSSrm [[MOVSSrm_alt]], $rip, 1, $noreg, %const.1, $noreg, implicit $mxcsr :: (load 4 from co…
20 …2 = ADDSSrm [[MOVSSrm_alt]], $rip, 1, $noreg, %const.2, $noreg, implicit $mxcsr :: (load 4 from co…
41 …r128 = ADDPDrm [[MOVAPDrm]], $rip, 1, $noreg, %const.1, $noreg, implicit $mxcsr :: (load 16 from c…
42 …r128 = ADDPDrm [[MOVAPDrm]], $rip, 1, $noreg, %const.2, $noreg, implicit $mxcsr :: (load 16 from c…
Dfp-intrinsics-flags.ll32 ; CHECK: COMISDrr [[MOVSDrm_alt1]], [[MOVSDrm_alt]], implicit-def $eflags, implicit $mxcsr
36 ; CHECK: [[SUBSDrr:%[0-9]+]]:fr64 = SUBSDrr [[MOVSDrm_alt]], killed [[PHI]], implicit $mxcsr
62 …-9]+]]:gr32 = CVTTSD2SIrm %fixed-stack.0, 1, $noreg, 0, $noreg, implicit $mxcsr :: (load 8 from %f…
74 …-9]+]]:gr32 = CVTTSD2SIrm %fixed-stack.0, 1, $noreg, 0, $noreg, implicit $mxcsr :: (load 8 from %f…
87 ; CHECK: COMISDrr [[MOVSDrm_alt1]], [[MOVSDrm_alt]], implicit-def $eflags, implicit $mxcsr
94 ; CHECK: [[SUBSDrr:%[0-9]+]]:fr64 = SUBSDrr [[MOVSDrm_alt]], killed [[PHI]], implicit $mxcsr
95 ; CHECK: [[CVTTSD2SIrr:%[0-9]+]]:gr32 = CVTTSD2SIrr killed [[SUBSDrr]], implicit $mxcsr
111 ; CHECK: %3:fr64 = DIVSDrm [[MOVSDrm_alt]], %fixed-stack.2, 1, $noreg, 0, $noreg, implicit $mxcsr :…
/external/llvm-project/llvm/test/CodeGen/MIR/X86/
Dfastmath.mir13 ; CHECK: %1:fr32 = nnan VMULSSrr %0, %0, implicit $mxcsr
14 %1:fr32 = nnan VMULSSrr %0, %0, implicit $mxcsr
15 ; CHECK: %2:fr32 = ninf VMULSSrr %1, %1, implicit $mxcsr
16 %2:fr32 = ninf VMULSSrr %1, %1, implicit $mxcsr
17 ; CHECK: %3:fr32 = nsz VMULSSrr %2, %2, implicit $mxcsr
18 %3:fr32 = nsz VMULSSrr %2, %2, implicit $mxcsr
19 ; CHECK: %4:fr32 = arcp VMULSSrr %3, %3, implicit $mxcsr
20 %4:fr32 = arcp VMULSSrr %3, %3, implicit $mxcsr
21 ; CHECK: %5:fr32 = contract VMULSSrr %4, %4, implicit $mxcsr
22 %5:fr32 = contract VMULSSrr %4, %4, implicit $mxcsr
[all …]
Dconstant-pool.mir64 ; CHECK: $xmm0 = ADDSDrm killed $xmm0, $rip, 1, $noreg, %const.0, $noreg, implicit $mxcsr
65 ; CHECK-NEXT: $xmm1 = ADDSSrm killed $xmm1, $rip, 1, $noreg, %const.1, $noreg, implicit $mxcsr
66 $xmm0 = ADDSDrm killed $xmm0, $rip, 1, _, %const.0, _, implicit $mxcsr
67 $xmm1 = ADDSSrm killed $xmm1, $rip, 1, _, %const.1, _, implicit $mxcsr
68 $xmm1 = CVTSS2SDrr killed $xmm1, implicit $mxcsr
69 $xmm0 = MULSDrr killed $xmm0, killed $xmm1, implicit $mxcsr
92 $xmm0 = ADDSDrm killed $xmm0, $rip, 1, _, %const.0, _, implicit $mxcsr
93 $xmm1 = ADDSSrm killed $xmm1, $rip, 1, _, %const.1, _, implicit $mxcsr
94 $xmm1 = CVTSS2SDrr killed $xmm1, implicit $mxcsr
95 $xmm0 = MULSDrr killed $xmm0, killed $xmm1, implicit $mxcsr
[all …]
Dmircanon-flags.mir26 %1:fr32 = nnan VMULSSrr %0, %0, implicit $mxcsr
27 %2:fr32 = ninf VMULSSrr %1, %1, implicit $mxcsr
28 %3:fr32 = nsz VMULSSrr %2, %2, implicit $mxcsr
29 %4:fr32 = arcp VMULSSrr %3, %3, implicit $mxcsr
30 %5:fr32 = contract VMULSSrr %4, %4, implicit $mxcsr
31 %6:fr32 = afn VMULSSrr %5, %5, implicit $mxcsr
32 %7:fr32 = reassoc VMULSSrr %6, %6, implicit $mxcsr
33 %8:fr32 = nsz arcp contract afn reassoc VMULSSrr %7, %7, implicit $mxcsr
34 %9:fr32 = contract afn reassoc VMULSSrr %8, %8, implicit $mxcsr
/external/virglrenderer/src/gallium/auxiliary/util/
Du_math.c90 unsigned mxcsr = 0; in util_fpstate_get() local
94 mxcsr = _mm_getcsr(); in util_fpstate_get()
98 return mxcsr; in util_fpstate_get()
130 util_fpstate_set(unsigned mxcsr) in util_fpstate_set() argument
134 _mm_setcsr(mxcsr); in util_fpstate_set()
/external/mesa3d/src/util/
Du_math.c92 unsigned mxcsr = 0; in util_fpstate_get() local
96 mxcsr = _mm_getcsr(); in util_fpstate_get()
100 return mxcsr; in util_fpstate_get()
132 util_fpstate_set(unsigned mxcsr) in util_fpstate_set() argument
136 _mm_setcsr(mxcsr); in util_fpstate_set()
/external/llvm-project/libc/utils/FPUtil/x86_64/
DFEnv.h144 uint32_t mxcsr = internal::getMXCSR(); in enableExcept() local
145 mxcsr &= ~(bitMask << internal::MXCSRExceptionContolBitPoistion); in enableExcept()
146 internal::writeMXCSR(mxcsr); in enableExcept()
168 uint32_t mxcsr = internal::getMXCSR(); in disableExcept() local
169 mxcsr |= (bitMask << internal::MXCSRExceptionContolBitPoistion); in disableExcept()
170 internal::writeMXCSR(mxcsr); in disableExcept()
183 uint32_t mxcsr = internal::getMXCSR(); in clearExcept() local
184 mxcsr &= ~internal::getStatusValueForExcept(excepts); in clearExcept()
185 internal::writeMXCSR(mxcsr); in clearExcept()
/external/llvm-project/llvm/test/CodeGen/X86/GlobalISel/
Dselect-fmul-scalar.mir47 ; SSE: %4:fr32 = nofpexcept MULSSrr [[COPY1]], [[COPY3]], implicit $mxcsr
56 ; AVX: %4:fr32 = nofpexcept VMULSSrr [[COPY1]], [[COPY3]], implicit $mxcsr
65 ; AVX512F: %4:fr32x = nofpexcept VMULSSZrr [[COPY1]], [[COPY3]], implicit $mxcsr
74 ; AVX512VL: %4:fr32x = nofpexcept VMULSSZrr [[COPY1]], [[COPY3]], implicit $mxcsr
116 ; SSE: %4:fr64 = nofpexcept MULSDrr [[COPY1]], [[COPY3]], implicit $mxcsr
125 ; AVX: %4:fr64 = nofpexcept VMULSDrr [[COPY1]], [[COPY3]], implicit $mxcsr
134 ; AVX512F: %4:fr64x = nofpexcept VMULSDZrr [[COPY1]], [[COPY3]], implicit $mxcsr
143 ; AVX512VL: %4:fr64x = nofpexcept VMULSDZrr [[COPY1]], [[COPY3]], implicit $mxcsr
Dselect-fadd-scalar.mir47 ; SSE: %4:fr32 = nofpexcept ADDSSrr [[COPY1]], [[COPY3]], implicit $mxcsr
56 ; AVX: %4:fr32 = nofpexcept VADDSSrr [[COPY1]], [[COPY3]], implicit $mxcsr
65 ; AVX512F: %4:fr32x = nofpexcept VADDSSZrr [[COPY1]], [[COPY3]], implicit $mxcsr
74 ; AVX512VL: %4:fr32x = nofpexcept VADDSSZrr [[COPY1]], [[COPY3]], implicit $mxcsr
116 ; SSE: %4:fr64 = nofpexcept ADDSDrr [[COPY1]], [[COPY3]], implicit $mxcsr
125 ; AVX: %4:fr64 = nofpexcept VADDSDrr [[COPY1]], [[COPY3]], implicit $mxcsr
134 ; AVX512F: %4:fr64x = nofpexcept VADDSDZrr [[COPY1]], [[COPY3]], implicit $mxcsr
143 ; AVX512VL: %4:fr64x = nofpexcept VADDSDZrr [[COPY1]], [[COPY3]], implicit $mxcsr
Dselect-fsub-scalar.mir47 ; SSE: %4:fr32 = nofpexcept SUBSSrr [[COPY1]], [[COPY3]], implicit $mxcsr
56 ; AVX: %4:fr32 = nofpexcept VSUBSSrr [[COPY1]], [[COPY3]], implicit $mxcsr
65 ; AVX512F: %4:fr32x = nofpexcept VSUBSSZrr [[COPY1]], [[COPY3]], implicit $mxcsr
74 ; AVX512VL: %4:fr32x = nofpexcept VSUBSSZrr [[COPY1]], [[COPY3]], implicit $mxcsr
116 ; SSE: %4:fr64 = nofpexcept SUBSDrr [[COPY1]], [[COPY3]], implicit $mxcsr
125 ; AVX: %4:fr64 = nofpexcept VSUBSDrr [[COPY1]], [[COPY3]], implicit $mxcsr
134 ; AVX512F: %4:fr64x = nofpexcept VSUBSDZrr [[COPY1]], [[COPY3]], implicit $mxcsr
143 ; AVX512VL: %4:fr64x = nofpexcept VSUBSDZrr [[COPY1]], [[COPY3]], implicit $mxcsr
Dselect-fdiv-scalar.mir47 ; SSE: %4:fr32 = nofpexcept DIVSSrr [[COPY1]], [[COPY3]], implicit $mxcsr
56 ; AVX: %4:fr32 = nofpexcept VDIVSSrr [[COPY1]], [[COPY3]], implicit $mxcsr
65 ; AVX512F: %4:fr32x = nofpexcept VDIVSSZrr [[COPY1]], [[COPY3]], implicit $mxcsr
74 ; AVX512VL: %4:fr32x = nofpexcept VDIVSSZrr [[COPY1]], [[COPY3]], implicit $mxcsr
116 ; SSE: %4:fr64 = nofpexcept DIVSDrr [[COPY1]], [[COPY3]], implicit $mxcsr
125 ; AVX: %4:fr64 = nofpexcept VDIVSDrr [[COPY1]], [[COPY3]], implicit $mxcsr
134 ; AVX512F: %4:fr64x = nofpexcept VDIVSDZrr [[COPY1]], [[COPY3]], implicit $mxcsr
143 ; AVX512VL: %4:fr64x = nofpexcept VDIVSDZrr [[COPY1]], [[COPY3]], implicit $mxcsr
Dx86_64-select-fptosi.mir74 ; CHECK: %3:gr32 = nofpexcept CVTTSS2SIrr [[COPY1]], implicit $mxcsr
105 ; CHECK: %3:gr32 = nofpexcept CVTTSS2SIrr [[COPY1]], implicit $mxcsr
135 ; CHECK: %2:gr32 = nofpexcept CVTTSS2SIrr [[COPY1]], implicit $mxcsr
163 ; CHECK: %2:gr64 = nofpexcept CVTTSS2SI64rr [[COPY1]], implicit $mxcsr
192 ; CHECK: %3:gr32 = nofpexcept CVTTSD2SIrr [[COPY1]], implicit $mxcsr
223 ; CHECK: %3:gr32 = nofpexcept CVTTSD2SIrr [[COPY1]], implicit $mxcsr
253 ; CHECK: %2:gr32 = nofpexcept CVTTSD2SIrr [[COPY1]], implicit $mxcsr
281 ; CHECK: %2:gr64 = nofpexcept CVTTSD2SI64rr [[COPY1]], implicit $mxcsr
Dx86_64-select-sitofp.mir64 ; CHECK: %1:fr32 = nofpexcept CVTSI2SSrr [[COPY]], implicit $mxcsr
92 ; CHECK: %1:fr32 = nofpexcept CVTSI642SSrr [[COPY]], implicit $mxcsr
148 ; CHECK: %1:fr64 = nofpexcept CVTSI642SDrr [[COPY]], implicit $mxcsr
/external/rust/crates/gdbstub/src/arch/x86/reg/
Dcore64.rs27 pub mxcsr: u32, field
69 write_bytes!(&self.mxcsr.to_le_bytes()); in gdb_serialize()
117 self.mxcsr = u32::from_le_bytes(bytes[0x214..0x218].try_into().unwrap()); in gdb_deserialize()
Dcore32.rs41 pub mxcsr: u32, field
82 write_bytes!(&self.mxcsr.to_le_bytes()); in gdb_serialize()
130 self.mxcsr = u32::from_le_bytes(bytes[0x130..0x134].try_into().unwrap()); in gdb_deserialize()
/external/pthreadpool/src/
Dthreadpool-utils.h19 uint32_t mxcsr; member
32 state.mxcsr = (uint32_t) _mm_getcsr(); in get_fpu_state()
47 _mm_setcsr((unsigned int) state.mxcsr); in set_fpu_state()
/external/llvm-project/llvm/test/CodeGen/Generic/
D2007-04-27-LargeMemObject.ll8 %mxcsr = alloca %struct..0anon, align 16 ; <%struct..0anon*> [#uses=1]
10 …deeffect "$0 $1", "=*m,*m,~{dirflag},~{fpsr},~{flags}"( %struct..0anon* %mxcsr, %struct..0anon* %…
/external/llvm/test/CodeGen/Generic/
D2007-04-27-LargeMemObject.ll8 %mxcsr = alloca %struct..0anon, align 16 ; <%struct..0anon*> [#uses=1]
10 …deeffect "$0 $1", "=*m,*m,~{dirflag},~{fpsr},~{flags}"( %struct..0anon* %mxcsr, %struct..0anon* %…
/external/google-breakpad/src/common/linux/
Dbreakpad_getcontext_unittest.cc164 COMPILE_ASSERT_EQ(offsetof(_libc_fpstate,mxcsr),offsetof(_fpstate,mxcsr), in TEST()
181 offsetof(std::remove_pointer<fpregset_t>::type,mxcsr), in TEST()
/external/llvm-project/compiler-rt/test/sanitizer_common/TestCases/Linux/
Dptrace.cpp44 if (fpregs.mxcsr) in main()
45 printf("%x\n", fpregs.mxcsr); in main()
/external/compiler-rt/test/sanitizer_common/TestCases/Linux/
Dptrace.cc42 if (fpregs.mxcsr) in main()
43 printf("%x\n", fpregs.mxcsr); in main()

123