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Searched refs:spills (Results 1 – 25 of 175) sorted by relevance

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/external/llvm-project/llvm/test/CodeGen/AArch64/
Darm64-spill-remarks.ll20 ; REMARK: remark: /tmp/kk.c:3:20: 1 spills 1 reloads generated in loop{{$}}
22 ; REMARK: remark: /tmp/kk.c:2:20: 1 spills 1 reloads generated in loop{{$}}
24 ; REMARK: remark: /tmp/kk.c:1:20: 2 spills 2 reloads generated in loop{{$}}
27 ; HOTNESS: remark: /tmp/kk.c:3:20: 1 spills 1 reloads generated in loop (hotness: 300)
29 ; HOTNESS: remark: /tmp/kk.c:2:20: 1 spills 1 reloads generated in loop (hotness: 30000)
31 ; HOTNESS: remark: /tmp/kk.c:1:20: 2 spills 2 reloads generated in loop (hotness: 300)
36 ; THRESHOLD: remark: /tmp/kk.c:2:20: 1 spills 1 reloads generated in loop (hotness: 30000)
46 ; YAML: - String: ' spills '
59 ; YAML: - String: ' spills '
72 ; YAML: - String: ' spills '
[all …]
/external/llvm/test/CodeGen/Thumb2/
Daligned-spill.ll1 ; RUN: llc < %s -mcpu=cortex-a8 -align-neon-spills=0 | FileCheck %s
2 ; RUN: llc < %s -mcpu=cortex-a8 -align-neon-spills=1 | FileCheck %s --check-prefix=NEON
27 ; Stack pointer must be updated before the spills.
32 ; This could legally happen before the spills.
58 ; Stack pointer must be updated before the spills.
85 ; Stack pointer must be updated before the spills.
/external/llvm-project/llvm/test/CodeGen/Thumb2/
Daligned-spill.ll1 ; RUN: llc < %s -mcpu=cortex-a8 -align-neon-spills=0 | FileCheck %s
2 ; RUN: llc < %s -mcpu=cortex-a8 -align-neon-spills=1 | FileCheck %s --check-prefix=NEON
27 ; Stack pointer must be updated before the spills.
32 ; This could legally happen before the spills.
58 ; Stack pointer must be updated before the spills.
85 ; Stack pointer must be updated before the spills.
/external/llvm/test/CodeGen/X86/
Dsink-cheap-instructions.ll2 ; RUN: llc < %s -mtriple=x86_64-linux -sink-insts-to-avoid-spills | FileCheck %s -check-prefix=SINK
5 ; spills.
D2003-08-03-CallArgLiveRanges.ll5 ; cause spills!
D2008-10-27-CoalescerBug.ll3 ; Now this test spills one register. But a reload in the loop is cheaper than
/external/llvm-project/llvm/test/CodeGen/X86/
Dsink-cheap-instructions.ll2 ; RUN: llc < %s -mtriple=x86_64-linux -sink-insts-to-avoid-spills | FileCheck %s -check-prefix=SINK
5 ; spills.
D2003-08-03-CallArgLiveRanges.ll5 ; cause spills!
/external/llvm/test/CodeGen/AMDGPU/
Dspill-scavenge-offset.ll8 ; When the offset of VGPR spills into scratch space gets too large, an additional SGPR
10 ; mechanism works even when many spills happen.
/external/llvm-project/llvm/test/CodeGen/SystemZ/
Dint-cmp-55.ll1 ; Check that we don't insert unnecessary CC spills
Dalias-01.ll5 ; Check that there are no spills.
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dsi-lower-sgpr-spills.mir1 # RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -run-pass=si-lower-sgpr-spills -o - %s …
Dsgpr-spill-partially-undef.mir2 # RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -run-pass=si-lower-sgpr-spills -o - %s …
/external/llvm/test/CodeGen/SystemZ/
Dalias-01.ll5 ; Check that there are no spills.
/external/llvm-project/llvm/test/CodeGen/SPARC/
Dspillsize.ll6 ; This function spills two values: %p and the materialized large constant.
/external/llvm/test/CodeGen/SPARC/
Dspillsize.ll6 ; This function spills two values: %p and the materialized large constant.
/external/llvm-project/llvm/test/DebugInfo/MIR/InstrRef/
Dsurvives-livedebugvars.mir22 # The fast register allocator puts some spills in -- these are no-ops as far
23 # as the slot indexes are concerned. It doesn't matter which side of spills
/external/llvm-project/llvm/test/CodeGen/PowerPC/
Dgpr-vsr-spill.ll1 …-mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu -ppc-enable-gpr-to-vsr-spills < %s | FileCheck …
Dframe-size.ll11 ; will fail the small-frame-size check and the function has spills).
/external/llvm-project/llvm/test/CodeGen/Hexagon/
Dcoalescing-hvx-across-calls.ll6 ; Check that this code only spills a single vector.
/external/llvm/test/CodeGen/PowerPC/
Dframe-size.ll11 ; will fail the small-frame-size check and the function has spills).
/external/llvm/test/Transforms/SLPVectorizer/AArch64/
Dload-store-q.ll6 ; spills and fills. This is the case for <2 x double>,
/external/llvm-project/llvm/test/Transforms/SLPVectorizer/AArch64/
Dload-store-q.ll6 ; spills and fills. This is the case for <2 x double>,
/external/llvm-project/llvm/test/CodeGen/ARM/
Dgpr-paired-spill-thumbinst.ll4 ; This test makes sure spills of 64-bit pairs in Thumb mode actually
/external/llvm/test/CodeGen/ARM/
Dgpr-paired-spill-thumbinst.ll4 ; This test makes sure spills of 64-bit pairs in Thumb mode actually

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