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/external/llvm-project/llvm/test/CodeGen/PowerPC/
Dvsx-partword-int-loads-and-stores.ll8 %splat.splatinsert = insertelement <16 x i8> undef, i8 %0, i32 0
9 …%splat.splat = shufflevector <16 x i8> %splat.splatinsert, <16 x i8> undef, <16 x i32> zeroinitial…
10 ret <16 x i8> %splat.splat
24 %splat.splatinsert = insertelement <8 x i16> undef, i16 %conv, i32 0
25 …%splat.splat = shufflevector <8 x i16> %splat.splatinsert, <8 x i16> undef, <8 x i32> zeroinitiali…
26 ret <8 x i16> %splat.splat
40 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0
41 …%splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitiali…
42 ret <4 x i32> %splat.splat
56 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0
[all …]
Dpower9-moves-and-splats.ll74 %splat.splatinsert = insertelement <4 x i32> undef, i32 %0, i32 0
75 …%splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitiali…
76 ret <4 x i32> %splat.splat
92 %splat.splatinsert = insertelement <4 x float> undef, float %0, i32 0
93 …%splat.splat = shufflevector <4 x float> %splat.splatinsert, <4 x float> undef, <4 x i32> zeroinit…
94 ret <4 x float> %splat.splat
114 %splat.splatinsert = insertelement <4 x i32> undef, i32 %0, i32 0
115 …%splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitiali…
116 ret <4 x i32> %splat.splat
136 %splat.splatinsert = insertelement <4 x float> undef, float %0, i32 0
[all …]
Dpr36068.ll12 %splat.splatinsert = insertelement <4 x float> undef, float %a, i32 0
13 …%splat.splat = shufflevector <4 x float> %splat.splatinsert, <4 x float> undef, <4 x i32> zeroinit…
15 %mul = fmul <4 x float> %splat.splat, %0
Dload-and-splat.ll25 %splat.splatinsert.i = insertelement <2 x double> undef, double %0, i32 0
26 …%splat.splat.i = shufflevector <2 x double> %splat.splatinsert.i, <2 x double> undef, <2 x i32> ze…
27 store <2 x double> %splat.splat.i, <2 x double>* %c, align 16
49 %splat.splatinsert.i = insertelement <4 x float> undef, float %0, i32 0
50 …%splat.splat.i = shufflevector <4 x float> %splat.splatinsert.i, <4 x float> undef, <4 x i32> zero…
51 store <4 x float> %splat.splat.i, <4 x float>* %c, align 16
73 %splat.splatinsert.i = insertelement <4 x i32> undef, i32 %0, i32 0
74 …%splat.splat.i = shufflevector <4 x i32> %splat.splatinsert.i, <4 x i32> undef, <4 x i32> zeroinit…
75 store <4 x i32> %splat.splat.i, <4 x i32>* %c, align 16
96 %splat.splatinsert.i = insertelement <2 x i64> undef, i64 %0, i32 0
[all …]
Dcombine-fneg.ll24 %splat.splatinsert = insertelement <4 x double> undef, double %a0, i32 0
25 …%splat.splat = shufflevector <4 x double> %splat.splatinsert, <4 x double> undef, <4 x i32> zeroin…
26 %div = fdiv reassoc nsz arcp ninf <4 x double> %a1, %splat.splat
Dcrash.ll28 %splat.splatinsert = insertelement <1 x i128> undef, i128 %0, i32 0
29 …%splat.splat = shufflevector <1 x i128> %splat.splatinsert, <1 x i128> undef, <1 x i32> zeroinitia…
30 %1 = bitcast <1 x i128> %splat.splat to <2 x i64>
/external/llvm-project/llvm/test/Transforms/Scalarizer/
Dvector-gep.ll48 ;CHECK: %.splat = shufflevector <4 x i16> %.splatinsert, <4 x i16> undef, <4 x i32> zeroinitializer
49 ;CHECK: %.splat[[I0]] = extractelement <4 x i16> %.splat, i32 0
50 ;CHECK: getelementptr i16, i16* %[[I0]], i16 %.splat[[I0]]
51 ;CHECK: %.splat[[I1]] = extractelement <4 x i16> %.splat, i32 1
52 ;CHECK: getelementptr i16, i16* %[[I1]], i16 %.splat[[I1]]
53 ;CHECK: %.splat[[I2]] = extractelement <4 x i16> %.splat, i32 2
54 ;CHECK: getelementptr i16, i16* %[[I2]], i16 %.splat[[I2]]
55 ;CHECK: %.splat[[I3]] = extractelement <4 x i16> %.splat, i32 3
56 ;CHECK: getelementptr i16, i16* %[[I3]], i16 %.splat[[I3]]
73 ;CHECK: %.splat = shufflevector <4 x i16*> %.splatinsert, <4 x i16*> undef, <4 x i32> zeroinitializ…
[all …]
/external/llvm-project/llvm/test/CodeGen/AArch64/
Dsve-int-arith-imm.ll15 …%splat = shufflevector <vscale x 16 x i8> %elt, <vscale x 16 x i8> undef, <vscale x 16 x i32> zero…
16 %cmp = icmp sgt <vscale x 16 x i8> %a, %splat
17 %res = select <vscale x 16 x i1> %cmp, <vscale x 16 x i8> %a, <vscale x 16 x i8> %splat
26 …%splat = shufflevector <vscale x 16 x i8> %elt, <vscale x 16 x i8> undef, <vscale x 16 x i32> zero…
27 %cmp = icmp sgt <vscale x 16 x i8> %a, %splat
28 %res = select <vscale x 16 x i1> %cmp, <vscale x 16 x i8> %a, <vscale x 16 x i8> %splat
37 …%splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroi…
38 %cmp = icmp sgt <vscale x 8 x i16> %a, %splat
39 %res = select <vscale x 8 x i1> %cmp, <vscale x 8 x i16> %a, <vscale x 8 x i16> %splat
48 …%splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroi…
[all …]
Dsve-fixed-length-splat-vector.ll33 %splat = shufflevector <8 x i8> %insert, <8 x i8> undef, <8 x i32> zeroinitializer
34 ret <8 x i8> %splat
43 %splat = shufflevector <16 x i8> %insert, <16 x i8> undef, <16 x i32> zeroinitializer
44 ret <16 x i8> %splat
54 %splat = shufflevector <32 x i8> %insert, <32 x i8> undef, <32 x i32> zeroinitializer
55 store <32 x i8> %splat, <32 x i8>* %b
74 %splat = shufflevector <64 x i8> %insert, <64 x i8> undef, <64 x i32> zeroinitializer
75 store <64 x i8> %splat, <64 x i8>* %b
86 %splat = shufflevector <128 x i8> %insert, <128 x i8> undef, <128 x i32> zeroinitializer
87 store <128 x i8> %splat, <128 x i8>* %b
[all …]
Dsve-int-imm.ll17 …%splat = shufflevector <vscale x 16 x i8> %elt, <vscale x 16 x i8> undef, <vscale x 16 x i32> zero…
18 %res = add <vscale x 16 x i8> %a, %splat
27 …%splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroi…
28 %res = add <vscale x 8 x i16> %a, %splat
37 …%splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroi…
38 %res = add <vscale x 8 x i16> %a, %splat
47 …%splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroi…
48 %res = add <vscale x 4 x i32> %a, %splat
57 …%splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroi…
58 %res = add <vscale x 4 x i32> %a, %splat
[all …]
Dsve-int-log-imm.ll17 …%splat = shufflevector <vscale x 16 x i8> %elt, <vscale x 16 x i8> undef, <vscale x 16 x i32> zero…
18 %res = or <vscale x 16 x i8> %a, %splat
27 …%splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroi…
28 %res = or <vscale x 8 x i16> %a, %splat
37 …%splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroi…
38 %res = or <vscale x 4 x i32> %a, %splat
47 …%splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroi…
48 %res = or <vscale x 2 x i64> %a, %splat
58 …%splat = shufflevector <vscale x 16 x i8> %elt, <vscale x 16 x i8> undef, <vscale x 16 x i32> zero…
59 %res = xor <vscale x 16 x i8> %a, %splat
[all …]
Dsve-intrinsics-int-compares-with-imm.ll20 …%splat = shufflevector <vscale x 16 x i8> %elt, <vscale x 16 x i8> undef, <vscale x 16 x i32> zero…
21 %out = icmp eq <vscale x 16 x i8> %a, %splat
30 …%splat = shufflevector <vscale x 16 x i8> %elt, <vscale x 16 x i8> undef, <vscale x 16 x i32> zero…
33 <vscale x 16 x i8> %splat)
42 …%splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroi…
45 <vscale x 2 x i64> %splat)
54 …%splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroi…
55 %out = icmp eq <vscale x 8 x i16> %a, %splat
64 …%splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroi…
67 <vscale x 8 x i16> %splat)
[all …]
Dmul_by_elt.ll13 %splat = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> zeroinitializer
14 %mul = fmul <4 x float> %splat, <float 3.0, float 3.0, float 3.0, float 3.0>
26 %splat = shufflevector <4 x float> %mul, <4 x float> undef, <4 x i32> zeroinitializer
27 ret <4 x float> %splat
30 ; Try different type and splat lane.
38 %splat = shufflevector <2 x double> %a, <2 x double> undef, <2 x i32> <i32 1, i32 1>
39 %mul = fmul <2 x double> %splat, <double 5.0, double 5.0>
51 %splat = shufflevector <2 x double> %mul, <2 x double> undef, <2 x i32> <i32 1, i32 1>
52 ret <2 x double> %splat
76 %splat = shufflevector <2 x double> %mul, <2 x double> undef, <2 x i32> <i32 1, i32 1>
[all …]
Dsve-vector-splat.ll14 …%splat = shufflevector <vscale x 16 x i8> %ins, <vscale x 16 x i8> undef, <vscale x 16 x i32> zero…
15 ret <vscale x 16 x i8> %splat
23 …%splat = shufflevector <vscale x 8 x i16> %ins, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroi…
24 ret <vscale x 8 x i16> %splat
32 …%splat = shufflevector <vscale x 4 x i32> %ins, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroi…
33 ret <vscale x 4 x i32> %splat
41 …%splat = shufflevector <vscale x 2 x i64> %ins, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroi…
42 ret <vscale x 2 x i64> %splat
50 …%splat = shufflevector <vscale x 16 x i8> %ins, <vscale x 16 x i8> undef, <vscale x 16 x i32> zero…
51 ret <vscale x 16 x i8> %splat
[all …]
Dsve-intrinsics-int-arith-imm.ll17 …%splat = shufflevector <vscale x 16 x i8> %elt, <vscale x 16 x i8> undef, <vscale x 16 x i32> zero…
20 <vscale x 16 x i8> %splat)
31 …%splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroi…
34 <vscale x 8 x i16> %splat)
48 …%splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroi…
51 <vscale x 8 x i16> %splat)
62 …%splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroi…
65 <vscale x 4 x i32> %splat)
79 …%splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroi…
82 <vscale x 4 x i32> %splat)
[all …]
/external/llvm-project/llvm/test/CodeGen/Thumb2/mve-intrinsics/
Ddup.ll15 %.splat = shufflevector <8 x half> %.splatinsert, <8 x half> undef, <8 x i32> zeroinitializer
16 ret <8 x half> %.splat
27 %.splat = shufflevector <4 x float> %.splatinsert, <4 x float> undef, <4 x i32> zeroinitializer
28 ret <4 x float> %.splat
38 %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> undef, <16 x i32> zeroinitializer
39 ret <16 x i8> %.splat
49 %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> undef, <8 x i32> zeroinitializer
50 ret <8 x i16> %.splat
60 %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
61 ret <4 x i32> %.splat
[all …]
/external/XNNPACK/scripts/
Dgenerate-f32-dwconv2d-chw.sh238 …d-chw/3x3p1-wasmsimd-splat.c.in -D ROW_TILE=1 -D ACCUMULATORS=1 -D X86=0 -o src/f32-dwconv2d-chw/g…
239 …d-chw/3x3p1-wasmsimd-splat.c.in -D ROW_TILE=2 -D ACCUMULATORS=1 -D X86=0 -o src/f32-dwconv2d-chw/g…
240 …d-chw/3x3p1-wasmsimd-splat.c.in -D ROW_TILE=3 -D ACCUMULATORS=1 -D X86=0 -o src/f32-dwconv2d-chw/g…
241 …d-chw/3x3p1-wasmsimd-splat.c.in -D ROW_TILE=4 -D ACCUMULATORS=1 -D X86=0 -o src/f32-dwconv2d-chw/g…
242 …d-chw/3x3p1-wasmsimd-splat.c.in -D ROW_TILE=5 -D ACCUMULATORS=1 -D X86=0 -o src/f32-dwconv2d-chw/g…
243 …d-chw/3x3p1-wasmsimd-splat.c.in -D ROW_TILE=6 -D ACCUMULATORS=1 -D X86=0 -o src/f32-dwconv2d-chw/g…
245 …d-chw/3x3p1-wasmsimd-splat.c.in -D ROW_TILE=1 -D ACCUMULATORS=2 -D X86=0 -o src/f32-dwconv2d-chw/g…
246 …d-chw/3x3p1-wasmsimd-splat.c.in -D ROW_TILE=1 -D ACCUMULATORS=3 -D X86=0 -o src/f32-dwconv2d-chw/g…
247 …d-chw/3x3p1-wasmsimd-splat.c.in -D ROW_TILE=1 -D ACCUMULATORS=4 -D X86=0 -o src/f32-dwconv2d-chw/g…
248 …d-chw/3x3p1-wasmsimd-splat.c.in -D ROW_TILE=2 -D ACCUMULATORS=2 -D X86=0 -o src/f32-dwconv2d-chw/g…
[all …]
/external/llvm-project/llvm/test/CodeGen/Mips/msa/
D3r_splat.ll1 ; Test the MSA splat intrinsics that are encoded with the 3R instruction
15 %1 = tail call <16 x i8> @llvm.mips.splat.b(<16 x i8> %0, i32 %a)
20 declare <16 x i8> @llvm.mips.splat.b(<16 x i8>, i32) nounwind
26 ; MIPS32-DAG: splat.b [[R4:\$w[0-9]+]], [[R3]][$4]
36 %1 = tail call <8 x i16> @llvm.mips.splat.h(<8 x i16> %0, i32 %a)
41 declare <8 x i16> @llvm.mips.splat.h(<8 x i16>, i32) nounwind
47 ; MIPS32-DAG: splat.h [[R4:\$w[0-9]+]], [[R3]][$4]
57 %1 = tail call <4 x i32> @llvm.mips.splat.w(<4 x i32> %0, i32 %a)
62 declare <4 x i32> @llvm.mips.splat.w(<4 x i32>, i32) nounwind
68 ; MIPS32-DAG: splat.w [[R4:\$w[0-9]+]], [[R3]][$4]
[all …]
/external/llvm/test/CodeGen/SystemZ/
Dvec-perm-01.ll1 ; Test vector splat.
5 ; Test v16i8 splat of the first element.
15 ; Test v16i8 splat of the last element.
28 ; Test v16i8 splat of an arbitrary element, using the second operand of
42 ; Test v8i16 splat of the first element.
52 ; Test v8i16 splat of the last element.
63 ; Test v8i16 splat of an arbitrary element, using the second operand of
75 ; Test v4i32 splat of the first element.
85 ; Test v4i32 splat of the last element.
95 ; Test v4i32 splat of an arbitrary element, using the second operand of
[all …]
/external/llvm-project/llvm/test/CodeGen/SystemZ/
Dvec-perm-01.ll1 ; Test vector splat.
5 ; Test v16i8 splat of the first element.
15 ; Test v16i8 splat of the last element.
28 ; Test v16i8 splat of an arbitrary element, using the second operand of
42 ; Test v8i16 splat of the first element.
52 ; Test v8i16 splat of the last element.
63 ; Test v8i16 splat of an arbitrary element, using the second operand of
75 ; Test v4i32 splat of the first element.
85 ; Test v4i32 splat of the last element.
95 ; Test v4i32 splat of an arbitrary element, using the second operand of
[all …]
/external/llvm/test/CodeGen/Mips/msa/
D3r_splat.ll1 ; Test the MSA splat intrinsics that are encoded with the 3R instruction
15 %1 = tail call <16 x i8> @llvm.mips.splat.b(<16 x i8> %0, i32 %a)
20 declare <16 x i8> @llvm.mips.splat.b(<16 x i8>, i32) nounwind
26 ; MIPS32-DAG: splat.b [[R4:\$w[0-9]+]], [[R3]][$4]
36 %1 = tail call <8 x i16> @llvm.mips.splat.h(<8 x i16> %0, i32 %a)
41 declare <8 x i16> @llvm.mips.splat.h(<8 x i16>, i32) nounwind
47 ; MIPS32-DAG: splat.h [[R4:\$w[0-9]+]], [[R3]][$4]
57 %1 = tail call <4 x i32> @llvm.mips.splat.w(<4 x i32> %0, i32 %a)
62 declare <4 x i32> @llvm.mips.splat.w(<4 x i32>, i32) nounwind
68 ; MIPS32-DAG: splat.w [[R4:\$w[0-9]+]], [[R3]][$4]
[all …]
/external/rust/crates/rand/src/distributions/
Dfloat.rs213 test_f32! { f32x2_edge_cases, f32x2, f32x2::splat(0.0), f32x2::splat(EPSILON32) }
215 test_f32! { f32x4_edge_cases, f32x4, f32x4::splat(0.0), f32x4::splat(EPSILON32) }
217 test_f32! { f32x8_edge_cases, f32x8, f32x8::splat(0.0), f32x8::splat(EPSILON32) }
219 test_f32! { f32x16_edge_cases, f32x16, f32x16::splat(0.0), f32x16::splat(EPSILON32) }
253 test_f64! { f64x2_edge_cases, f64x2, f64x2::splat(0.0), f64x2::splat(EPSILON64) }
255 test_f64! { f64x4_edge_cases, f64x4, f64x4::splat(0.0), f64x4::splat(EPSILON64) }
257 test_f64! { f64x8_edge_cases, f64x8, f64x8::splat(0.0), f64x8::splat(EPSILON64) }
/external/llvm/test/Transforms/InstCombine/
Dfast-math-scalarization.ll8 %splat.splatinsert = insertelement <4 x float> undef, float %0, i32 0
9 …%splat.splat = shufflevector <4 x float> %splat.splatinsert, <4 x float> undef, <4 x i32> zeroinit…
10 %splat.splatinsert1 = insertelement <4 x float> undef, float 3.0, i32 0
14 %x.0 = phi <4 x float> [ %splat.splat, %entry ], [ %mul, %for.body ]
/external/skia/tests/sksl/runtime/
DLoopInt.skvm2 0 r0 = splat 40A00000 (5)
3 1 r1 = splat 420C0000 (35)
4 2 r2 = splat 41700000 (15)
5 3 r3 = splat 3F800000 (1)
DLoopFloat.skvm2 0 r0 = splat 40A00000 (5)
3 1 r1 = splat 420C0000 (35)
4 2 r2 = splat 41700000 (15)
5 3 r3 = splat 3FDCCCCD (1.725)

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