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Searched refs:strided (Results 1 – 25 of 86) sorted by relevance

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/external/llvm-project/llvm/test/CodeGen/Thumb2/
Dmve-shuffleext.ll12 …%strided.vec = shufflevector <8 x i16> %src, <8 x i16> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 …
13 %out = sext <4 x i16> %strided.vec to <4 x i32>
23 …%strided.vec = shufflevector <8 x i16> %src, <8 x i16> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 …
24 %out = sext <4 x i16> %strided.vec to <4 x i32>
35 …%strided.vec = shufflevector <16 x i16> %src, <16 x i16> undef, <8 x i32> <i32 0, i32 2, i32 4, i3…
36 %out = sext <8 x i16> %strided.vec to <8 x i32>
47 …%strided.vec = shufflevector <16 x i16> %src, <16 x i16> undef, <8 x i32> <i32 1, i32 3, i32 5, i3…
48 %out = sext <8 x i16> %strided.vec to <8 x i32>
58 …%strided.vec = shufflevector <8 x i16> %src, <8 x i16> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 …
59 %out = zext <4 x i16> %strided.vec to <4 x i32>
[all …]
Dmve-vcvt16.ll77 …%strided.vec = shufflevector <4 x float> %src1, <4 x float> %src2, <8 x i32> <i32 0, i32 4, i32 1,…
78 %out = fptrunc <8 x float> %strided.vec to <8 x half>
90 …%strided.vec = shufflevector <4 x float> %src1, <4 x float> %src2, <8 x i32> <i32 4, i32 0, i32 5,…
91 %out = fptrunc <8 x float> %strided.vec to <8 x half>
104 …%strided.vec = shufflevector <8 x float> %src1, <8 x float> %src2, <16 x i32> <i32 0, i32 8, i32 1…
105 %out = fptrunc <16 x float> %strided.vec to <16 x half>
120 …%strided.vec = shufflevector <8 x float> %src1, <8 x float> %src2, <16 x i32> <i32 8, i32 0, i32 9…
121 %out = fptrunc <16 x float> %strided.vec to <16 x half>
320 …%strided.vec = shufflevector <4 x float> %val1, <4 x float> %val2, <8 x i32> <i32 0, i32 4, i32 1,…
321 %out = fptrunc <8 x float> %strided.vec to <8 x half>
[all …]
/external/llvm-project/polly/docs/experiments/matmul/
Dmatmul.polly.interchanged+tiled+vector.ll191 …%strided.vec = shufflevector <16 x float> %wide.vec21, <16 x float> undef, <4 x i32> <i32 0, i32 4…
192 …%strided.vec11 = shufflevector <16 x float> %wide.vec21, <16 x float> undef, <4 x i32> <i32 1, i32…
193 …%strided.vec12 = shufflevector <16 x float> %wide.vec21, <16 x float> undef, <4 x i32> <i32 2, i32…
194 …%strided.vec13 = shufflevector <16 x float> %wide.vec21, <16 x float> undef, <4 x i32> <i32 3, i32…
198 …%strided.vec15 = shufflevector <16 x float> %wide.vec14, <16 x float> undef, <4 x i32> <i32 0, i32…
199 …%strided.vec16 = shufflevector <16 x float> %wide.vec14, <16 x float> undef, <4 x i32> <i32 1, i32…
200 …%strided.vec17 = shufflevector <16 x float> %wide.vec14, <16 x float> undef, <4 x i32> <i32 2, i32…
201 …%strided.vec18 = shufflevector <16 x float> %wide.vec14, <16 x float> undef, <4 x i32> <i32 3, i32…
202 %11 = fmul <4 x float> %broadcast.splat20, %strided.vec15
203 %12 = fadd <4 x float> %strided.vec, %11
[all …]
Dmatmul.polly.interchanged+tiled+vector+openmp.ll272 …%strided.vec = shufflevector <16 x float> %wide.vec15, <16 x float> undef, <4 x i32> <i32 0, i32 4…
273 …%strided.vec5 = shufflevector <16 x float> %wide.vec15, <16 x float> undef, <4 x i32> <i32 1, i32 …
274 …%strided.vec6 = shufflevector <16 x float> %wide.vec15, <16 x float> undef, <4 x i32> <i32 2, i32 …
275 …%strided.vec7 = shufflevector <16 x float> %wide.vec15, <16 x float> undef, <4 x i32> <i32 3, i32 …
279 …%strided.vec9 = shufflevector <16 x float> %wide.vec8, <16 x float> undef, <4 x i32> <i32 0, i32 4…
280 …%strided.vec10 = shufflevector <16 x float> %wide.vec8, <16 x float> undef, <4 x i32> <i32 1, i32 …
281 …%strided.vec11 = shufflevector <16 x float> %wide.vec8, <16 x float> undef, <4 x i32> <i32 2, i32 …
282 …%strided.vec12 = shufflevector <16 x float> %wide.vec8, <16 x float> undef, <4 x i32> <i32 3, i32 …
283 %16 = fmul <4 x float> %broadcast.splat14, %strided.vec9
284 %17 = fadd <4 x float> %strided.vec, %16
[all …]
/external/llvm/test/CodeGen/PowerPC/
Dqpx-unal-cons-lds.ll53 …%strided.vec = shufflevector <8 x double> %wide.vec, <8 x double> undef, <4 x i32> <i32 0, i32 2, …
54 …%3 = fadd <4 x double> %strided.vec, <double 1.000000e+00, double 1.000000e+00, double 1.000000e+0…
63 …%strided.vec.1 = shufflevector <8 x double> %wide.vec.1, <8 x double> undef, <4 x i32> <i32 0, i32…
64 …%9 = fadd <4 x double> %strided.vec.1, <double 1.000000e+00, double 1.000000e+00, double 1.000000e…
73 …%strided.vec.2 = shufflevector <8 x double> %wide.vec.2, <8 x double> undef, <4 x i32> <i32 0, i32…
74 …%15 = fadd <4 x double> %strided.vec.2, <double 1.000000e+00, double 1.000000e+00, double 1.000000…
83 …%strided.vec.3 = shufflevector <8 x double> %wide.vec.3, <8 x double> undef, <4 x i32> <i32 0, i32…
84 …%21 = fadd <4 x double> %strided.vec.3, <double 1.000000e+00, double 1.000000e+00, double 1.000000…
93 …%strided.vec.4 = shufflevector <8 x double> %wide.vec.4, <8 x double> undef, <4 x i32> <i32 0, i32…
94 …%27 = fadd <4 x double> %strided.vec.4, <double 1.000000e+00, double 1.000000e+00, double 1.000000…
[all …]
Dp8altivec-shuffles-pred.ll8 %strided.vec = shufflevector <4 x i32> %wide.vec, <4 x i32> undef, <2 x i32> <i32 0, i32 2>
9 ret <2 x i32> %strided.vec
20 …%strided.vec = shufflevector <16 x i8> %wide.vec, <16 x i8> undef, <16 x i32> <i32 undef, i32 unde…
21 ret <16 x i8> %strided.vec
/external/llvm/test/CodeGen/AArch64/
Daarch64-interleaved-accesses.ll10 …%strided.v0 = shufflevector <16 x i8> %wide.vec, <16 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, …
11 …%strided.v1 = shufflevector <16 x i8> %wide.vec, <16 x i8> undef, <8 x i32> <i32 1, i32 3, i32 5, …
12 %add = add nsw <8 x i8> %strided.v0, %strided.v1
23 …%strided.v2 = shufflevector <12 x i32> %wide.vec, <12 x i32> undef, <4 x i32> <i32 2, i32 5, i32 8…
24 …%strided.v1 = shufflevector <12 x i32> %wide.vec, <12 x i32> undef, <4 x i32> <i32 1, i32 4, i32 7…
25 %add = add nsw <4 x i32> %strided.v2, %strided.v1
36 …%strided.v0 = shufflevector <16 x i32> %wide.vec, <16 x i32> undef, <4 x i32> <i32 0, i32 4, i32 8…
37 …%strided.v2 = shufflevector <16 x i32> %wide.vec, <16 x i32> undef, <4 x i32> <i32 2, i32 6, i32 1…
38 %add = add nsw <4 x i32> %strided.v0, %strided.v2
88 %strided.v0 = shufflevector <4 x i32*> %wide.vec, <4 x i32*> undef, <2 x i32> <i32 0, i32 2>
[all …]
/external/llvm-project/llvm/test/CodeGen/AArch64/
Dfalkor-hwpf-fix.mir15 $w2 = LDRWui $x1, 0 :: ("aarch64-strided-access" load 4)
36 $q2 = LD1i64 $q2, 0, $x1 :: ("aarch64-strided-access" load 4)
57 $q2 = LD1i8 $q2, 0, $x1 :: ("aarch64-strided-access" load 4)
78 $d2 = LD1Onev1d $x1 :: ("aarch64-strided-access" load 4)
99 $d2_d3 = LD1Twov1d $x1 :: ("aarch64-strided-access" load 4)
120 $q2, $q3 = LDPQi $x1, 3 :: ("aarch64-strided-access" load 4)
141 $x2, $x3 = LDPXi $x1, 3 :: ("aarch64-strided-access" load 4)
166 $x1, $w2 = LDRWpost $x1, 0 :: ("aarch64-strided-access" load 4)
188 $x1, $q2 = LD1i64_POST $q2, 0, $x1, $x1 :: ("aarch64-strided-access" load 4)
210 $x1, $q2 = LD1i8_POST $q2, 0, $x1, $x1 :: ("aarch64-strided-access" load 4)
[all …]
Dfalkor-hwpf.ll4 ; Check that strided access metadata is added to loads in inner loops when compiling for Falkor.
7 ; CHECK: load i32, i32* %gep, align 4, !falkor.strided.access !0
8 ; CHECK: load i32, i32* %gep2, align 4, !falkor.strided.access !0
34 ; Check that outer loop strided load isn't marked.
36 ; CHECK: load i32, i32* %gep, align 4, !falkor.strided.access !0
79 ; Check that non-strided load isn't marked.
81 ; CHECK: load i32, i32* %gep, align 4, !falkor.strided.access !0
/external/llvm/test/CodeGen/ARM/
Darm-interleaved-accesses.ll10 …%strided.v0 = shufflevector <16 x i8> %wide.vec, <16 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, …
11 …%strided.v1 = shufflevector <16 x i8> %wide.vec, <16 x i8> undef, <8 x i32> <i32 1, i32 3, i32 5, …
12 %add = add nsw <8 x i8> %strided.v0, %strided.v1
23 %strided.v2 = shufflevector <6 x i32> %wide.vec, <6 x i32> undef, <2 x i32> <i32 2, i32 5>
24 %strided.v1 = shufflevector <6 x i32> %wide.vec, <6 x i32> undef, <2 x i32> <i32 1, i32 4>
25 %add = add nsw <2 x i32> %strided.v2, %strided.v1
37 …%strided.v0 = shufflevector <16 x i32> %wide.vec, <16 x i32> undef, <4 x i32> <i32 0, i32 4, i32 8…
38 …%strided.v2 = shufflevector <16 x i32> %wide.vec, <16 x i32> undef, <4 x i32> <i32 2, i32 6, i32 1…
39 %add = add nsw <4 x i32> %strided.v0, %strided.v2
91 %strided.v0 = shufflevector <4 x i32*> %wide.vec, <4 x i32*> undef, <2 x i32> <i32 0, i32 2>
[all …]
/external/llvm-project/llvm/test/CodeGen/PowerPC/
Dp8altivec-shuffles-pred.ll8 %strided.vec = shufflevector <4 x i32> %wide.vec, <4 x i32> undef, <2 x i32> <i32 0, i32 2>
9 ret <2 x i32> %strided.vec
20 …%strided.vec = shufflevector <16 x i8> %wide.vec, <16 x i8> undef, <16 x i32> <i32 undef, i32 unde…
21 ret <16 x i8> %strided.vec
/external/llvm-project/llvm/test/CodeGen/MIR/AArch64/
Dtarget-memoperands.mir19 ; CHECK: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: ("aarch64-strided-access" load 4)
21 ; CHECK: G_STORE [[LOAD1]](s32), [[COPY]](p0) :: ("aarch64-strided-access" store 4)
25 %2:_(s32) = G_LOAD %0(p0) :: ("aarch64-strided-access" load 4)
27 G_STORE %2(s32), %0(p0) :: ("aarch64-strided-access" store 4)
/external/llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/
Dirtranslator-atomic-metadata.ll23 …_ADD:%[0-9]+]]:_(s32) = G_ATOMICRMW_ADD [[COPY]](p0), [[C]] :: ("aarch64-strided-access" load stor…
26 %oldval = atomicrmw add i32* %ptr, i32 1 monotonic, !falkor.strided.access !0
36 …9]+]]:_(s32) = G_ATOMICRMW_ADD [[COPY]](p0), [[C]] :: (volatile "aarch64-strided-access" load stor…
39 %oldval = atomicrmw volatile add i32* %ptr, i32 1 monotonic, !falkor.strided.access !0
65 …= G_ATOMIC_CMPXCHG_WITH_SUCCESS [[COPY]](p0), [[C]], [[C1]] :: ("aarch64-strided-access" load stor…
68 %val_success = cmpxchg i32* %addr, i32 0, i32 1 monotonic monotonic, !falkor.strided.access !0
80 …C_CMPXCHG_WITH_SUCCESS [[COPY]](p0), [[C]], [[C1]] :: (volatile "aarch64-strided-access" load stor…
83 …%val_success = cmpxchg volatile i32* %addr, i32 0, i32 1 monotonic monotonic, !falkor.strided.acce…
Dirtranslator-store-metadata.ll46 ; CHECK: G_STORE [[C]](s32), [[COPY]](p0) :: ("aarch64-strided-access" store 4 into %ir.ptr)
48 store i32 0, i32* %ptr, align 4, !falkor.strided.access !0
/external/llvm-project/llvm/test/CodeGen/X86/
Dshuffle-strided-with-offset-256.ll33 …%strided.vec = shufflevector <32 x i8> %vec, <32 x i8> undef, <16 x i32> <i32 1, i32 3, i32 5, i32…
34 store <16 x i8> %strided.vec, <16 x i8>* %S
90 …%strided.vec = shufflevector <16 x i16> %vec, <16 x i16> undef, <8 x i32> <i32 1, i32 3, i32 5, i3…
91 store <8 x i16> %strided.vec, <8 x i16>* %S
110 …%strided.vec = shufflevector <8 x i32> %vec, <8 x i32> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 …
111 store <4 x i32> %strided.vec, <4 x i32>* %S
138 …%strided.vec = shufflevector <32 x i8> %vec, <32 x i8> undef, <8 x i32> <i32 1, i32 5, i32 9, i32 …
139 store <8 x i8> %strided.vec, <8 x i8>* %S
166 …%strided.vec = shufflevector <32 x i8> %vec, <32 x i8> undef, <8 x i32> <i32 2, i32 6, i32 10, i32…
167 store <8 x i8> %strided.vec, <8 x i8>* %S
[all …]
Dshuffle-strided-with-offset-512.ll56 …%strided.vec = shufflevector <64 x i8> %vec, <64 x i8> undef, <32 x i32> <i32 1, i32 3, i32 5, i32…
57 store <32 x i8> %strided.vec, <32 x i8>* %S
106 …%strided.vec = shufflevector <32 x i16> %vec, <32 x i16> undef, <16 x i32> <i32 1, i32 3, i32 5, i…
107 store <16 x i16> %strided.vec, <16 x i16>* %S
149 …%strided.vec = shufflevector <16 x i32> %vec, <16 x i32> undef, <8 x i32> <i32 1, i32 3, i32 5, i3…
150 store <8 x i32> %strided.vec, <8 x i32>* %S
173 …%strided.vec = shufflevector <64 x i8> %vec, <64 x i8> undef, <16 x i32> <i32 1, i32 5, i32 9, i32…
174 store <16 x i8> %strided.vec, <16 x i8>* %S
197 …%strided.vec = shufflevector <64 x i8> %vec, <64 x i8> undef, <16 x i32> <i32 2, i32 6, i32 10, i3…
198 store <16 x i8> %strided.vec, <16 x i8>* %S
[all …]
Dshuffle-strided-with-offset-128.ll42 …%strided.vec = shufflevector <16 x i8> %vec, <16 x i8> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 …
43 store <8 x i8> %strided.vec, <8 x i8>* %S
78 …%strided.vec = shufflevector <8 x i16> %vec, <8 x i16> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 …
79 store <4 x i16> %strided.vec, <4 x i16>* %S
102 %strided.vec = shufflevector <4 x i32> %vec, <4 x i32> undef, <2 x i32> <i32 1, i32 3>
103 store <2 x i32> %strided.vec, <2 x i32>* %S
145 …%strided.vec = shufflevector <16 x i8> %vec, <16 x i8> undef, <4 x i32> <i32 1, i32 5, i32 9, i32 …
146 store <4 x i8> %strided.vec, <4 x i8>* %S
184 …%strided.vec = shufflevector <16 x i8> %vec, <16 x i8> undef, <4 x i32> <i32 2, i32 6, i32 10, i32…
185 store <4 x i8> %strided.vec, <4 x i8>* %S
[all …]
Dshuffle-vs-trunc-512.ll66 …%strided.vec = shufflevector <64 x i8> %vec, <64 x i8> undef, <32 x i32> <i32 0, i32 2, i32 4, i32…
67 store <32 x i8> %strided.vec, <32 x i8>* %S
119 %strided.vec = trunc <32 x i16> %bc to <32 x i8>
120 store <32 x i8> %strided.vec, <32 x i8>* %S
132 …%strided.vec = shufflevector <32 x i16> %vec, <32 x i16> undef, <16 x i32> <i32 0, i32 2, i32 4, i…
133 store <16 x i16> %strided.vec, <16 x i16>* %S
146 %strided.vec = trunc <16 x i32> %bc to <16 x i16>
147 store <16 x i16> %strided.vec, <16 x i16>* %S
159 …%strided.vec = shufflevector <16 x i32> %vec, <16 x i32> undef, <8 x i32> <i32 0, i32 2, i32 4, i3…
160 store <8 x i32> %strided.vec, <8 x i32>* %S
[all …]
Dshuffle-vs-trunc-128.ll67 …%strided.vec = shufflevector <16 x i8> %vec, <16 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 …
68 store <8 x i8> %strided.vec, <8 x i8>* %S
123 %strided.vec = trunc <8 x i16> %bc to <8 x i8>
124 store <8 x i8> %strided.vec, <8 x i8>* %S
177 …%strided.vec = shufflevector <8 x i16> %vec, <8 x i16> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 …
178 store <4 x i16> %strided.vec, <4 x i16>* %S
232 %strided.vec = trunc <4 x i32> %bc to <4 x i16>
233 store <4 x i16> %strided.vec, <4 x i16>* %S
256 %strided.vec = shufflevector <4 x i32> %vec, <4 x i32> undef, <2 x i32> <i32 0, i32 2>
257 store <2 x i32> %strided.vec, <2 x i32>* %S
[all …]
Dshuffle-vs-trunc-256.ll65 …%strided.vec = shufflevector <32 x i8> %vec, <32 x i8> undef, <16 x i32> <i32 0, i32 2, i32 4, i32…
66 store <16 x i8> %strided.vec, <16 x i8>* %S
128 %strided.vec = trunc <16 x i16> %bc to <16 x i8>
129 store <16 x i8> %strided.vec, <16 x i8>* %S
180 …%strided.vec = shufflevector <16 x i16> %vec, <16 x i16> undef, <8 x i32> <i32 0, i32 2, i32 4, i3…
181 store <8 x i16> %strided.vec, <8 x i16>* %S
244 %strided.vec = trunc <8 x i32> %bc to <8 x i16>
245 store <8 x i16> %strided.vec, <8 x i16>* %S
292 …%strided.vec = shufflevector <8 x i32> %vec, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 …
293 store <4 x i32> %strided.vec, <4 x i32>* %S
[all …]
/external/llvm-project/llvm/test/CodeGen/ARM/
Dcrash-on-pow2-shufflevector.ll20 %strided.vec = shufflevector <16 x i32> %wide.vec, <16 x i32> undef, <2 x i32> <i32 0, i32 8>
21 %bin.rdx20 = add <2 x i32> %strided.vec, %strided.vec
/external/llvm-project/mlir/test/Dialect/Affine/
Dmemref-stride-calculation.mlir54 // CHECK: MemRefType memref<5xf32, affine_map<(d0)[s0] -> (s0)>> cannot be converted to strided form
56 // CHECK: MemRefType memref<5xf32, affine_map<(d0)[s0] -> (123)>> cannot be converted to strided fo…
63 …fine_map<(d0, d1, d2)[s0, s1] -> (d0 * s0 + d1 * s1 + d2 + 1)>> cannot be converted to strided form
65 …4x5xf32, affine_map<(d0, d1, d2) -> (d0 floordiv 4 + d1 + d2)>> cannot be converted to strided form
67 …x4x5xf32, affine_map<(d0, d1, d2) -> (d0 ceildiv 4 + d1 + d2)>> cannot be converted to strided form
69 …ef<3x4x5xf32, affine_map<(d0, d1, d2) -> (d0 mod 4 + d1 + d2)>> cannot be converted to strided form
/external/llvm-project/llvm/test/Transforms/InterleavedAccess/X86/
Dinterleaved-accesses-64bits-avx.ll31 …%strided.v0 = shufflevector <16 x double> %wide.vec, <16 x double> undef, <4 x i32> <i32 0, i32 4,…
32 …%strided.v1 = shufflevector <16 x double> %wide.vec, <16 x double> undef, <4 x i32> <i32 1, i32 5,…
33 …%strided.v2 = shufflevector <16 x double> %wide.vec, <16 x double> undef, <4 x i32> <i32 2, i32 6,…
34 …%strided.v3 = shufflevector <16 x double> %wide.vec, <16 x double> undef, <4 x i32> <i32 3, i32 7,…
35 %add1 = fadd <4 x double> %strided.v0, %strided.v1
36 %add2 = fadd <4 x double> %add1, %strided.v2
37 %add3 = fadd <4 x double> %add2, %strided.v3
66 …%strided.v0 = shufflevector <16 x i64> %wide.vec, <16 x i64> undef, <4 x i32> <i32 0, i32 4, i32 8…
67 …%strided.v1 = shufflevector <16 x i64> %wide.vec, <16 x i64> undef, <4 x i32> <i32 1, i32 5, i32 9…
68 …%strided.v2 = shufflevector <16 x i64> %wide.vec, <16 x i64> undef, <4 x i32> <i32 2, i32 6, i32 1…
[all …]
/external/llvm-project/llvm/test/CodeGen/Hexagon/loop-idiom/
Dhexagon-memmove2.ll5 ; Ensure that we don't form a memcpy for strided loops. Briefly, when we taught
6 ; LoopIdiom about memmove and strided loops, this got miscompiled into a memcpy
/external/llvm-project/llvm/test/Transforms/LoopVectorize/
Dinterleaved-accesses-uniform-load.ll3 ; Make sure the vectorizer can handle this loop: The strided load is only used
35 ; CHECK: %strided.vec = shufflevector <16 x i32> %wide.vec, <16 x i32> undef, <4 x i32> <i32 0, i32…

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