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Searched refs:v2i1 (Results 1 – 25 of 87) sorted by relevance

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/external/llvm/include/llvm/CodeGen/
DMachineValueType.h59 v2i1 = 13, // 2 x i1 enumerator
104 FIRST_INTEGER_VECTOR_VALUETYPE = v2i1,
123 FIRST_VECTOR_VALUETYPE = v2i1,
317 case v2i1: in getVectorElementType()
411 case v2i1: in getVectorNumElements()
449 case v2i1: return 2; in getSizeInBits()
593 if (NumElements == 2) return MVT::v2i1; in getVectorVT()
DValueTypes.td36 def v2i1 : ValueType<2 , 13>; // 2 x i1 vector value
/external/llvm/test/Transforms/InstCombine/
Dbitreverse-fold.ll57 %x = call <2 x i1> @llvm.bitreverse.v2i1(<2 x i1> zeroinitializer)
64 %x = call <2 x i1> @llvm.bitreverse.v2i1(<2 x i1> <i1 true, i1 true>)
90 declare <2 x i1> @llvm.bitreverse.v2i1(<2 x i1>) readnone
/external/llvm-project/llvm/test/Transforms/InstSimplify/
Dbitreverse-fold.ll71 %x = call <2 x i1> @llvm.bitreverse.v2i1(<2 x i1> zeroinitializer)
78 %x = call <2 x i1> @llvm.bitreverse.v2i1(<2 x i1> <i1 true, i1 true>)
104 declare <2 x i1> @llvm.bitreverse.v2i1(<2 x i1>) readnone
/external/llvm-project/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp1420 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 1 }, in getCastInstrCost()
1421 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 1 }, in getCastInstrCost()
1433 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 2 }, in getCastInstrCost()
1434 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 2 }, in getCastInstrCost()
1447 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 2 }, // widen to zmm in getCastInstrCost()
1448 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, // widen to zmm in getCastInstrCost()
1482 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 3 }, // sext+vpslld+vptestmd in getCastInstrCost()
1486 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 3 }, // sext+vpsllq+vptestmq in getCastInstrCost()
1490 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, 2 }, // zmm vpslld+vptestmd in getCastInstrCost()
1494 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i64, 2 }, // zmm vpsllq+vptestmq in getCastInstrCost()
[all …]
DX86InstrVecCompiler.td168 def maskzeroupperv2i1 : maskzeroupper<v2i1, VK2>;
259 (v2i1 VK2:$mask), (iPTR 0))),
286 (v2i1 VK2:$mask), (iPTR 0))),
336 (v2i1 VK2:$mask), (iPTR 0))),
349 (v2i1 VK2:$mask), (iPTR 0))),
/external/llvm-project/llvm/test/CodeGen/AArch64/
Dvecreduce-bool.ll5 declare i1 @llvm.vector.reduce.and.v2i1(<2 x i1> %a)
12 declare i1 @llvm.vector.reduce.or.v2i1(<2 x i1> %a)
44 %y = call i1 @llvm.vector.reduce.and.v2i1(<2 x i1> %x)
139 %y = call i1 @llvm.vector.reduce.or.v2i1(<2 x i1> %x)
/external/llvm/lib/Target/Hexagon/
DHexagonInstrInfoVector.td14 def V2I1: PatLeaf<(v2i1 PredRegs:$R)>;
227 def: vcmp_vi1_pat<A2_vcmpweq, seteq, V2I32, v2i1>;
228 def: vcmp_vi1_pat<A2_vcmpwgt, setgt, V2I32, v2i1>;
229 def: vcmp_vi1_pat<A2_vcmpwgtu, setugt, V2I32, v2i1>;
311 def: InvertCmp_pat<A2_vcmpwgt, setlt, V2I32, v2i1>;
318 def: InvertCmp_pat<A2_vcmpwgtu, setult, V2I32, v2i1>;
322 def: Pat<(v2i1 (setne V2I32:$Rs, V2I32:$Rt)),
323 (C2_not (v2i1 (A2_vcmpbeq V2I32:$Rs, V2I32:$Rt)))>;
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Support/
DMachineValueType.h61 v2i1 = 15, // 2 x i1 enumerator
429 case v2i1: in getVectorElementType()
636 case v2i1: in getVectorNumElements()
701 case v2i1: return TypeSize::Fixed(2); in getSizeInBits()
924 if (NumElements == 2) return MVT::v2i1; in getVectorVT()
/external/llvm-project/llvm/test/Analysis/CostModel/X86/
Dreduce-xor.ll158 … an estimated cost of 3 for instruction: %V2 = call i1 @llvm.vector.reduce.xor.v2i1(<2 x i1> undef)
169 … an estimated cost of 3 for instruction: %V2 = call i1 @llvm.vector.reduce.xor.v2i1(<2 x i1> undef)
180 … an estimated cost of 3 for instruction: %V2 = call i1 @llvm.vector.reduce.xor.v2i1(<2 x i1> undef)
191 … an estimated cost of 3 for instruction: %V2 = call i1 @llvm.vector.reduce.xor.v2i1(<2 x i1> undef)
202 … an estimated cost of 3 for instruction: %V2 = call i1 @llvm.vector.reduce.xor.v2i1(<2 x i1> undef)
213 … an estimated cost of 6 for instruction: %V2 = call i1 @llvm.vector.reduce.xor.v2i1(<2 x i1> undef)
224 … an estimated cost of 6 for instruction: %V2 = call i1 @llvm.vector.reduce.xor.v2i1(<2 x i1> undef)
235 … an estimated cost of 6 for instruction: %V2 = call i1 @llvm.vector.reduce.xor.v2i1(<2 x i1> undef)
245 %V2 = call i1 @llvm.vector.reduce.xor.v2i1(<2 x i1> undef)
283 declare i1 @llvm.vector.reduce.xor.v2i1(<2 x i1>)
Dreduce-and.ll158 … an estimated cost of 2 for instruction: %V2 = call i1 @llvm.vector.reduce.and.v2i1(<2 x i1> undef)
169 … an estimated cost of 2 for instruction: %V2 = call i1 @llvm.vector.reduce.and.v2i1(<2 x i1> undef)
180 … an estimated cost of 2 for instruction: %V2 = call i1 @llvm.vector.reduce.and.v2i1(<2 x i1> undef)
191 … an estimated cost of 3 for instruction: %V2 = call i1 @llvm.vector.reduce.and.v2i1(<2 x i1> undef)
202 … an estimated cost of 3 for instruction: %V2 = call i1 @llvm.vector.reduce.and.v2i1(<2 x i1> undef)
213 … an estimated cost of 3 for instruction: %V2 = call i1 @llvm.vector.reduce.and.v2i1(<2 x i1> undef)
223 %V2 = call i1 @llvm.vector.reduce.and.v2i1(<2 x i1> undef)
261 declare i1 @llvm.vector.reduce.and.v2i1(<2 x i1>)
Dreduce-or.ll158 …d an estimated cost of 2 for instruction: %V2 = call i1 @llvm.vector.reduce.or.v2i1(<2 x i1> undef)
169 …d an estimated cost of 2 for instruction: %V2 = call i1 @llvm.vector.reduce.or.v2i1(<2 x i1> undef)
180 …d an estimated cost of 2 for instruction: %V2 = call i1 @llvm.vector.reduce.or.v2i1(<2 x i1> undef)
191 …d an estimated cost of 3 for instruction: %V2 = call i1 @llvm.vector.reduce.or.v2i1(<2 x i1> undef)
202 …d an estimated cost of 3 for instruction: %V2 = call i1 @llvm.vector.reduce.or.v2i1(<2 x i1> undef)
213 …d an estimated cost of 3 for instruction: %V2 = call i1 @llvm.vector.reduce.or.v2i1(<2 x i1> undef)
223 %V2 = call i1 @llvm.vector.reduce.or.v2i1(<2 x i1> undef)
261 declare i1 @llvm.vector.reduce.or.v2i1(<2 x i1>)
/external/llvm-project/llvm/include/llvm/Support/
DMachineValueType.h62 v2i1 = 16, // 2 x i1 enumerator
496 case v2i1: in getVectorElementType()
752 case v2i1: in getVectorNumElements()
825 case v2i1: return TypeSize::Fixed(2); in getSizeInBits()
1111 if (NumElements == 2) return MVT::v2i1; in getVectorVT()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86InstrVecCompiler.td168 def maskzeroupperv2i1 : maskzeroupper<v2i1, VK2>;
259 (v2i1 VK2:$mask), (iPTR 0))),
286 (v2i1 VK2:$mask), (iPTR 0))),
336 (v2i1 VK2:$mask), (iPTR 0))),
349 (v2i1 VK2:$mask), (iPTR 0))),
/external/llvm/lib/IR/
DValueTypes.cpp145 case MVT::v2i1: return "v2i1"; in getEVTString()
223 case MVT::v2i1: return VectorType::get(Type::getInt1Ty(Context), 2); in getTypeForEVT()
/external/llvm-project/llvm/test/CodeGen/SystemZ/
Dvec-move-16.ll64 ; Test a v2i1->v2i64 extension.
Dvec-move-15.ll63 ; Test a v2i1->v2i64 extension.
Dvec-and-03.ll71 ; Test a v2i1->v2i64 extension.
Dvec-move-17.ll63 ; Test a v2i64->v2i1 truncation.
Dvec-shift-07.ll71 ; Test a v2i1->v2i64 extension.
/external/llvm/test/CodeGen/SystemZ/
Dvec-move-15.ll63 ; Test a v2i1->v2i64 extension.
Dvec-move-16.ll63 ; Test a v2i1->v2i64 extension.
Dvec-and-03.ll71 ; Test a v2i1->v2i64 extension.
Dvec-move-17.ll63 ; Test a v2i64->v2i1 truncation.
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonPatterns.td80 def V2I1: PatLeaf<(v2i1 PredRegs:$R)>;
539 def: OpR_RR_pat<MI, Op, v2i1, V2I1>;
627 def: OpR_RR_pat<A2_vcmpweq, seteq, v2i1, V2I32>;
629 def: OpR_RR_pat<A2_vcmpwgt, RevCmp<setlt>, v2i1, V2I32>;
631 def: OpR_RR_pat<A2_vcmpwgt, setgt, v2i1, V2I32>;
633 def: OpR_RR_pat<A2_vcmpwgtu, RevCmp<setult>, v2i1, V2I32>;
635 def: OpR_RR_pat<A2_vcmpwgtu, setugt, v2i1, V2I32>;
699 def: OpmR_RR_pat<Outn<A2_vcmpweq>, setne, v2i1, V2I32>;
700 def: OpmR_RR_pat<Outn<A2_vcmpwgt>, setle, v2i1, V2I32>;
701 def: OpmR_RR_pat<Outn<A2_vcmpwgtu>, setule, v2i1, V2I32>;
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