Searched refs:EL3 (Results 1 – 25 of 63) sorted by relevance
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| /external/arm-trusted-firmware/docs/resources/diagrams/plantuml/ |
| D | sdei_general.puml | 11 participant EL3
15 EL2->EL3: **SDEI_INTERRUPT_BIND**(irq)
16 EL3->EL2: event number: ev
17 EL2->EL3: **SDEI_EVENT_REGISTER**(ev, handler, ...)
18 EL3->EL2: success
19 EL2->EL3: **SDEI_EVENT_ENABLE**(ev)
20 EL3->EL2: success
21 EL2->EL3: **SDEI_PE_UNMASK**()
22 EL3->EL2: 1
26 SDEI-->EL3: SDEI interrupt
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| D | sdei_explicit_dispatch.puml | 11 participant EL3
16 EL2->EL3: **SDEI_EVENT_REGISTER**(ev, handler, ...)
17 EL3->EL2: success
18 EL2->EL3: **SDEI_EVENT_ENABLE**(ev)
19 EL3->EL2: success
20 EL2->EL3: **SDEI_PE_UNMASK**()
21 EL3->EL2: 1
25 EL3<--]: **CRITICAL EVENT**
26 activate EL3 #red
27 note over EL3: Critical event triage
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| /external/arm-trusted-firmware/docs/design/ |
| D | alt-boot-flows.rst | 4 EL3 payloads alternative boot flow
16 ``EL3 payloads`` through TF-A instead. This is implemented as an alternative
17 boot flow, where a modified BL2 boots an EL3 payload, instead of loading the
19 developing EL3 baremetal code by:
25 When booting an EL3 payload on Arm standard platforms, the configuration of the
28 DRAM to the EL3 payload.
33 - Running in EL3;
42 Booting an EL3 payload
45 The EL3 payload image is a standalone image and is not part of the FIP. It is
48 - The EL3 payload may reside in non-volatile memory (NVM) and execute in
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| D | interrupt-framework-design.rst | 4 This framework is responsible for managing interrupts routed to EL3. It also
5 allows EL3 software to configure the interrupt routing behavior. Its main
9 software (Secure interrupts) to EL3, when execution is in non-secure state
11 the interrupt to either software in EL3 or Secure-EL1 depending upon the
20 exception levels lower than EL3. This could be done with or without the
35 #. Secure EL1 interrupt. This type of interrupt can be routed to EL3 or
39 #. Non-secure interrupt. This type of interrupt can be routed to EL3,
44 #. EL3 interrupt. This type of interrupt can be routed to EL3 or Secure-EL1
46 always handled in EL3.
62 in the Secure Configuration Register at EL3 (``SCR_EL3.FIQ`` and ``SCR_EL3.IRQ``
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| D | firmware-design.rst | 48 - Boot Loader stage 3-1 (BL31) *EL3 Runtime Software*
56 - Boot Loader stage 3-2 (BL32) *EL3 Runtime Software*
75 - specification of the EL3 Runtime Software (BL31 for AArch64 and BL32 for
104 stage. BL2 passes the list of the next images to execute to the *EL3 Runtime
131 This stage begins execution from the platform's reset vector at EL3. The reset
212 SYS_LED[2:1] - Exception Level (EL3=0x3, EL2=0x2, EL1=0x1, EL0=0x0)
226 to EL3 Runtime Software.
248 both External Aborts and SError Interrupts in EL3. The ``SCR.SIF`` bit is
253 ``CPTR_EL2`` register from EL2 are configured to not trap to EL3 by
255 configured not to trap to EL3 by clearing the ``CPTR_EL3.TTA`` bit.
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| /external/arm-trusted-firmware/docs/getting_started/ |
| D | psci-lib-integration-guide.rst | 7 to be integrated with EL3 Runtime Software which invokes the PSCI Library
8 interface appropriately. **EL3 Runtime Software** refers to software executing
9 at the highest secure privileged mode, which is EL3 in AArch64 or Secure SVC/
12 must adhere to `SMCCC`_. In AArch32, EL3 Runtime Software may additionally
16 integration with EL3 Runtime Software in this document is targeted towards
26 #. After cold reset, the EL3 Runtime Software performs its cold boot
34 do bookkeeping for the EL3 Runtime Software during power management.
41 context and exiting to non-secure world. If the EL3 Runtime Software needs
50 #. After warm reset, the EL3 Runtime Software performs the necessary warm
81 system registers which do not require coordination with the EL3 Runtime
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| D | initial-build.rst | 72 - (AArch32 only) ``AARCH32_SP`` is the AArch32 EL3 Runtime Software and it
75 an AArch32 EL3 Runtime Software. Some AArch32 EL3 Runtime Software may
77 to integrate PSCI library with AArch32 EL3 Runtime Software can be found
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| D | build-options.rst | 52 BL2 at EL3 execution level.
206 - ``EL3_PAYLOAD_BASE``: This option enables booting an EL3 payload instead of
207 the normal boot flow. It must specify the entry point address of the EL3
208 payload. Please refer to the "Booting an EL3 payload" section for more
244 When this option is set to ``1``, EL3 allows lower ELs to access their own
245 MPAM registers without trapping into EL3. This option doesn't make use of
246 partitioning in EL3, however. Platform initialisation code should configure
247 and use partitions in EL3 as required. This option defaults to ``0``.
314 targeted at EL3. When set ``0`` (default), no exceptions are expected or
315 handled at EL3, and a panic will result. This is supported only for AArch64
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| D | rt-svc-writers-guide.rst | 1 EL3 Runtime Service Writer's Guide
7 This document describes how to add a runtime service to the EL3 Runtime
11 levels lower than EL3 will request runtime services using the Secure Monitor
19 for full details). The EL3 runtime services framework in BL31 enables the
75 The EL3 runtime services framework uses the call type and OEN to identify a
156 function must carry out any essential EL3 initialization prior to receiving a
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| /external/arm-trusted-firmware/docs/about/ |
| D | features.rst | 29 Convention`_ using an EL3 runtime services framework.
33 This library is pre-integrated with the AArch64 EL3 Runtime Software, and
34 is also suitable for integration with other AArch32 EL3 Runtime Software,
38 integration with AArch32 EL3 Runtime Software.
43 AArch64 EL3 Runtime Software must be integrated with a Secure Payload
68 - An Exception Handling Framework (EHF) that allows dispatching of EL3
80 the EL3 Runtime Software is loaded using other firmware or a separate
82 at EL3.
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| /external/arm-trusted-firmware/docs/components/ |
| D | exception-handling.rst | 5 Firmware (BL31) that are targeted at EL3, other than SMCs. The |EHF| takes care
6 of the following exceptions when targeted at EL3:
24 allows for asynchronous exceptions to be routed to EL3. As described in the
29 FIQs and IRQs routed to EL3 are not required to be handled in EL3.
32 exceptions are targeted at and handled in EL3. For instance:
47 first received by the EL3 firmware, and then dispatched to Normal world
51 suitably routed to EL3, and the Runtime Firmware (BL31) is extended to include
53 EL3. These components—referred to as *dispatchers* [#spd]_ in general—may
58 - Receive and handle exceptions entirely in EL3, meaning the exceptions
59 handling terminates in EL3.
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| D | ras.rst | 10 routed to and handled in EL3. Said errors are Synchronous External Abort (SEA),
24 exceptions resulting from platform errors in EL3. It allows the platform to
46 Uncontainable Errors, Double Fault, and errors rising from EL3 execution. Please
114 <EL3 interrupts>`.
177 ``EASE`` bits to ``SCR_EL3`` register. These were introduced to assist EL3
182 |TF-A|, for legacy reasons, executes entire EL3 with all exceptions unmasked.
183 This means that all exceptions routed to EL3 are handled immediately. |TF-A|
198 - ``EL3_EXCEPTION_HANDLING=1`` enables handling of exceptions at EL3. See
202 EL3.
205 ``plat_ea_handler``, the External Abort handler in EL3. When ``RAS_EXTENSION``
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| D | platform-interrupt-controller-API.rst | 145 for EL3 interrupts.
148 EL3 interrupts.
175 - ``INTR_TYPE_EL3``: interrupt is meant to be consumed by EL3.
206 This API should raise an EL3 SGI. The first parameter, ``sgi_num``, specifies
212 to appropriate *SGI Register* in order to raise the EL3 SGI.
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| D | sdei.rst | 38 EL3. The interrupt is handed over to the SDEI dispatcher, which then arranges to
42 the client handler completes, at which point EL3 does EOI [12].
187 The interrupts must be configured to target EL3. This means that they should
239 EL3 [7]. EL3 performs a first-level triage of the event, and a RAS component
280 - The caller of the API is a component running in EL3; for example, a RAS
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| D | secure-partition-manager.rst | 69 resides at EL3 and S-EL2 (or EL3 and S-EL1).
93 at EL3 and principally relays FF-A messages from NWd (Hypervisor or OS
99 from EL3 to S-EL1.
101 SPMD conveys FF-A protocol from EL3 to S-EL2.
266 EL3 Runtime Firmware BL31: offset=0x8CD1, size=0x13000, cmdline="--soc-fw"
446 Hypervisor. Invocation from OS Kernel ends straight at EL3. The PVM issues
448 ``MPIDR``, entry point address and a CPU context address. The EL3 PSCI layer
453 EL3 to only originate from the NWd. Thus concerning the SPMC (at secure
528 ``PSCI_CPU_ON`` service invocation. A notification is passed from EL3
535 ``PSCI_CPU_ON`` calls that are directly trapped to EL3.
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| /external/arm-trusted-firmware/docs/process/ |
| D | security-hardening.rst | 68 at Secure EL1, Secure EL2 (if implemented) and EL3.
80 The ``MDCR_EL3`` register allows EL3 to configure the PMU (among other things).
97 - The ``PMCR_EL0.DP`` bit therefore needs to be set to ``1`` when EL3 is
98 entered and ``PMCR_EL0`` needs to be saved and restored in EL3.
104 EL3, which disables counting altogether.
110 ``PMCR_EL0`` therefore needs to be saved and restored in EL3.
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| /external/arm-trusted-firmware/docs/security_advisories/ |
| D | security-advisory-tfv-7.rst | 54 For affected CPUs, this approach enables the mitigation during EL3
75 For affected CPUs, this approach also enables the mitigation during EL3
80 on entry to EL3, and restores the mitigation state of the lower exception level
81 on exit from EL3. For more information on this approach, see `Firmware
|
| D | security-advisory-tfv-5.rst | 38 to the list of saved/restored registers both when entering EL3 and also
51 whereas the EL3 was fixed in the later commits.
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| D | security-advisory-tfv-8.rst | 26 When taking an exception to EL3, BL31 saves the CPU context. The aim is to
55 request (or asynchronous exception to EL3) that used these return values.
77 in EL3 is relatively easy and cheap. Therefore, TF-A will now ensure that no
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| /external/arm-trusted-firmware/docs/plat/ |
| D | allwinner.rst | 4 Trusted Firmware-A (TF-A) implements the EL3 firmware layer for Allwinner
5 SoCs with ARMv8 cores. Only BL31 is used to provide proper EL3 setup and
|
| D | socionext-uniphier.rst | 9 TF-A provides a special mode, BL2-AT-EL3, which enables BL2 to execute at EL3.
45 3. BL2 (at EL3)
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| D | qti.rst | 4 Trusted Firmware-A (TF-A) implements the EL3 firmware layer for QTI SC7180.
|
| /external/llvm-project/polly/test/Isl/CodeGen/ |
| D | simple_vec_stride_x.ll | 69 ; CHECK: [[EL3:%[a-zA-Z0-9_]+]] = extractelement <4 x float> [[VEC4]], i32 2
70 ; CHECK: store float [[EL3]]
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| /external/arm-trusted-firmware/docs/plat/arm/juno/ |
| D | index.rst | 192 Booting an EL3 payload
195 If the EL3 payload is able to execute in place, it may be programmed in flash
202 be used to load the EL3 payload's ELF file over JTAG on Juno.
204 For more information on EL3 payloads in general, see
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| /external/arm-trusted-firmware/docs/perf/ |
| D | performance-monitoring-unit.rst | 86 - Reserved if EL3 not implemented.
105 EL3.
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