Home
last modified time | relevance | path

Searched refs:GPR (Results 1 – 25 of 452) sorted by relevance

12345678910>>...19

/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/
DRISCVInstrInfoA.td27 def GPRMemAtomic : RegisterOperand<GPR> {
39 (outs GPR:$rd), (ins GPRMemAtomic:$rs1),
54 (outs GPR:$rd), (ins GPRMemAtomic:$rs1, GPR:$rs2),
65 def : Pat<(StoreOp GPR:$rs1, StTy:$rs2), (Inst StTy:$rs2, GPR:$rs1, 0)>;
67 def : Pat<(StoreOp (add GPR:$rs1, simm12:$imm12), StTy:$rs2),
68 (Inst StTy:$rs2, GPR:$rs1, simm12:$imm12)>;
142 defm : AtomicStPat<atomic_store_8, SB, GPR>;
143 defm : AtomicStPat<atomic_store_16, SH, GPR>;
144 defm : AtomicStPat<atomic_store_32, SW, GPR>;
171 def : Pat<(atomic_load_sub_32_monotonic GPR:$addr, GPR:$incr),
[all …]
DRISCVInstrInfo.td300 (ins GPR:$rs1, GPR:$rs2, simm13_lsb0:$imm12),
309 : RVInstI<funct3, OPC_LOAD, (outs GPR:$rd), (ins GPR:$rs1, simm12:$imm12),
318 (ins GPR:$rs2, GPR:$rs1, simm12:$imm12),
323 : RVInstI<funct3, OPC_OP_IMM, (outs GPR:$rd), (ins GPR:$rs1, simm12:$imm12),
329 : RVInstIShift<arithshift, funct3, OPC_OP_IMM, (outs GPR:$rd),
330 (ins GPR:$rs1, uimmlog2xlen:$shamt), opcodestr,
336 : RVInstR<funct7, funct3, OPC_OP, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
341 : RVInstI<funct3, OPC_SYSTEM, (outs GPR:$rd), (ins csr_sysreg:$imm12, GPR:$rs1),
346 : RVInstI<funct3, OPC_SYSTEM, (outs GPR:$rd),
352 : RVInstIShiftW<arithshift, funct3, OPC_OP_IMM_32, (outs GPR:$rd),
[all …]
DRISCVInstrInfoM.td74 def : Pat<(sext_inreg (mul GPR:$rs1, GPR:$rs2), i32),
75 (MULW GPR:$rs1, GPR:$rs2)>;
84 def : Pat<(zexti32 (riscv_divuw (zexti32 GPR:$rs1), (zexti32 GPR:$rs2))),
85 (DIVU GPR:$rs1, GPR:$rs2)>;
86 def : Pat<(zexti32 (riscv_remuw (zexti32 GPR:$rs1), (zexti32 GPR:$rs2))),
87 (REMU GPR:$rs1, GPR:$rs2)>;
92 def : Pat<(srem (sexti32 GPR:$rs1), (sexti32 GPR:$rs2)),
93 (REMW GPR:$rs1, GPR:$rs2)>;
94 def : Pat<(sext_inreg (srem (sexti32 GPR:$rs1),
95 (sexti32 GPR:$rs2)), i32),
[all …]
DRISCVInstrInfoF.td96 : RVInstR<0b1010000, funct3, OPC_OP_FP, (outs GPR:$rd),
107 (ins GPR:$rs1, simm12:$imm12),
116 (ins FPR32:$rs2, GPR:$rs1, simm12:$imm12),
158 def FCVT_W_S : FPUnaryOp_r_frm<0b1100000, GPR, FPR32, "fcvt.w.s">,
162 def : FPUnaryOpDynFrmAlias<FCVT_W_S, "fcvt.w.s", GPR, FPR32>;
164 def FCVT_WU_S : FPUnaryOp_r_frm<0b1100000, GPR, FPR32, "fcvt.wu.s">,
168 def : FPUnaryOpDynFrmAlias<FCVT_WU_S, "fcvt.wu.s", GPR, FPR32>;
170 def FMV_X_W : FPUnaryOp_r<0b1110000, 0b000, GPR, FPR32, "fmv.x.w">,
179 def FCLASS_S : FPUnaryOp_r<0b1110000, 0b001, GPR, FPR32, "fclass.s">,
184 def FCVT_S_W : FPUnaryOp_r_frm<0b1101000, FPR32, GPR, "fcvt.s.w">,
[all …]
DRISCVInstrInfoD.td61 : RVInstR<0b1010001, funct3, OPC_OP_FP, (outs GPR:$rd),
73 (ins GPR:$rs1, simm12:$imm12),
82 (ins FPR64:$rs2, GPR:$rs1, simm12:$imm12),
135 def FCLASS_D : FPUnaryOp_r<0b1110001, 0b001, GPR, FPR64, "fclass.d">,
140 def FCVT_W_D : FPUnaryOp_r_frm<0b1100001, GPR, FPR64, "fcvt.w.d">,
144 def : FPUnaryOpDynFrmAlias<FCVT_W_D, "fcvt.w.d", GPR, FPR64>;
146 def FCVT_WU_D : FPUnaryOp_r_frm<0b1100001, GPR, FPR64, "fcvt.wu.d">,
150 def : FPUnaryOpDynFrmAlias<FCVT_WU_D, "fcvt.wu.d", GPR, FPR64>;
152 def FCVT_D_W : FPUnaryOp_r<0b1101001, 0b000, FPR64, GPR, "fcvt.d.w">,
157 def FCVT_D_WU : FPUnaryOp_r<0b1101001, 0b000, FPR64, GPR, "fcvt.d.wu">,
[all …]
/external/llvm-project/llvm/lib/Target/RISCV/
DRISCVInstrInfoA.td27 def GPRMemAtomic : RegisterOperand<GPR> {
39 (outs GPR:$rd), (ins GPRMemAtomic:$rs1),
54 (outs GPR:$rd), (ins GPRMemAtomic:$rs1, GPR:$rs2),
65 def : Pat<(StoreOp GPR:$rs1, StTy:$rs2), (Inst StTy:$rs2, GPR:$rs1, 0)>;
67 def : Pat<(StoreOp (add GPR:$rs1, simm12:$imm12), StTy:$rs2),
68 (Inst StTy:$rs2, GPR:$rs1, simm12:$imm12)>;
142 defm : AtomicStPat<atomic_store_8, SB, GPR>;
143 defm : AtomicStPat<atomic_store_16, SH, GPR>;
144 defm : AtomicStPat<atomic_store_32, SW, GPR>;
171 def : Pat<(atomic_load_sub_32_monotonic GPR:$addr, GPR:$incr),
[all …]
DRISCVInstrInfoB.td110 : RVInstR<funct7, funct3, opcode, (outs GPR:$rd), (ins GPR:$rs1),
117 : RVInstI<funct3, OPC_OP_IMM_32, (outs GPR:$rd),
118 (ins GPR:$rs1, simm12:$imm12), opcodestr, "$rd, $rs1, $imm12">;
123 : RVInstI<funct3, opcode, (outs GPR:$rd),
124 (ins GPR:$rs1, uimmlog2xlen:$shamt), opcodestr,
139 : RVInstI<funct3, opcode, (outs GPR:$rd), (ins GPR:$rs1, uimm5:$shamt),
150 : RVInstI<funct3, opcode, (outs GPR:$rd), (ins GPR:$rs1, shfl_uimm:$shamt),
161 : RVInstR4<funct2, opcode, (outs GPR:$rd),
162 (ins GPR:$rs1, GPR:$rs2, GPR:$rs3), opcodestr, argstr> {
170 : RVInstR4<0b10, opcode, (outs GPR:$rd),
[all …]
DRISCVInstrInfo.td348 (ins GPR:$rs1, GPR:$rs2, simm13_lsb0:$imm12),
357 : RVInstI<funct3, OPC_LOAD, (outs GPR:$rd), (ins GPR:$rs1, simm12:$imm12),
366 (ins GPR:$rs2, GPR:$rs1, simm12:$imm12),
371 : RVInstI<funct3, OPC_OP_IMM, (outs GPR:$rd), (ins GPR:$rs1, simm12:$imm12),
377 : RVInstIShift<arithshift, funct3, OPC_OP_IMM, (outs GPR:$rd),
378 (ins GPR:$rs1, uimmlog2xlen:$shamt), opcodestr,
384 : RVInstR<funct7, funct3, OPC_OP, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
390 : RVInstI<funct3, OPC_SYSTEM, (outs GPR:$rd), (ins csr_sysreg:$imm12, GPR:$rs1),
396 : RVInstI<funct3, OPC_SYSTEM, (outs GPR:$rd),
402 : RVInstIShiftW<arithshift, funct3, OPC_OP_IMM_32, (outs GPR:$rd),
[all …]
DRISCVInstrInfoM.td74 def : Pat<(sext_inreg (mul GPR:$rs1, GPR:$rs2), i32),
75 (MULW GPR:$rs1, GPR:$rs2)>;
84 def : Pat<(and (riscv_divuw (assertzexti32 GPR:$rs1),
85 (assertzexti32 GPR:$rs2)), 0xffffffff),
86 (DIVU GPR:$rs1, GPR:$rs2)>;
87 def : Pat<(and (riscv_remuw (assertzexti32 GPR:$rs1),
88 (assertzexti32 GPR:$rs2)), 0xffffffff),
89 (REMU GPR:$rs1, GPR:$rs2)>;
94 def : Pat<(srem (sexti32 GPR:$rs1), (sexti32 GPR:$rs2)),
95 (REMW GPR:$rs1, GPR:$rs2)>;
[all …]
DRISCVInstrInfoF.td95 : RVInstR<0b1010000, funct3, OPC_OP_FP, (outs GPR:$rd),
106 (ins GPR:$rs1, simm12:$imm12),
115 (ins FPR32:$rs2, GPR:$rs1, simm12:$imm12),
162 def FCVT_W_S : FPUnaryOp_r_frm<0b1100000, GPR, FPR32, "fcvt.w.s">,
166 def : FPUnaryOpDynFrmAlias<FCVT_W_S, "fcvt.w.s", GPR, FPR32>;
168 def FCVT_WU_S : FPUnaryOp_r_frm<0b1100000, GPR, FPR32, "fcvt.wu.s">,
172 def : FPUnaryOpDynFrmAlias<FCVT_WU_S, "fcvt.wu.s", GPR, FPR32>;
174 def FMV_X_W : FPUnaryOp_r<0b1110000, 0b000, GPR, FPR32, "fmv.x.w">,
183 def FCLASS_S : FPUnaryOp_r<0b1110000, 0b001, GPR, FPR32, "fclass.s">,
188 def FCVT_S_W : FPUnaryOp_r_frm<0b1101000, FPR32, GPR, "fcvt.s.w">,
[all …]
DRISCVInstrInfoD.td59 : RVInstR<0b1010001, funct3, OPC_OP_FP, (outs GPR:$rd),
71 (ins GPR:$rs1, simm12:$imm12),
80 (ins FPR64:$rs2, GPR:$rs1, simm12:$imm12),
142 def FCLASS_D : FPUnaryOp_r<0b1110001, 0b001, GPR, FPR64, "fclass.d">,
147 def FCVT_W_D : FPUnaryOp_r_frm<0b1100001, GPR, FPR64, "fcvt.w.d">,
151 def : FPUnaryOpDynFrmAlias<FCVT_W_D, "fcvt.w.d", GPR, FPR64>;
153 def FCVT_WU_D : FPUnaryOp_r_frm<0b1100001, GPR, FPR64, "fcvt.wu.d">,
157 def : FPUnaryOpDynFrmAlias<FCVT_WU_D, "fcvt.wu.d", GPR, FPR64>;
159 def FCVT_D_W : FPUnaryOp_r<0b1101001, 0b000, FPR64, GPR, "fcvt.d.w">,
164 def FCVT_D_WU : FPUnaryOp_r<0b1101001, 0b000, FPR64, GPR, "fcvt.d.wu">,
[all …]
/external/llvm/lib/Target/Lanai/
DLanaiInstrInfo.td195 let MIOperandInfo = (ops GPR:$base, i32lo16s:$offset, AluOp:$Opcode);
207 let MIOperandInfo = (ops GPR:$Op1, GPR:$Op2, AluOp:$Opcode);
229 let MIOperandInfo = (ops GPR:$base, imm10:$offset, AluOp:$Opcode);
280 def LO : InstRI<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, LoExt:$imm16),
284 def HI : InstRI<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, HiExt:$imm16),
296 def R : InstRR<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, GPR:$Rs2, pred:$DDDI),
298 [(set GPR:$Rd, (OpNode GPR:$Rs1, GPR:$Rs2))]>;
304 [(set GPR:$Rd, (OpNode GPR:$Rs1, LoExt:$imm16))],
305 [(set GPR:$Rd, (OpNode GPR:$Rs1, HiExt:$imm16))]>;
309 def R : InstRR<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, GPR:$Rs2, pred:$DDDI),
[all …]
/external/llvm-project/llvm/lib/Target/Lanai/
DLanaiInstrInfo.td192 let MIOperandInfo = (ops GPR:$base, i32lo16s:$offset, AluOp:$Opcode);
204 let MIOperandInfo = (ops GPR:$Op1, GPR:$Op2, AluOp:$Opcode);
226 let MIOperandInfo = (ops GPR:$base, imm10:$offset, AluOp:$Opcode);
277 def LO : InstRI<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, LoExt:$imm16),
281 def HI : InstRI<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, HiExt:$imm16),
293 def R : InstRR<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, GPR:$Rs2, pred:$DDDI),
295 [(set GPR:$Rd, (OpNode GPR:$Rs1, GPR:$Rs2))]>;
301 [(set GPR:$Rd, (OpNode GPR:$Rs1, LoExt:$imm16))],
302 [(set GPR:$Rd, (OpNode GPR:$Rs1, HiExt:$imm16))]>;
306 def R : InstRR<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, GPR:$Rs2, pred:$DDDI),
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/
DLanaiInstrInfo.td192 let MIOperandInfo = (ops GPR:$base, i32lo16s:$offset, AluOp:$Opcode);
204 let MIOperandInfo = (ops GPR:$Op1, GPR:$Op2, AluOp:$Opcode);
226 let MIOperandInfo = (ops GPR:$base, imm10:$offset, AluOp:$Opcode);
277 def LO : InstRI<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, LoExt:$imm16),
281 def HI : InstRI<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, HiExt:$imm16),
293 def R : InstRR<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, GPR:$Rs2, pred:$DDDI),
295 [(set GPR:$Rd, (OpNode GPR:$Rs1, GPR:$Rs2))]>;
301 [(set GPR:$Rd, (OpNode GPR:$Rs1, LoExt:$imm16))],
302 [(set GPR:$Rd, (OpNode GPR:$Rs1, HiExt:$imm16))]>;
306 def R : InstRR<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, GPR:$Rs2, pred:$DDDI),
[all …]
/external/llvm-project/llvm/lib/Target/ARM/
DARMInstrInfo.td385 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
760 let MIOperandInfo = (ops GPR, i32imm);
771 let MIOperandInfo = (ops GPR, GPR, i32imm);
782 let MIOperandInfo = (ops GPR, i32imm);
1090 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
1111 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift);
1167 // FIXME: am2offset_imm should only need the immediate, not the GPR. Having
1168 // the GPR is purely vestigal at this point.
1189 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
1214 let MIOperandInfo = (ops GPR, i32imm);
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMInstrInfo.td342 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
647 let MIOperandInfo = (ops GPR, i32imm);
658 let MIOperandInfo = (ops GPR, GPR, i32imm);
669 let MIOperandInfo = (ops GPR, i32imm);
975 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
996 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift);
1052 // FIXME: am2offset_imm should only need the immediate, not the GPR. Having
1053 // the GPR is purely vestigal at this point.
1074 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
1099 let MIOperandInfo = (ops GPR, i32imm);
[all …]
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dvertex-fetch-encoding.ll6 ; EG: VTX_READ_32 T[[GPR:[0-9]]].X, T[[GPR]].X, 0, #1 ; encoding: [0x40,0x01,0x0[[GPR]],0x10,0x0[[G…
7 ; CM: VTX_READ_32 T[[GPR:[0-9]]].X, T[[GPR]].X, 0, #1 ; encoding: [0x40,0x01,0x0[[GPR]],0x00,0x0[[G…
26 ; EG: VTX_READ_32 T[[GPR:[0-9]]].X, T[[GPR]].X, 0, #3 ; encoding: [0x40,0x03,0x0[[GPR]],0x10,0x0[[G…
27 ; CM: VTX_READ_32 T[[GPR:[0-9]]].X, T[[GPR]].X, 0, #3 ; encoding: [0x40,0x03,0x0[[GPR]],0x00,0x0[[G…
36 ; EG: VTX_READ_32 T[[GPR:[0-9]]].X, T[[GPR]].X, 0, #2 ; encoding: [0x40,0x02,0x0[[GPR]],0x10,0x0[[G…
37 ; CM: VTX_READ_32 T[[GPR:[0-9]]].X, T[[GPR]].X, 0, #2 ; encoding: [0x40,0x02,0x0[[GPR]],0x00,0x0[[G…
/external/llvm/test/CodeGen/Mips/
Dfpbr.ll3 …s -march=mipsel -mcpu=mips32r6 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,GPR,32-GPR
6 ; RUN: llc < %s -march=mips64el -mcpu=mips64r6 | FileCheck %s -check-prefixes=ALL,GPR,64-GPR
16 ; 32-GPR: cmp.eq.s $[[FGRCC:f[0-9]+]], $f12, $f14
17 ; 64-GPR: cmp.eq.s $[[FGRCC:f[0-9]+]], $f12, $f13
18 ; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]]
20 ; GPR: not $[[GPRCC]], $[[GPRCC]]
21 ; 32-GPR: bnez $[[GPRCC]], $BB0_2
22 ; 64-GPR: bnezc $[[GPRCC]], $BB0_2
51 ; 32-GPR: cmp.ule.s $[[FGRCC:f[0-9]+]], $f14, $f12
52 ; 64-GPR: cmp.ule.s $[[FGRCC:f[0-9]+]], $f13, $f12
[all …]
Danalyzebranch.ll3 ; RUN: llc -march=mips -mcpu=mips32r6 < %s | FileCheck %s -check-prefixes=ALL,GPR,32-GPR
7 ; RUN: llc -march=mips64 -mcpu=mips64r6 < %s | FileCheck %s -check-prefixes=ALL,GPR,64-GPR
16 ; 32-GPR: mtc1 $zero, $[[Z:f[0-9]]]
17 ; 32-GPR: mthc1 $zero, $[[Z:f[0-9]]]
18 ; 64-GPR: dmtc1 $zero, $[[Z:f[0-9]]]
19 ; GPR: cmp.lt.d $[[FGRCC:f[0-9]+]], $[[Z]], $f12
20 ; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC]]
21 ; GPR-NOT: not $[[GPRCC]], $[[GPRCC]]
22 ; GPR: bnezc $[[GPRCC]], $BB
49 ; GPR: mtc1 $zero, $[[Z:f[0-9]]]
[all …]
/external/llvm-project/llvm/test/CodeGen/Mips/
Dfpbr.ll3 …s -march=mipsel -mcpu=mips32r6 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,GPR,32-GPR
6 ; RUN: llc < %s -march=mips64el -mcpu=mips64r6 | FileCheck %s -check-prefixes=ALL,GPR,64-GPR
17 ; 32-GPR: cmp.eq.s $[[FGRCC:f[0-9]+]], $f12, $f14
18 ; 64-GPR: cmp.eq.s $[[FGRCC:f[0-9]+]], $f12, $f13
19 ; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]]
21 ; GPR: not $[[GPRCC]], $[[GPRCC]]
22 ; 32-GPR: bnez $[[GPRCC]], $BB0_2
23 ; 64-GPR: bnezc $[[GPRCC]], .LBB0_2
53 ; 32-GPR: cmp.ule.s $[[FGRCC:f[0-9]+]], $f14, $f12
54 ; 64-GPR: cmp.ule.s $[[FGRCC:f[0-9]+]], $f13, $f12
[all …]
/external/llvm/lib/Target/ARM/
DARMInstrInfo.td360 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
561 let MIOperandInfo = (ops GPR, i32imm);
572 let MIOperandInfo = (ops GPR, GPR, i32imm);
583 let MIOperandInfo = (ops GPR, i32imm);
827 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
848 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift);
902 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
919 // FIXME: am2offset_imm should only need the immediate, not the GPR. Having
920 // the GPR is purely vestigal at this point.
941 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/
DBPFInstrInfo.td80 let MIOperandInfo = (ops GPR, i16imm);
160 (ins GPR:$dst, GPR:$src, brtarget:$BrDst),
176 (ins GPR:$dst, i64imm:$imm, brtarget:$BrDst),
267 (outs GPR:$dst),
268 (ins GPR:$src2, GPR:$src),
270 [(set GPR:$dst, (OpNode i64:$src2, i64:$src))]>;
272 (outs GPR:$dst),
273 (ins GPR:$src2, i64imm:$imm),
275 [(set GPR:$dst, (OpNode GPR:$src2, i64immSExt32:$imm))]>;
313 def NEG_64: NEG_RR<BPF_ALU64, BPF_NEG, (outs GPR:$dst), (ins GPR:$src),
[all …]
/external/llvm-project/llvm/lib/Target/BPF/
DBPFInstrInfo.td80 let MIOperandInfo = (ops GPR, i16imm);
160 (ins GPR:$dst, GPR:$src, brtarget:$BrDst),
176 (ins GPR:$dst, i64imm:$imm, brtarget:$BrDst),
267 (outs GPR:$dst),
268 (ins GPR:$src2, GPR:$src),
270 [(set GPR:$dst, (OpNode i64:$src2, i64:$src))]>;
272 (outs GPR:$dst),
273 (ins GPR:$src2, i64imm:$imm),
275 [(set GPR:$dst, (OpNode GPR:$src2, i64immSExt32:$imm))]>;
313 def NEG_64: NEG_RR<BPF_ALU64, BPF_NEG, (outs GPR:$dst), (ins GPR:$src),
[all …]
/external/llvm-project/llvm/lib/Target/CSKY/
DCSKYInstrFormats.td62 : CSKY32Inst<AddrModeNone, 0x33, (outs GPR:$rz), (ins operand:$offset),
75 (outs GPR:$rz), (ins GPR:$rx,ImmType:$imm16),
88 : CSKY32Inst<AddrModeNone, 0x3a, (outs GPR:$rz), (ins ImmType:$imm16),
90 [(set GPR:$rz, ImmType:$imm16)]> {
105 (outs GPR:$rz), (ins operand:$imm16),
135 : CSKY32Inst<AddrModeNone, 0x3a, (outs), (ins GPR:$rx),
148 (ins GPR:$rx, operand:$imm2),
174 (ins GPR:$rx, i32imm:$imm16), !strconcat(op, "\t$rx, $imm16"), []> {
186 : CSKY32Inst<AddrModeNone, 0x3a, (outs), (ins GPR:$rx, operand:$imm16),
200 : CSKY32Inst<AddrModeNone, 0x39, (outs GPR:$rz),
[all …]
DCSKYInstrInfo.td69 (outs GPR:$rz), (ins GPR:$rx, uimm5:$imm5),
70 [(set GPR:$rz, (shl GPR:$rx, uimm5:$imm5))]>;
72 (outs GPR:$rz), (ins GPR:$rx, uimm5:$imm5),
73 [(set GPR:$rz, (srl GPR:$rx, uimm5:$imm5))]>;
75 (outs GPR:$rz), (ins GPR:$rx, uimm5:$imm5),
76 [(set GPR:$rz, (sra GPR:$rx, uimm5:$imm5))]>;
107 def NOT32 : R_XXZ<0b001001, 0b00100, (outs GPR:$rz), (ins GPR:$rx),
108 "not", [(set GPR:$rz, (not GPR:$rx))]>;

12345678910>>...19