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Searched refs:Lowering (Results 1 – 25 of 56) sorted by relevance

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/external/swiftshader/third_party/subzero/src/
DIceAssemblerARM32.h220 const TargetLowering *Lowering) { in ldr() argument
221 const TargetInfo TInfo(Lowering); in ldr()
229 CondARM32::Cond Cond, const TargetLowering *Lowering) { in ldrex() argument
230 const TargetInfo TInfo(Lowering); in ldrex()
292 const TargetLowering *Lowering) { in str() argument
293 const TargetInfo TInfo(Lowering); in str()
301 CondARM32::Cond Cond, const TargetLowering *Lowering) { in strex() argument
302 const TargetInfo TInfo(Lowering); in strex()
429 CondARM32::Cond Cond, const TargetLowering *Lowering) { in vldrd() argument
430 const TargetInfo TInfo(Lowering); in vldrd()
[all …]
DIceTargetLoweringX86Base.h1066 ScopedIacaMark(TargetX86Base *Lowering) : Lowering(Lowering) { in ScopedIacaMark() argument
1067 Lowering->_iaca_start(); in ScopedIacaMark()
1071 if (!Lowering) in end()
1073 Lowering->_iaca_end(); in end()
1074 Lowering = nullptr; in end()
1078 TargetX86Base *Lowering;
/external/tensorflow/tensorflow/compiler/mlir/tosa/g3doc/
Dlegalization.md1151 **TOSA Lowering**
1170 **TOSA Lowering** This operator is trivially lowered to tosa.ADD.
1182 **TOSA Lowering** This operator is trivially lowered to tosa.ADD.
1194 **TOSA Lowering**
1210 **TOSA Lowering**
1227 **TOSA Lowering**
1245 **TOSA Lowering**
1259 **TOSA Lowering**
1273 **TOSA Lowering**
1287 **TOSA Lowering**
[all …]
/external/llvm/lib/Target/X86/
DX86WinAllocaExpander.cpp44 enum Lowering { TouchAndSub, Sub, Probe }; enum in __anon41e05d5b0111::X86WinAllocaExpander
47 typedef MapVector<MachineInstr*, Lowering> LoweringMap;
53 Lowering getLowering(int64_t CurrentOffset, int64_t AllocaAmount);
56 void lower(MachineInstr* MI, Lowering L);
99 X86WinAllocaExpander::Lowering
163 Lowering L = getLowering(Offset, Amount); in computeLowerings()
201 void X86WinAllocaExpander::lower(MachineInstr* MI, Lowering L) { in lower()
/external/llvm-project/llvm/lib/LTO/
DUpdateCompilerUsed.cpp75 const TargetLowering *Lowering = in initializeLibCalls() local
78 if (Lowering && TLSet.insert(Lowering).second) in initializeLibCalls()
84 Lowering->getLibcallName(static_cast<RTLIB::Libcall>(I))) in initializeLibCalls()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/LTO/
DUpdateCompilerUsed.cpp74 const TargetLowering *Lowering = in initializeLibCalls() local
77 if (Lowering && TLSet.insert(Lowering).second) in initializeLibCalls()
83 Lowering->getLibcallName(static_cast<RTLIB::Libcall>(I))) in initializeLibCalls()
/external/llvm-project/llvm/lib/Target/X86/
DX86WinAllocaExpander.cpp44 enum Lowering { TouchAndSub, Sub, Probe }; enum in __anonca2e87090111::X86WinAllocaExpander
47 typedef MapVector<MachineInstr*, Lowering> LoweringMap;
53 Lowering getLowering(int64_t CurrentOffset, int64_t AllocaAmount);
56 void lower(MachineInstr* MI, Lowering L);
96 X86WinAllocaExpander::Lowering
160 Lowering L = getLowering(Offset, Amount); in computeLowerings()
198 void X86WinAllocaExpander::lower(MachineInstr* MI, Lowering L) { in lower()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86WinAllocaExpander.cpp43 enum Lowering { TouchAndSub, Sub, Probe }; enum in __anonde98ebfd0111::X86WinAllocaExpander
46 typedef MapVector<MachineInstr*, Lowering> LoweringMap;
52 Lowering getLowering(int64_t CurrentOffset, int64_t AllocaAmount);
55 void lower(MachineInstr* MI, Lowering L);
95 X86WinAllocaExpander::Lowering
159 Lowering L = getLowering(Offset, Amount); in computeLowerings()
197 void X86WinAllocaExpander::lower(MachineInstr* MI, Lowering L) { in lower()
/external/llvm/lib/LTO/
DUpdateCompilerUsed.cpp75 const TargetLowering *Lowering = in initializeLibCalls() local
78 if (Lowering && TLSet.insert(Lowering).second) in initializeLibCalls()
84 Lowering->getLibcallName(static_cast<RTLIB::Libcall>(I))) in initializeLibCalls()
/external/tensorflow/tensorflow/compiler/mlir/hlo/lib/Dialect/mhlo/transforms/
Dlegalize_to_standard_patterns.td39 // Unary Lowering Patterns.
42 // Binary Lowering Patterns.
/external/llvm-project/llvm/test/CodeGen/AArch64/
DO0-pipeline.ll16 ; CHECK-NEXT: Pre-ISel Intrinsic Lowering
21 ; CHECK-NEXT: Shadow Stack GC Lowering
DO3-pipeline.ll18 ; CHECK-NEXT: Pre-ISel Intrinsic Lowering
49 ; CHECK-NEXT: Shadow Stack GC Lowering
/external/llvm-project/llvm/test/CodeGen/X86/
DO0-pipeline.ll18 ; CHECK-NEXT: Pre-ISel Intrinsic Lowering
23 ; CHECK-NEXT: Shadow Stack GC Lowering
Dopt-pipeline.ll24 ; CHECK-NEXT: Pre-ISel Intrinsic Lowering
45 ; CHECK-NEXT: Shadow Stack GC Lowering
/external/llvm-project/llvm/test/CodeGen/WebAssembly/
Dsimd-noopt.ll4 ;; up v2i64 values. Lowering away v2i64s is a temporary measure while
/external/llvm/lib/Target/AMDGPU/
DAMDGPUISelDAGToDAG.cpp224 const SITargetLowering& Lowering = in glueCopyToM0() local
229 SDValue M0 = Lowering.copyToM0(*CurDAG, CurDAG->getEntryNode(), SDLoc(N), in glueCopyToM0()
458 const SITargetLowering& Lowering = in Select() local
460 Lowering.legalizeTargetIndependentNode(N, *CurDAG); in Select()
886 const SITargetLowering& Lowering = in SelectMUBUFAddr64() local
889 SRsrc = SDValue(Lowering.wrapAddr64Rsrc(*CurDAG, DL, Ptr), 0); in SelectMUBUFAddr64()
956 const SITargetLowering& Lowering = in SelectMUBUFOffset() local
959 SRsrc = SDValue(Lowering.buildRSRC(*CurDAG, DL, Ptr, 0, Rsrc), 0); in SelectMUBUFOffset()
1551 const AMDGPUTargetLowering& Lowering = in PostprocessISelDAG() local
1562 SDNode *ResNode = Lowering.PostISelFolding(MachineNode, *CurDAG); in PostprocessISelDAG()
/external/cpuinfo/test/dmesg/
Dnexus9.log31 [ 0.000000] Lowering sbus maximum rate from 420000000 to 372000000
32 [ 0.000000] Lowering vic03 maximum rate from 900000000 to 720000000
33 [ 0.000000] Lowering tsec maximum rate from 900000000 to 720000000
34 [ 0.000000] Lowering msenc maximum rate from 600000000 to 456000000
35 [ 0.000000] Lowering se maximum rate from 600000000 to 456000000
36 [ 0.000000] Lowering vde maximum rate from 600000000 to 456000000
37 [ 0.000000] Lowering host1x maximum rate from 500000000 to 408000000
38 [ 0.000000] Lowering vi maximum rate from 700000000 to 600000000
39 [ 0.000000] Lowering isp maximum rate from 700000000 to 600000000
40 [ 0.000000] Lowering c4bus maximum rate from 700000000 to 600000000
[all …]
/external/llvm-project/mlir/docs/Tutorials/Toy/
D_index.md30 - [Chapter #6](Ch-6.md): Lowering to LLVM and code generation. Here we'll
DCh-6.md1 # Chapter 6: Lowering to LLVM and CodeGeneration
10 ## Lowering to LLVM
102 ### Full Lowering
DCh-5.md1 # Chapter 5: Partial Lowering to Lower-Level Dialects for Optimization
154 ## Partial Lowering
174 ### Design Considerations With Partial Lowering argument
/external/llvm-project/llvm/test/CodeGen/ARM/
DO3-pipeline.ll6 ; CHECK-NEXT: Pre-ISel Intrinsic Lowering
29 ; CHECK-NEXT: Shadow Stack GC Lowering
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DAMDGPUISelDAGToDAG.cpp619 const SITargetLowering& Lowering = in glueCopyToM0() local
624 SDValue M0 = Lowering.copyToM0(*CurDAG, N->getOperand(0), SDLoc(N), Val); in glueCopyToM0()
887 const SITargetLowering& Lowering = in Select() local
889 N = Lowering.legalizeTargetIndependentNode(N, *CurDAG); in Select()
1452 const SITargetLowering& Lowering = in SelectMUBUFAddr64() local
1455 SRsrc = SDValue(Lowering.wrapAddr64Rsrc(*CurDAG, DL, Ptr), 0); in SelectMUBUFAddr64()
1611 const SITargetLowering& Lowering = in SelectMUBUFOffset() local
1614 SRsrc = SDValue(Lowering.buildRSRC(*CurDAG, DL, Ptr, 0, Rsrc), 0); in SelectMUBUFOffset()
2717 const AMDGPUTargetLowering& Lowering = in PostprocessISelDAG() local
2731 SDNode *ResNode = Lowering.PostISelFolding(MachineNode, *CurDAG); in PostprocessISelDAG()
/external/llvm-project/llvm/lib/Target/AMDGPU/
DAMDGPUISelDAGToDAG.cpp624 const SITargetLowering& Lowering = in glueCopyToM0() local
629 SDValue M0 = Lowering.copyToM0(*CurDAG, N->getOperand(0), SDLoc(N), Val); in glueCopyToM0()
870 const SITargetLowering& Lowering = in Select() local
872 N = Lowering.legalizeTargetIndependentNode(N, *CurDAG); in Select()
1520 const SITargetLowering& Lowering = in SelectMUBUFAddr64() local
1523 SRsrc = SDValue(Lowering.wrapAddr64Rsrc(*CurDAG, DL, Ptr), 0); in SelectMUBUFAddr64()
1675 const SITargetLowering& Lowering = in SelectMUBUFOffset() local
1678 SRsrc = SDValue(Lowering.buildRSRC(*CurDAG, DL, Ptr, 0, Rsrc), 0); in SelectMUBUFOffset()
2984 const AMDGPUTargetLowering& Lowering = in PostprocessISelDAG() local
2998 SDNode *ResNode = Lowering.PostISelFolding(MachineNode, *CurDAG); in PostprocessISelDAG()
/external/llvm-project/llvm/docs/
DCoroutines.rst65 Switched-Resume Lowering
126 Returned-Continuation Lowering
177 Async Lowering
228 `llvm.coro.id.async` intrinsic. Lowering will update the size entry with the
240 Lowering will split an async coroutine into a ramp function and one resume
1197 from the frontend. Lowering will add to this size the size required by the frame
1207 Lowering will update the context size requirement in this struct by adding the
1526 Lowering will replace this intrinsic with the resume function for this suspend
1534 suspend point. It should take 3 arguments. Lowering will `musttail` call this
1564 Lowering will replace this intrinsic with its coroutine function argument.
/external/XNNPACK/
DREADME.md109 - [Alibaba HALO (Heterogeneity-Aware Lowering and Optimization)](https://github.com/alibaba/heterog…

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