| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrInfo.h | 46 unsigned isLoadFromStackSlot(const MachineInstr &MI,
54 unsigned isStoreToStackSlot(const MachineInstr &MI,
109 bool analyzeLoop(MachineLoop &L, MachineInstr *&IndVarInst,
110 MachineInstr *&CmpInst) const override;
117 MachineInstr *IndVar, MachineInstr *Cmp,
119 SmallVectorImpl<MachineInstr *> &PrevInsts,
189 bool expandPostRAPseudo(MachineInstr &MI) const override;
192 bool getMemOpBaseRegImmOfs(MachineInstr &LdSt, unsigned &BaseReg,
206 bool isPredicated(const MachineInstr &MI) const override;
210 bool PredicateInstruction(MachineInstr &MI,
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| D | HexagonVLIWPacketizer.h | 12 std::vector<MachineInstr*> OldPacketMIs;
32 std::vector<MachineInstr*> IgnoreDepMIs;
53 bool ignorePseudoInstruction(const MachineInstr &MI,
58 bool isSoloInstruction(const MachineInstr &MI) override;
68 MachineBasicBlock::iterator addToPacket(MachineInstr &MI) override;
71 bool shouldAddToPacket(const MachineInstr &MI) override;
76 bool isCallDependent(const MachineInstr* MI, SDep::Kind DepType,
78 bool promoteToDotCur(MachineInstr* MI, SDep::Kind DepType,
81 bool canPromoteToDotCur(const MachineInstr* MI, const SUnit* PacketSU,
86 bool promoteToDotNew(MachineInstr* MI, SDep::Kind DepType,
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrInfo.h | 34 class MachineInstr; variable
57 unsigned isLoadFromStackSlot(const MachineInstr &MI,
65 unsigned isStoreToStackSlot(const MachineInstr &MI,
72 const MachineInstr &MI,
79 const MachineInstr &MI,
204 bool expandPostRAPseudo(MachineInstr &MI) const override;
207 bool getMemOperandWithOffset(const MachineInstr &LdSt,
222 bool isPredicated(const MachineInstr &MI) const override;
225 bool isPostIncrement(const MachineInstr &MI) const override;
229 bool PredicateInstruction(MachineInstr &MI,
[all …]
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| D | HexagonVLIWPacketizer.h | 23 class MachineInstr; variable
29 std::vector<MachineInstr *> OldPacketMIs;
54 std::vector<MachineInstr*> IgnoreDepMIs;
79 bool ignorePseudoInstruction(const MachineInstr &MI,
84 bool isSoloInstruction(const MachineInstr &MI) override;
95 MachineBasicBlock::iterator addToPacket(MachineInstr &MI) override;
98 bool shouldAddToPacket(const MachineInstr &MI) override;
109 bool isCallDependent(const MachineInstr &MI, SDep::Kind DepType,
111 bool promoteToDotCur(MachineInstr &MI, SDep::Kind DepType,
114 bool canPromoteToDotCur(const MachineInstr &MI, const SUnit *PacketSU,
[all …]
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| /external/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | CombinerHelper.h | 31 class MachineInstr; variable
42 MachineInstr *MI;
63 MachineInstr *Logic;
64 MachineInstr *Shift2;
123 bool tryCombineCopy(MachineInstr &MI);
124 bool matchCombineCopy(MachineInstr &MI);
125 void applyCombineCopy(MachineInstr &MI);
129 bool isPredecessor(const MachineInstr &DefMI, const MachineInstr &UseMI);
137 bool dominates(const MachineInstr &DefMI, const MachineInstr &UseMI);
141 bool tryCombineExtendingLoads(MachineInstr &MI);
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| D | LegalizerHelper.h | 81 LegalizeResult legalizeInstrStep(MachineInstr &MI);
84 LegalizeResult libcall(MachineInstr &MI);
88 LegalizeResult narrowScalar(MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy);
93 LegalizeResult widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy);
96 LegalizeResult bitcast(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
100 LegalizeResult lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
104 LegalizeResult fewerElementsVector(MachineInstr &MI, unsigned TypeIdx,
109 LegalizeResult moreElementsVector(MachineInstr &MI, unsigned TypeIdx,
123 void widenScalarSrc(MachineInstr &MI, LLT WideTy, unsigned OpIdx,
129 void narrowScalarSrc(MachineInstr &MI, LLT NarrowTy, unsigned OpIdx);
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| /external/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrInfo.h | 34 class MachineInstr; variable
57 unsigned isLoadFromStackSlot(const MachineInstr &MI,
65 unsigned isStoreToStackSlot(const MachineInstr &MI,
72 const MachineInstr &MI,
79 const MachineInstr &MI,
204 bool expandPostRAPseudo(MachineInstr &MI) const override;
208 const MachineInstr &LdSt,
223 bool isPredicated(const MachineInstr &MI) const override;
226 bool isPostIncrement(const MachineInstr &MI) const override;
230 bool PredicateInstruction(MachineInstr &MI,
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| D | HexagonVLIWPacketizer.h | 23 class MachineInstr; variable
29 std::vector<MachineInstr *> OldPacketMIs;
54 std::vector<MachineInstr*> IgnoreDepMIs;
86 bool ignorePseudoInstruction(const MachineInstr &MI,
91 bool isSoloInstruction(const MachineInstr &MI) override;
102 MachineBasicBlock::iterator addToPacket(MachineInstr &MI) override;
105 bool shouldAddToPacket(const MachineInstr &MI) override;
116 bool isCallDependent(const MachineInstr &MI, SDep::Kind DepType,
118 bool promoteToDotCur(MachineInstr &MI, SDep::Kind DepType,
121 bool canPromoteToDotCur(const MachineInstr &MI, const SUnit *PacketSU,
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | LegalizerHelper.h | 63 LegalizeResult legalizeInstrStep(MachineInstr &MI);
66 LegalizeResult libcall(MachineInstr &MI);
70 LegalizeResult narrowScalar(MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy);
75 LegalizeResult widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy);
79 LegalizeResult lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
83 LegalizeResult fewerElementsVector(MachineInstr &MI, unsigned TypeIdx,
88 LegalizeResult moreElementsVector(MachineInstr &MI, unsigned TypeIdx,
103 void widenScalarSrc(MachineInstr &MI, LLT WideTy, unsigned OpIdx,
109 void narrowScalarSrc(MachineInstr &MI, LLT NarrowTy, unsigned OpIdx);
114 void widenScalarDst(MachineInstr &MI, LLT WideTy, unsigned OpIdx = 0,
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| D | CombinerHelper.h | 28 class MachineInstr; variable
36 MachineInstr *MI;
74 bool tryCombineCopy(MachineInstr &MI);
75 bool matchCombineCopy(MachineInstr &MI);
76 void applyCombineCopy(MachineInstr &MI);
80 bool isPredecessor(MachineInstr &DefMI, MachineInstr &UseMI);
88 bool dominates(MachineInstr &DefMI, MachineInstr &UseMI);
92 bool tryCombineExtendingLoads(MachineInstr &MI);
93 bool matchCombineExtendingLoads(MachineInstr &MI, PreferredTuple &MatchInfo);
94 void applyCombineExtendingLoads(MachineInstr &MI, PreferredTuple &MatchInfo);
[all …]
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| /external/llvm/include/llvm/Target/ |
| D | TargetInstrInfo.h | 83 bool isTriviallyReMaterializable(const MachineInstr &MI,
99 virtual bool isReallyTriviallyReMaterializable(const MachineInstr &MI, in isReallyTriviallyReMaterializable()
119 virtual MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
143 bool isReallyTriviallyReMaterializableGeneric(const MachineInstr &MI,
162 virtual int getSPAdjust(const MachineInstr &MI) const;
169 virtual bool isCoalescableExtInstr(const MachineInstr &MI, in isCoalescableExtInstr()
180 virtual unsigned isLoadFromStackSlot(const MachineInstr &MI, in isLoadFromStackSlot()
187 virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI, in isLoadFromStackSlotPostFE()
198 virtual bool hasLoadFromStackSlot(const MachineInstr &MI,
207 virtual unsigned isStoreToStackSlot(const MachineInstr &MI, in isStoreToStackSlot()
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUInstructionSelector.h | 41 class MachineInstr; variable
60 bool select(MachineInstr &I) override;
68 const MachineInstr &GEP;
72 GEPInfo(const MachineInstr &GEP) : GEP(GEP), Imm(0) { } in GEPInfo()
77 bool isInstrUniform(const MachineInstr &MI) const;
85 bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
91 bool constrainCopyLikeIntrin(MachineInstr &MI, unsigned NewOpc) const;
92 bool selectCOPY(MachineInstr &I) const;
93 bool selectPHI(MachineInstr &I) const;
94 bool selectG_TRUNC(MachineInstr &I) const;
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| D | GCNHazardRecognizer.h | 25 class MachineInstr; variable
35 typedef function_ref<bool(MachineInstr *)> IsHazardFn;
44 MachineInstr *CurrCycleInstr;
45 std::list<MachineInstr*> EmittedInstrs;
63 void addClauseInst(const MachineInstr &MI);
73 int checkSoftClauseHazards(MachineInstr *SMEM);
74 int checkSMRDHazards(MachineInstr *SMRD);
75 int checkVMEMHazards(MachineInstr* VMEM);
76 int checkDPPHazards(MachineInstr *DPP);
77 int checkDivFMasHazards(MachineInstr *DivFMas);
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| D | AMDGPULegalizerInfo.h | 35 bool legalizeCustom(LegalizerHelper &Helper, MachineInstr &MI) const override;
41 bool legalizeAddrSpaceCast(MachineInstr &MI, MachineRegisterInfo &MRI,
43 bool legalizeFrint(MachineInstr &MI, MachineRegisterInfo &MRI,
45 bool legalizeFceil(MachineInstr &MI, MachineRegisterInfo &MRI,
47 bool legalizeFrem(MachineInstr &MI, MachineRegisterInfo &MRI,
49 bool legalizeIntrinsicTrunc(MachineInstr &MI, MachineRegisterInfo &MRI,
51 bool legalizeITOFP(MachineInstr &MI, MachineRegisterInfo &MRI,
53 bool legalizeFPTOI(MachineInstr &MI, MachineRegisterInfo &MRI,
55 bool legalizeMinNumMaxNum(LegalizerHelper &Helper, MachineInstr &MI) const;
56 bool legalizeExtractVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI,
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | GCNHazardRecognizer.h | 25 class MachineInstr; variable
35 typedef function_ref<bool(MachineInstr *)> IsHazardFn;
44 MachineInstr *CurrCycleInstr;
45 std::list<MachineInstr*> EmittedInstrs;
63 void addClauseInst(const MachineInstr &MI);
73 int checkSoftClauseHazards(MachineInstr *SMEM);
74 int checkSMRDHazards(MachineInstr *SMRD);
75 int checkVMEMHazards(MachineInstr* VMEM);
76 int checkDPPHazards(MachineInstr *DPP);
77 int checkDivFMasHazards(MachineInstr *DivFMas);
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| D | AMDGPUInstructionSelector.h | 37 class MachineInstr; variable
55 bool select(MachineInstr &I) override;
63 const MachineInstr &GEP;
67 GEPInfo(const MachineInstr &GEP) : GEP(GEP), Imm(0) { } in GEPInfo()
70 bool isInstrUniform(const MachineInstr &MI) const;
78 bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
83 bool selectCOPY(MachineInstr &I) const;
84 bool selectPHI(MachineInstr &I) const;
85 bool selectG_TRUNC(MachineInstr &I) const;
86 bool selectG_SZA_EXT(MachineInstr &I) const;
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.h | 57 void swapOperands(MachineInstr &Inst) const;
59 void lowerScalarAbs(SmallVectorImpl<MachineInstr *> &Worklist,
60 MachineInstr &Inst) const;
62 void splitScalar64BitUnaryOp(SmallVectorImpl<MachineInstr *> &Worklist,
63 MachineInstr &Inst, unsigned Opcode) const;
65 void splitScalar64BitBinaryOp(SmallVectorImpl<MachineInstr *> &Worklist,
66 MachineInstr &Inst, unsigned Opcode) const;
68 void splitScalar64BitBCNT(SmallVectorImpl<MachineInstr *> &Worklist,
69 MachineInstr &Inst) const;
70 void splitScalar64BitBFE(SmallVectorImpl<MachineInstr *> &Worklist,
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | TargetInstrInfo.h | 116 bool isTriviallyReMaterializable(const MachineInstr &MI,
132 virtual bool isReallyTriviallyReMaterializable(const MachineInstr &MI, in isReallyTriviallyReMaterializable()
152 virtual MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
175 bool isReallyTriviallyReMaterializableGeneric(const MachineInstr &MI,
188 bool isFrameInstr(const MachineInstr &I) const { in isFrameInstr()
194 bool isFrameSetup(const MachineInstr &I) const { in isFrameSetup()
206 int64_t getFrameSize(const MachineInstr &I) const { in getFrameSize()
215 int64_t getFrameTotalSize(const MachineInstr &I) const { in getFrameTotalSize()
231 virtual int getSPAdjust(const MachineInstr &MI) const;
238 virtual bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, in isCoalescableExtInstr()
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| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86InstrInfo.h | 33 AC_EVEX_2_VEX = MachineInstr::TAsmComments
47 CondCode getCondFromBranch(const MachineInstr &MI);
50 CondCode getCondFromSETCC(const MachineInstr &MI);
53 CondCode getCondFromCMov(const MachineInstr &MI);
110 inline static bool isLeaMem(const MachineInstr &MI, unsigned Op) { in isLeaMem()
123 inline static bool isMem(const MachineInstr &MI, unsigned Op) { in isMem()
139 SmallVectorImpl<MachineInstr *> &CondBranches,
153 int64_t getFrameAdjustment(const MachineInstr &I) const { in getFrameAdjustment()
162 void setFrameAdjustment(MachineInstr &I, int64_t V) const { in setFrameAdjustment()
173 int getSPAdjust(const MachineInstr &MI) const override;
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| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | TargetInstrInfo.h | 123 bool isTriviallyReMaterializable(const MachineInstr &MI,
139 virtual bool isReallyTriviallyReMaterializable(const MachineInstr &MI, in isReallyTriviallyReMaterializable()
159 virtual MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
182 bool isReallyTriviallyReMaterializableGeneric(const MachineInstr &MI,
195 bool isFrameInstr(const MachineInstr &I) const { in isFrameInstr()
201 bool isFrameSetup(const MachineInstr &I) const { in isFrameSetup()
213 int64_t getFrameSize(const MachineInstr &I) const { in getFrameSize()
222 int64_t getFrameTotalSize(const MachineInstr &I) const { in getFrameTotalSize()
238 virtual int getSPAdjust(const MachineInstr &MI) const;
245 virtual bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg, in isCoalescableExtInstr()
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| D | ReachingDefAnalysis.h | 34 class MachineInstr; variable
94 DenseMap<MachineInstr *, int> InstIds;
107 using InstSet = SmallPtrSetImpl<MachineInstr*>;
142 int getReachingDef(MachineInstr *MI, MCRegister PhysReg) const;
145 bool hasSameReachingDef(MachineInstr *A, MachineInstr *B,
150 bool isReachingDefLiveOut(MachineInstr *MI, MCRegister PhysReg) const;
154 MachineInstr *getLocalLiveOutMIDef(MachineBasicBlock *MBB,
159 MachineInstr *getUniqueReachingMIDef(MachineInstr *MI,
164 MachineInstr *getMIOperand(MachineInstr *MI, unsigned Idx) const;
168 MachineInstr *getMIOperand(MachineInstr *MI, MachineOperand &MO) const;
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsRegisterBankInfo.h | 39 getInstrMapping(const MachineInstr &MI) const override;
50 void setRegBank(MachineInstr &MI, MachineRegisterInfo &MRI) const;
79 SmallVector<MachineInstr *, 2> DefUses;
80 SmallVector<MachineInstr *, 2> UseDefs;
90 MachineInstr *skipCopiesOutgoing(MachineInstr *MI) const;
97 MachineInstr *skipCopiesIncoming(MachineInstr *MI) const;
100 AmbiguousRegDefUseContainer(const MachineInstr *MI);
101 SmallVectorImpl<MachineInstr *> &getDefUses() { return DefUses; } in getDefUses()
102 SmallVectorImpl<MachineInstr *> &getUseDefs() { return UseDefs; } in getUseDefs()
110 DenseMap<const MachineInstr *, SmallVector<const MachineInstr *, 2>>
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86InstrInfo.h | 35 AC_EVEX_2_VEX = MachineInstr::TAsmComments
49 CondCode getCondFromBranch(const MachineInstr &MI);
52 CondCode getCondFromSETCC(const MachineInstr &MI);
55 CondCode getCondFromCMov(const MachineInstr &MI);
112 inline static bool isLeaMem(const MachineInstr &MI, unsigned Op) { in isLeaMem()
125 inline static bool isMem(const MachineInstr &MI, unsigned Op) { in isMem()
141 SmallVectorImpl<MachineInstr *> &CondBranches,
155 int64_t getFrameAdjustment(const MachineInstr &I) const { in getFrameAdjustment()
164 void setFrameAdjustment(MachineInstr &I, int64_t V) const { in setFrameAdjustment()
175 int getSPAdjust(const MachineInstr &MI) const override;
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.h | 118 SmallVectorImpl<MachineInstr *> &NewMIs) const;
122 SmallVectorImpl<MachineInstr *> &NewMIs) const;
126 bool transformToImmFormFedByLI(MachineInstr &MI, const ImmInstrInfo &III,
127 unsigned ConstantOpNo, MachineInstr &DefMI,
131 bool transformToImmFormFedByAdd(MachineInstr &MI, const ImmInstrInfo &III,
132 unsigned ConstantOpNo, MachineInstr &DefMI,
139 MachineInstr *getForwardingDefMI(MachineInstr &MI,
145 bool isUseMIElgibleForForwarding(MachineInstr &MI, const ImmInstrInfo &III,
147 bool isDefMIElgibleForForwarding(MachineInstr &DefMI,
152 const MachineInstr &DefMI,
[all …]
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrInfo.h | 121 inline static bool isLeaMem(const MachineInstr &MI, unsigned Op) { in isLeaMem()
134 inline static bool isMem(const MachineInstr &MI, unsigned Op) { in isMem()
172 SmallVectorImpl<MachineInstr *> &CondBranches,
187 int getSPAdjust(const MachineInstr &MI) const override;
195 bool isCoalescableExtInstr(const MachineInstr &MI,
199 unsigned isLoadFromStackSlot(const MachineInstr &MI,
204 unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI,
207 unsigned isStoreToStackSlot(const MachineInstr &MI,
212 unsigned isStoreToStackSlotPostFE(const MachineInstr &MI,
215 bool isReallyTriviallyReMaterializable(const MachineInstr &MI,
[all …]
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