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Searched refs:SREM (Results 1 – 25 of 127) sorted by relevance

12 3 4 5 6

/external/llvm-project/llvm/test/Transforms/InstCombine/
D	srem-canonicalize.ll	7 ; CHECK-NEXT: [[SREM:%.]] = sub nsw i32 0, [[TMP1]] 8 ; CHECK-NEXT: ret i32 [[SREM]] 20 ; CHECK-NEXT: [[SREM:%.]] = srem i32 [[Y]], [[NEG]] 21 ; CHECK-NEXT: ret i32 [[SREM]] 32 ; CHECK-NEXT: [[SREM:%.]] = srem i32 [[NEG]], [[Y:%.]] 33 ; CHECK-NEXT: ret i32 [[SREM]] 43 ; CHECK-NEXT: [[SREM:%.]] = sub nsw <2 x i32> zeroinitializer, [[TMP1]] 44 ; CHECK-NEXT: ret <2 x i32> [[SREM]] 54 ; CHECK-NEXT: [[SREM:%.]] = srem i32 [[NEG]], [[Y:%.]] 55 ; CHECK-NEXT: [[SREM2:%.]] = srem i32 [[SREM]], [[NEG]]
/external/llvm-project/llvm/test/CodeGen/X86/GlobalISel/
D	x86_64-legalize-srem.mir	`77 ; CHECK: [[SREM:%[0-9]+]]:_(s8) = G_SREM [[TRUNC]], [[TRUNC1]] 78 ; CHECK: $al = COPY [[SREM]](s8) 136 ; CHECK: [[SREM:%[0-9]+]]:_(s16) = G_SREM [[TRUNC]], [[TRUNC1]] 137 ; CHECK: $ax = COPY [[SREM]](s16) 191 ; CHECK: [[SREM:%[0-9]+]]:_(s32) = G_SREM [[COPY]], [[COPY1]] 192 ; CHECK: $eax = COPY [[SREM]](s32) 244 ; CHECK: [[SREM:%[0-9]+]]:_(s64) = G_SREM [[COPY]], [[COPY1]] 245 ; CHECK: $rax = COPY [[SREM]](s64)`
D	x86-legalize-srem.mir	`76 ; CHECK: [[SREM:%[0-9]+]]:_(s8) = G_SREM [[LOAD]], [[LOAD1]] 77 ; CHECK: $al = COPY [[SREM]](s8) 138 ; CHECK: [[SREM:%[0-9]+]]:_(s16) = G_SREM [[LOAD]], [[LOAD1]] 139 ; CHECK: $ax = COPY [[SREM]](s16) 200 ; CHECK: [[SREM:%[0-9]+]]:_(s32) = G_SREM [[LOAD]], [[LOAD1]] 201 ; CHECK: $eax = COPY [[SREM]](s32)`
D	x86_64-irtranslator.ll	`210 ; CHECK: [[SREM:%[0-9]+]]:_(s8) = G_SREM [[TRUNC]], [[TRUNC1]] 211 ; CHECK: $al = COPY [[SREM]](s8) 225 ; CHECK: [[SREM:%[0-9]+]]:_(s16) = G_SREM [[TRUNC]], [[TRUNC1]] 226 ; CHECK: $ax = COPY [[SREM]](s16) 238 ; CHECK: [[SREM:%[0-9]+]]:_(s32) = G_SREM [[COPY]], [[COPY1]] 239 ; CHECK: $eax = COPY [[SREM]](s32) 251 ; CHECK: [[SREM:%[0-9]+]]:_(s64) = G_SREM [[COPY]], [[COPY1]] 252 ; CHECK: $rax = COPY [[SREM]](s64)`
/external/llvm/lib/Target/ARM/
D	ARMTargetTransformInfo.cpp	428 { ISD::SREM, MVT::v1i64, 1 * FunctionCallDivCost}, in getArithmeticInstrCost() 432 { ISD::SREM, MVT::v2i32, 2 * FunctionCallDivCost}, in getArithmeticInstrCost() 436 { ISD::SREM, MVT::v4i16, 4 * FunctionCallDivCost}, in getArithmeticInstrCost() 440 { ISD::SREM, MVT::v8i8, 8 * FunctionCallDivCost}, in getArithmeticInstrCost() 445 { ISD::SREM, MVT::v2i64, 2 * FunctionCallDivCost}, in getArithmeticInstrCost() 449 { ISD::SREM, MVT::v4i32, 4 * FunctionCallDivCost}, in getArithmeticInstrCost() 453 { ISD::SREM, MVT::v8i16, 8 * FunctionCallDivCost}, in getArithmeticInstrCost() 457 { ISD::SREM, MVT::v16i8, 16 * FunctionCallDivCost}, in getArithmeticInstrCost()
/external/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/
D	rem_and_div.mir	`47 ; MIPS32: [[SREM:%[0-9]+]]:gprb(s32) = G_SREM [[COPY1]], [[COPY]] 48 ; MIPS32: $v0 = COPY [[SREM]](s32)`
D	rem_and_div_vec.mir	158 ; P5600: [[SREM:%[0-9]+]]:fprb(<16 x s8>) = G_SREM [[LOAD]], [[LOAD1]] 159 ; P5600: G_STORE [[SREM]](<16 x s8>), [[COPY2]](p0) :: (store 16 into %ir.c) 187 ; P5600: [[SREM:%[0-9]+]]:fprb(<8 x s16>) = G_SREM [[LOAD]], [[LOAD1]] 188 ; P5600: G_STORE [[SREM]](<8 x s16>), [[COPY2]](p0) :: (store 16 into %ir.c) 216 ; P5600: [[SREM:%[0-9]+]]:fprb(<4 x s32>) = G_SREM [[LOAD]], [[LOAD1]] 217 ; P5600: G_STORE [[SREM]](<4 x s32>), [[COPY2]](p0) :: (store 16 into %ir.c) 245 ; P5600: [[SREM:%[0-9]+]]:fprb(<2 x s64>) = G_SREM [[LOAD]], [[LOAD1]] 246 ; P5600: G_STORE [[SREM]](<2 x s64>), [[COPY2]](p0) :: (store 16 into %ir.c)
/external/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/legalizer/
D	rem_and_div_vec.mir	153 ; P5600: [[SREM:%[0-9]+]]:_(<16 x s8>) = G_SREM [[LOAD]], [[LOAD1]] 154 ; P5600: G_STORE [[SREM]](<16 x s8>), [[COPY2]](p0) :: (store 16 into %ir.c) 181 ; P5600: [[SREM:%[0-9]+]]:_(<8 x s16>) = G_SREM [[LOAD]], [[LOAD1]] 182 ; P5600: G_STORE [[SREM]](<8 x s16>), [[COPY2]](p0) :: (store 16 into %ir.c) 209 ; P5600: [[SREM:%[0-9]+]]:_(<4 x s32>) = G_SREM [[LOAD]], [[LOAD1]] 210 ; P5600: G_STORE [[SREM]](<4 x s32>), [[COPY2]](p0) :: (store 16 into %ir.c) 237 ; P5600: [[SREM:%[0-9]+]]:_(<2 x s64>) = G_SREM [[LOAD]], [[LOAD1]] 238 ; P5600: G_STORE [[SREM]](<2 x s64>), [[COPY2]](p0) :: (store 16 into %ir.c)
D	rem_and_div_vec_builtin.mir	181 ; P5600: [[SREM:%[0-9]+]]:_(<16 x s8>) = G_SREM [[LOAD]], [[LOAD1]] 182 ; P5600: G_STORE [[SREM]](<16 x s8>), [[COPY2]](p0) :: (store 16 into %ir.c) 209 ; P5600: [[SREM:%[0-9]+]]:_(<8 x s16>) = G_SREM [[LOAD]], [[LOAD1]] 210 ; P5600: G_STORE [[SREM]](<8 x s16>), [[COPY2]](p0) :: (store 16 into %ir.c) 237 ; P5600: [[SREM:%[0-9]+]]:_(<4 x s32>) = G_SREM [[LOAD]], [[LOAD1]] 238 ; P5600: G_STORE [[SREM]](<4 x s32>), [[COPY2]](p0) :: (store 16 into %ir.c) 265 ; P5600: [[SREM:%[0-9]+]]:_(<2 x s64>) = G_SREM [[LOAD]], [[LOAD1]] 266 ; P5600: G_STORE [[SREM]](<2 x s64>), [[COPY2]](p0) :: (store 16 into %ir.c)
D	rem_and_div.mir	`173 ; MIPS32: [[SREM:%[0-9]+]]:_(s32) = G_SREM [[ASHR]], [[ASHR1]] 174 ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SREM]](s32) 208 ; MIPS32: [[SREM:%[0-9]+]]:_(s32) = G_SREM [[ASHR]], [[ASHR1]] 209 ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SREM]](s32) 236 ; MIPS32: [[SREM:%[0-9]+]]:_(s32) = G_SREM [[COPY1]], [[COPY]] 237 ; MIPS32: $v0 = COPY [[SREM]](s32)`
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
D	ARMTargetTransformInfo.cpp	689 { ISD::SREM, MVT::v1i64, 1 * FunctionCallDivCost}, in getArithmeticInstrCost() 693 { ISD::SREM, MVT::v2i32, 2 * FunctionCallDivCost}, in getArithmeticInstrCost() 697 { ISD::SREM, MVT::v4i16, 4 * FunctionCallDivCost}, in getArithmeticInstrCost() 701 { ISD::SREM, MVT::v8i8, 8 * FunctionCallDivCost}, in getArithmeticInstrCost() 706 { ISD::SREM, MVT::v2i64, 2 * FunctionCallDivCost}, in getArithmeticInstrCost() 710 { ISD::SREM, MVT::v4i32, 4 * FunctionCallDivCost}, in getArithmeticInstrCost() 714 { ISD::SREM, MVT::v8i16, 8 * FunctionCallDivCost}, in getArithmeticInstrCost() 718 { ISD::SREM, MVT::v16i8, 16 * FunctionCallDivCost}, in getArithmeticInstrCost() 979 case ISD::SREM: in isHardwareLoopProfitable()
/external/llvm-project/llvm/test/Transforms/TypePromotion/ARM/
D	signed.ll	`51 ; CHECK-NEXT: [[SREM:%.]] = srem i16 [[ARG:%.]], 4 52 ; CHECK-NEXT: [[CMP:%.*]] = icmp ne i16 [[SREM]], 0`
/external/llvm-project/llvm/lib/Target/ARM/
D	ARMTargetTransformInfo.cpp	1167 { ISD::SREM, MVT::v1i64, 1 * FunctionCallDivCost}, in getArithmeticInstrCost() 1171 { ISD::SREM, MVT::v2i32, 2 * FunctionCallDivCost}, in getArithmeticInstrCost() 1175 { ISD::SREM, MVT::v4i16, 4 * FunctionCallDivCost}, in getArithmeticInstrCost() 1179 { ISD::SREM, MVT::v8i8, 8 * FunctionCallDivCost}, in getArithmeticInstrCost() 1184 { ISD::SREM, MVT::v2i64, 2 * FunctionCallDivCost}, in getArithmeticInstrCost() 1188 { ISD::SREM, MVT::v4i32, 4 * FunctionCallDivCost}, in getArithmeticInstrCost() 1192 { ISD::SREM, MVT::v8i16, 8 * FunctionCallDivCost}, in getArithmeticInstrCost() 1196 { ISD::SREM, MVT::v16i8, 16 * FunctionCallDivCost}, in getArithmeticInstrCost() 1608 case ISD::SREM: in maybeLoweredToCall()
/external/llvm-project/llvm/test/CodeGen/ARM/
D	sdiv-pow2-arm-size.ll	`4 ; Check SREM`
D	divmod-eabi.ll	`12 ; All "eabi" (Bare, GNU and Android) must lower SREM/UREM to __aeabi_{u,i}divmod`
/external/llvm-project/llvm/lib/Target/X86/
D	X86TargetTransformInfo.cpp	254 if ((ISD == ISD::SDIV \|\| ISD == ISD::SREM \|\| ISD == ISD::UDIV \|\| in getArithmeticInstrCost() 259 if (ISD == ISD::SDIV \|\| ISD == ISD::SREM) { in getArithmeticInstrCost() 278 if (ISD == ISD::SREM) { in getArithmeticInstrCost() 326 { ISD::SREM, MVT::v16i32, 8 }, // pmuludq+mul+sub sequence in getArithmeticInstrCost() 346 { ISD::SREM, MVT::v8i32, 8 }, // pmuludq+mul+sub sequence in getArithmeticInstrCost() 368 { ISD::SREM, MVT::v8i32, 16+2 }, // 2pmuludq+mul+sub sequence + split. in getArithmeticInstrCost() 370 { ISD::SREM, MVT::v4i32, 8 }, // pmuludq+mul+sub sequence in getArithmeticInstrCost() 387 { ISD::SREM, MVT::v64i8, 16 }, // 2ext+2*pmulhw+mul+sub sequence in getArithmeticInstrCost() 391 { ISD::SREM, MVT::v32i16, 8 }, // vpmulhw+mul+sub sequence in getArithmeticInstrCost() 406 { ISD::SREM, MVT::v16i32, 17 }, // vpmuldq+mul+sub sequence in getArithmeticInstrCost() [all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
D	X86TargetTransformInfo.cpp	248 if ((ISD == ISD::SDIV \|\| ISD == ISD::SREM \|\| ISD == ISD::UDIV \|\| in getArithmeticInstrCost() 253 if (ISD == ISD::SDIV \|\| ISD == ISD::SREM) { in getArithmeticInstrCost() 269 if (ISD == ISD::SREM) { in getArithmeticInstrCost() 351 { ISD::SREM, MVT::v64i8, 16 }, // 2ext+2pmulhw+mul+sub sequence in getArithmeticInstrCost() 355 { ISD::SREM, MVT::v32i16, 8 }, // vpmulhw+mul+sub sequence in getArithmeticInstrCost() 370 { ISD::SREM, MVT::v16i32, 17 }, // vpmuldq+mul+sub sequence in getArithmeticInstrCost() 385 { ISD::SREM, MVT::v32i8, 16 }, // 2ext+2pmulhw+mul+sub sequence in getArithmeticInstrCost() 389 { ISD::SREM, MVT::v16i16, 8 }, // vpmulhw+mul+sub sequence in getArithmeticInstrCost() 393 { ISD::SREM, MVT::v8i32, 19 }, // vpmuldq+mul+sub sequence in getArithmeticInstrCost() 407 { ISD::SREM, MVT::v32i8, 32+2 }, // 4ext+4pmulhw+mul+sub sequence + split. in getArithmeticInstrCost() [all …]
/external/llvm/include/llvm/CodeGen/
D	ISDOpcodes.h	`195 ADD, SUB, MUL, SDIV, UDIV, SREM, UREM, enumerator`
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
D	ISDOpcodes.h	`202 ADD, SUB, MUL, SDIV, UDIV, SREM, UREM, enumerator`
/external/llvm-project/llvm/include/llvm/CodeGen/
D	ISDOpcodes.h	`237 SREM, enumerator`
/external/llvm/test/CodeGen/ARM/
D	divmod-eabi.ll	`3 ; All "eabi" (Bare, GNU and Android) must lower SREM/UREM to __aeabi_{u,i}divmod`
/external/llvm/lib/Target/Mips/
D	MipsFastISel.cpp	`1675 case ISD::SREM: in selectDivRem() 1696 unsigned MFOpc = (ISDOpcode == ISD::SREM \|\| ISDOpcode == ISD::UREM) in selectDivRem() 1799 if (!selectBinaryOp(I, ISD::SREM)) in fastSelectInstruction() 1800 return selectDivRem(I, ISD::SREM); in fastSelectInstruction()`
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
D	MipsFastISel.cpp	`1932 case ISD::SREM: in selectDivRem() 1953 unsigned MFOpc = (ISDOpcode == ISD::SREM \|\| ISDOpcode == ISD::UREM) in selectDivRem() 2054 if (!selectBinaryOp(I, ISD::SREM)) in fastSelectInstruction() 2055 return selectDivRem(I, ISD::SREM); in fastSelectInstruction()`
/external/llvm-project/llvm/lib/Target/Mips/
D	MipsFastISel.cpp	`1930 case ISD::SREM: in selectDivRem() 1951 unsigned MFOpc = (ISDOpcode == ISD::SREM \|\| ISDOpcode == ISD::UREM) in selectDivRem() 2052 if (!selectBinaryOp(I, ISD::SREM)) in fastSelectInstruction() 2053 return selectDivRem(I, ISD::SREM); in fastSelectInstruction()`
/external/llvm-project/llvm/lib/CodeGen/SelectionDAG/
D	LegalizeVectorOps.cpp	`369 case ISD::SREM: in LegalizeOp() 890 case ISD::SREM: in Expand() 1382 assert((Node->getOpcode() == ISD::SREM \|\| Node->getOpcode() == ISD::UREM) && in ExpandREM()`

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