| /external/llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/ |
| D | legalize-reduce-add.mir | 14 ; CHECK: [[VECREDUCE_ADD:%[0-9]+]]:_(s8) = G_VECREDUCE_ADD [[LOAD]](<16 x s8>)
15 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[VECREDUCE_ADD]](s8)
37 ; CHECK: [[VECREDUCE_ADD:%[0-9]+]]:_(s16) = G_VECREDUCE_ADD [[LOAD]](<8 x s16>)
38 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[VECREDUCE_ADD]](s16)
60 ; CHECK: [[VECREDUCE_ADD:%[0-9]+]]:_(s32) = G_VECREDUCE_ADD [[LOAD]](<4 x s32>)
61 ; CHECK: $w0 = COPY [[VECREDUCE_ADD]](s32)
81 ; CHECK: [[VECREDUCE_ADD:%[0-9]+]]:_(s64) = G_VECREDUCE_ADD [[LOAD]](<2 x s64>)
82 ; CHECK: $x0 = COPY [[VECREDUCE_ADD]](s64)
|
| D | regbankselect-reductions.mir | 35 ; CHECK: [[VECREDUCE_ADD:%[0-9]+]]:fpr(s32) = G_VECREDUCE_ADD [[COPY]](<4 x s32>)
36 ; CHECK: $w0 = COPY [[VECREDUCE_ADD]](s32)
|
| D | irtranslator-reductions.ll | 111 ; CHECK: [[VECREDUCE_ADD:%[0-9]+]]:_(s32) = G_VECREDUCE_ADD [[COPY]](<4 x s32>)
112 ; CHECK: $w0 = COPY [[VECREDUCE_ADD]](s32)
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 937 VECREDUCE_ADD, VECREDUCE_MUL, enumerator
|
| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 1150 VECREDUCE_ADD, enumerator
|
| /external/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorOps.cpp | 475 case ISD::VECREDUCE_ADD: in LegalizeOp()
871 case ISD::VECREDUCE_ADD: in Expand()
|
| D | SelectionDAGDumper.cpp | 461 case ISD::VECREDUCE_ADD: return "vecreduce_add"; in getOperationName()
|
| D | LegalizeIntegerTypes.cpp | 199 case ISD::VECREDUCE_ADD: in PromoteIntegerResult()
1517 case ISD::VECREDUCE_ADD: in PromoteIntegerOperand()
1963 case ISD::VECREDUCE_ADD: in PromoteIntOp_VECREDUCE()
2156 case ISD::VECREDUCE_ADD: in ExpandIntegerResult()
|
| D | LegalizeVectorTypes.cpp | 618 case ISD::VECREDUCE_ADD: in ScalarizeVectorOperand()
2119 case ISD::VECREDUCE_ADD: in SplitVectorOperand()
4391 case ISD::VECREDUCE_ADD: in WidenVectorOperand()
|
| D | LegalizeDAG.cpp | 1166 case ISD::VECREDUCE_ADD: in LegalizeOp()
3939 case ISD::VECREDUCE_ADD: in ExpandNode()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 440 case ISD::VECREDUCE_ADD: return "vecreduce_add"; in getOperationName()
|
| D | LegalizeVectorOps.cpp | 474 case ISD::VECREDUCE_ADD: in LegalizeOp()
978 case ISD::VECREDUCE_ADD: in Expand()
|
| D | LegalizeVectorTypes.cpp | 606 case ISD::VECREDUCE_ADD: in ScalarizeVectorOperand()
1986 case ISD::VECREDUCE_ADD: in SplitVectorOperand()
2072 case ISD::VECREDUCE_ADD: CombineOpc = ISD::ADD; break; in SplitVecOp_VECREDUCE()
4227 case ISD::VECREDUCE_ADD: in WidenVectorOperand()
4690 case ISD::VECREDUCE_ADD: in WidenVecOp_VECREDUCE()
|
| D | LegalizeIntegerTypes.cpp | 190 case ISD::VECREDUCE_ADD: in PromoteIntegerResult()
1313 case ISD::VECREDUCE_ADD: in PromoteIntegerOperand()
1736 case ISD::VECREDUCE_ADD: in PromoteIntOp_VECREDUCE()
1919 case ISD::VECREDUCE_ADD: in ExpandIntegerResult()
|
| D | LegalizeDAG.cpp | 1150 case ISD::VECREDUCE_ADD: in LegalizeOp()
3799 case ISD::VECREDUCE_ADD: in ExpandNode()
|
| D | TargetLowering.cpp | 7613 case ISD::VECREDUCE_ADD: BaseOpcode = ISD::ADD; break; in expandVecReduce()
|
| D | SelectionDAGBuilder.cpp | 8981 Res = DAG.getNode(ISD::VECREDUCE_ADD, dl, VT, Op1); in visitVectorReduce()
|
| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 863 setTargetDAGCombine(ISD::VECREDUCE_ADD); in AArch64TargetLowering()
1000 setOperationAction(ISD::VECREDUCE_ADD, VT, Custom); in AArch64TargetLowering()
1006 setOperationAction(ISD::VECREDUCE_ADD, MVT::v2i64, Custom); in AArch64TargetLowering()
1087 setOperationAction(ISD::VECREDUCE_ADD, VT, Custom); in AArch64TargetLowering()
1362 setOperationAction(ISD::VECREDUCE_ADD, VT, Custom); in addTypeForFixedLengthSVE()
4282 case ISD::VECREDUCE_ADD: in LowerOperation()
10210 (Op.getOpcode() != ISD::VECREDUCE_ADD && in LowerVECREDUCE()
10219 case ISD::VECREDUCE_ADD: in LowerVECREDUCE()
10249 case ISD::VECREDUCE_ADD: in LowerVECREDUCE()
11499 return DAG.getNode(ISD::VECREDUCE_ADD, DL, N->getValueType(0), Dot); in performVecReduceAddCombine()
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 714 setOperationAction(ISD::VECREDUCE_ADD, VT, Expand); in initActions()
|
| /external/llvm-project/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 832 setOperationAction(ISD::VECREDUCE_ADD, VT, Expand); in initActions()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 427 def vecreduce_add : SDNode<"ISD::VECREDUCE_ADD", SDTVecReduce>;
|
| /external/llvm-project/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 434 def vecreduce_add : SDNode<"ISD::VECREDUCE_ADD", SDTVecReduce>;
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 783 setOperationAction(ISD::VECREDUCE_ADD, VT, Custom); in AArch64TargetLowering()
3268 case ISD::VECREDUCE_ADD: in LowerOperation()
8547 case ISD::VECREDUCE_ADD: in LowerVECREDUCE()
12932 case ISD::VECREDUCE_ADD: in ReplaceNodeResults()
|
| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 296 setOperationAction(ISD::VECREDUCE_ADD, VT, Legal); in addMVEVectorTypes()
984 setTargetDAGCombine(ISD::VECREDUCE_ADD); in ARMTargetLowering()
14946 assert(N->getOpcode() == ISD::VECREDUCE_ADD); in PerformVECREDUCE_ADDCombine()
15128 return DAG.getNode(ISD::VECREDUCE_ADD, dl, ResVT, Ext); in PerformVECREDUCE_ADDCombine()
16356 case ISD::VECREDUCE_ADD: in PerformDAGCombine()
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/ |
| D | ARMGenFastISel.inc | 2658 // FastEmit functions for ISD::VECREDUCE_ADD.
2780 case ISD::VECREDUCE_ADD: return fastEmit_ISD_VECREDUCE_ADD_r(VT, RetVT, Op0, Op0IsKill);
|