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/external/swiftshader/third_party/llvm-10.0/configs/common/include/llvm/IR/
DIntrinsicsAMDGPU.h1 /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
7 \*===----------------------------------------------------------------------===*/
12 namespace llvm {
16 amdgcn_alignbit = 821, // llvm.amdgcn.alignbit
17 amdgcn_alignbyte, // llvm.amdgcn.alignbyte
18 amdgcn_atomic_dec, // llvm.amdgcn.atomic.dec
19 amdgcn_atomic_inc, // llvm.amdgcn.atomic.inc
20 amdgcn_buffer_atomic_add, // llvm.amdgcn.buffer.atomic.add
21 amdgcn_buffer_atomic_and, // llvm.amdgcn.buffer.atomic.and
22 amdgcn_buffer_atomic_cmpswap, // llvm.amdgcn.buffer.atomic.cmpswap
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DIntrinsicsNVPTX.h1 /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
7 \*===----------------------------------------------------------------------===*/
12 namespace llvm {
16 nvvm_add_rm_d = 4302, // llvm.nvvm.add.rm.d
17 nvvm_add_rm_f, // llvm.nvvm.add.rm.f
18 nvvm_add_rm_ftz_f, // llvm.nvvm.add.rm.ftz.f
19 nvvm_add_rn_d, // llvm.nvvm.add.rn.d
20 nvvm_add_rn_f, // llvm.nvvm.add.rn.f
21 nvvm_add_rn_ftz_f, // llvm.nvvm.add.rn.ftz.f
22 nvvm_add_rp_d, // llvm.nvvm.add.rp.d
[all …]
/external/tensorflow/tensorflow/compiler/xla/mlir/transforms/runtime/tests/
Drt_to_llvm.mlir1 // RUN: xla-runtime-opt %s --split-input-file --xla-rt-to-llvm | FileCheck %s
4 // CHECK: %[[CTX:.*]]: !llvm.ptr<i8>
10 // -----
13 // CHECK: %[[CTX:.*]]: !llvm.ptr<i8>
21 // CHECK: %[[LLVM_PTR:.*]] = llvm.bitcast %[[RES_PTR]]
22 // CHECK: llvm.store %[[LLVM_MEMREF]], %[[LLVM_PTR]]
27 // -----
29 // CHECK-DAG: llvm.mlir.global {{.*}} @[[ERR0:.*]]("Failed precondition #0\00")
30 // CHECK-DAG: llvm.mlir.global {{.*}} @[[ERR1:.*]]("Failed precondition #1\00")
33 // CHECK: %[[CTX:.*]]: !llvm.ptr<i8>
[all …]
/external/clang/test/CodeGen/
D3dnow-builtins.c1 …N: %clang_cc1 %s -triple=x86_64-unknown-unknown -target-feature +3dnowa -emit-llvm -o - -Werror | …
2 … RUN: %clang_cc1 %s -triple=x86_64-scei-ps4 -target-feature +3dnowa -emit-llvm -o - -Werror | File…
10 // PS4-LABEL: define i64 @test_m_pavgusb in test_m_pavgusb()
11 // GCC-LABEL: define double @test_m_pavgusb in test_m_pavgusb()
12 // CHECK: @llvm.x86.3dnow.pavgusb in test_m_pavgusb()
17 // PS4-LABEL: define i64 @test_m_pf2id in test_m_pf2id()
18 // GCC-LABEL: define double @test_m_pf2id in test_m_pf2id()
19 // CHECK: @llvm.x86.3dnow.pf2id in test_m_pf2id()
24 // PS4-LABEL: define i64 @test_m_pfacc in test_m_pfacc()
25 // GCC-LABEL: define double @test_m_pfacc in test_m_pfacc()
[all …]
Darm-v8.1a-neon-intrinsics.c1 // RUN: %clang_cc1 -triple armv8.1a-linux-gnu -target-feature +neon \
2 // RUN: -S -emit-llvm -o - %s \
3 // RUN: | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-ARM
5 // RUN: %clang_cc1 -triple aarch64-linux-gnu -target-feature +neon \
6 // RUN: -target-feature +v8.1a -S -emit-llvm -o - %s \
7 // RUN: | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-AARCH64
9 // REQUIRES: arm-registered-target,aarch64-registered-target
13 // CHECK-LABEL: test_vqrdmlah_s16
15 // CHECK-ARM: call <4 x i16> @llvm.arm.neon.vqrdmulh.v4i16(<4 x i16> {{%.*}}, <4 x i16> {{%.*}}) in test_vqrdmlah_s16()
16 // CHECK-ARM: call <4 x i16> @llvm.arm.neon.vqadds.v4i16(<4 x i16> {{%.*}}, <4 x i16> {{%.*}}) in test_vqrdmlah_s16()
[all …]
Dbuiltins-arm.c1 // RUN: %clang_cc1 -Wall -Werror -triple thumbv7-eabi -target-cpu cortex-a8 -emit-llvm -o - %s | op…
27 // CHECK: call {{.*}} @llvm.arm.hint(i32 0)
33 // CHECK: call {{.*}} @llvm.arm.hint(i32 1)
39 // CHECK: call {{.*}} @llvm.arm.hint(i32 2)
45 // CHECK: call {{.*}} @llvm.arm.hint(i32 3)
51 // CHECK: call {{.*}} @llvm.arm.hint(i32 4)
57 // CHECK: call {{.*}} @llvm.arm.hint(i32 5)
63 // CHECK: call {{.*}} @llvm.arm.dbg(i32 0)
66 __builtin_arm_dmb(1); //CHECK: call {{.*}} @llvm.arm.dmb(i32 1) in test_barrier()
67 __builtin_arm_dsb(2); //CHECK: call {{.*}} @llvm.arm.dsb(i32 2) in test_barrier()
[all …]
Dbuiltins-arm64.c1 // RUN: %clang_cc1 -triple arm64-unknown-linux -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
10 // CHECK: call {{.*}} @llvm.thread.pointer() in tp()
13 // CHECK: call {{.*}} @llvm.aarch64.rbit.i32(i32 %a)
18 // CHECK: call {{.*}} @llvm.aarch64.rbit.i64(i64 %a)
24 __builtin_arm_nop(); //CHECK: call {{.*}} @llvm.aarch64.hint(i32 0) in hints()
25 __builtin_arm_yield(); //CHECK: call {{.*}} @llvm.aarch64.hint(i32 1) in hints()
26 __builtin_arm_wfe(); //CHECK: call {{.*}} @llvm.aarch64.hint(i32 2) in hints()
27 __builtin_arm_wfi(); //CHECK: call {{.*}} @llvm.aarch64.hint(i32 3) in hints()
28 __builtin_arm_sev(); //CHECK: call {{.*}} @llvm.aarch64.hint(i32 4) in hints()
29 __builtin_arm_sevl(); //CHECK: call {{.*}} @llvm.aarch64.hint(i32 5) in hints()
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/external/llvm/test/CodeGen/AMDGPU/
Dlds-alignment.ll1 ; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa < %s | FileCheck -check-prefix=HSA -check-p…
3 @lds.align16.0 = internal unnamed_addr addrspace(3) global [38 x i8] undef, align 16
4 @lds.align16.1 = internal unnamed_addr addrspace(3) global [38 x i8] undef, align 16
6 @lds.align8.0 = internal unnamed_addr addrspace(3) global [38 x i8] undef, align 8
7 @lds.align32.0 = internal unnamed_addr addrspace(3) global [38 x i8] undef, align 32
9 @lds.missing.align.0 = internal unnamed_addr addrspace(3) global [39 x i32] undef
10 @lds.missing.align.1 = internal unnamed_addr addrspace(3) global [7 x i64] undef
12 declare void @llvm.memcpy.p3i8.p1i8.i32(i8 addrspace(3)* nocapture, i8 addrspace(1)* nocapture read…
13 declare void @llvm.memcpy.p1i8.p3i8.i32(i8 addrspace(1)* nocapture, i8 addrspace(3)* nocapture read…
16 ; HSA-LABEL: {{^}}test_no_round_size_1:
[all …]
Dllvm.amdgcn.buffer.atomic.ll1 ;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -…
2 ;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -…
4 ;CHECK-LABEL: {{^}}test1:
5 ;CHECK: buffer_atomic_swap v0, off, s[0:3], 0 glc
6 ;VI: s_movk_i32 [[SOFS:s[0-9]+]], 0x1fff
8 ;CHECK: buffer_atomic_swap v0, v1, s[0:3], 0 idxen glc
10 ;CHECK: buffer_atomic_swap v0, v2, s[0:3], 0 offen glc
12 ;CHECK: buffer_atomic_swap v0, v[1:2], s[0:3], 0 idxen offen glc
14 ;CHECK: buffer_atomic_swap v0, v2, s[0:3], 0 offen offset:42 glc
15 ;CHECK-DAG: s_waitcnt vmcnt(0)
[all …]
/external/llvm/test/CodeGen/X86/
Dstack-folding-3dnow.ll1 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+3dnow | FileCheck %s
4 ;CHECK-LABEL: stack_fold_pavgusb
5 ;CHECK: pavgusb {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
7 %2 = call x86_mmx @llvm.x86.3dnow.pavgusb(x86_mmx %a, x86_mmx %b) nounwind readnone
10 declare x86_mmx @llvm.x86.3dnow.pavgusb(x86_mmx, x86_mmx) nounwind readnone
13 ;CHECK-LABEL: stack_fold_pf2id
14 ;CHECK: pf2id {{-?[0-9]*}}(%rsp), {{%mm[0-7]}} {{.*#+}} 8-byte Folded Reload
16 %2 = call x86_mmx @llvm.x86.3dnow.pf2id(x86_mmx %a) nounwind readnone
19 declare x86_mmx @llvm.x86.3dnow.pf2id(x86_mmx) nounwind readnone
22 ;CHECK-LABEL: stack_fold_pf2iw
[all …]
Dmmx-intrinsics.ll1 ; RUN: llc < %s -march=x86 -mattr=+mmx,+ssse3,-avx | FileCheck %s --check-prefix=ALL --check-prefix…
2 ; RUN: llc < %s -march=x86 -mattr=+mmx,+avx | FileCheck %s --check-prefix=ALL --check-prefix=X86
3 ; RUN: llc < %s -march=x86-64 -mattr=+mmx,+ssse3,-avx | FileCheck %s --check-prefix=ALL --check-pre…
4 ; RUN: llc < %s -march=x86-64 -mattr=+mmx,+avx | FileCheck %s --check-prefix=ALL --check-prefix=X64
6 declare x86_mmx @llvm.x86.ssse3.phadd.w(x86_mmx, x86_mmx) nounwind readnone
9 ; ALL-LABEL: @test1
15 %3 = bitcast <4 x i16> %0 to x86_mmx
16 %4 = tail call x86_mmx @llvm.x86.ssse3.phadd.w(x86_mmx %2, x86_mmx %3) nounwind readnone
23 declare x86_mmx @llvm.x86.mmx.pcmpgt.d(x86_mmx, x86_mmx) nounwind readnone
26 ; ALL-LABEL: @test88
[all …]
Dvector-shuffle-combining-avx.ll2 ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx | FileCheck %s --check-prefix=ALL --check-prefi…
3 ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx2 | FileCheck %s --check-prefix=ALL --check-pref…
4 ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx512f | FileCheck %s --check-prefix=ALL --check-p…
8 declare <4 x float> @llvm.x86.avx.vpermil.ps(<4 x float>, i8)
9 declare <8 x float> @llvm.x86.avx.vpermil.ps.256(<8 x float>, i8)
10 declare <2 x double> @llvm.x86.avx.vpermil.pd(<2 x double>, i8)
11 declare <4 x double> @llvm.x86.avx.vpermil.pd.256(<4 x double>, i8)
13 declare <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float>, <4 x i32>)
14 declare <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float>, <8 x i32>)
15 declare <2 x double> @llvm.x86.avx.vpermilvar.pd(<2 x double>, <2 x i64>)
[all …]
D3dnow-intrinsics.ll1 ; RUN: llc < %s -march=x86 -mattr=+3dnow | FileCheck %s
9 %3 = bitcast <8 x i8> %1 to x86_mmx
10 %4 = call x86_mmx @llvm.x86.3dnow.pavgusb(x86_mmx %2, x86_mmx %3)
15 declare x86_mmx @llvm.x86.3dnow.pavgusb(x86_mmx, x86_mmx) nounwind readnone
21 %1 = tail call x86_mmx @llvm.x86.3dnow.pf2id(x86_mmx %0)
26 declare x86_mmx @llvm.x86.3dnow.pf2id(x86_mmx) nounwind readnone
33 %2 = tail call x86_mmx @llvm.x86.3dnow.pfacc(x86_mmx %0, x86_mmx %1)
34 %3 = bitcast x86_mmx %2 to <2 x float>
35 ret <2 x float> %3
38 declare x86_mmx @llvm.x86.3dnow.pfacc(x86_mmx, x86_mmx) nounwind readnone
[all …]
Dmmx-fold-load.ll1 ; RUN: llc < %s -march=x86-64 -mattr=+mmx,+sse2 | FileCheck %s
4 ; CHECK-LABEL: t0:
6 ; CHECK: movq (%[[REG1:[a-z]+]]), %mm0
7 ; CHECK-NEXT: psllq (%[[REG2:[a-z]+]]), %mm0
8 ; CHECK-NEXT: movd %mm0, %rax
9 ; CHECK-NEXT: retq
14 %3 = tail call x86_mmx @llvm.x86.mmx.pslli.q(x86_mmx %1, i32 %2)
15 %4 = bitcast x86_mmx %3 to i64
18 declare x86_mmx @llvm.x86.mmx.pslli.q(x86_mmx, i32)
21 ; CHECK-LABEL: t1:
[all …]
/external/llvm/test/CodeGen/ARM/
Dintrinsics-coprocessor.ll1 ; RUN: llc < %s -mtriple=armv7-eabi -mcpu=cortex-a8 | FileCheck %s
2 ; RUN: llc < %s -march=thumb -mtriple=thumbv7-eabi -mcpu=cortex-a8 | FileCheck %s
6 ; CHECK: mrc p7, #1, r{{[0-9]+}}, c1, c1, #4
7 %0 = tail call i32 @llvm.arm.mrc(i32 7, i32 1, i32 1, i32 1, i32 4) nounwind
8 ; CHECK: mcr p7, #1, r{{[0-9]+}}, c1, c1, #4
9 tail call void @llvm.arm.mcr(i32 7, i32 1, i32 %0, i32 1, i32 1, i32 4) nounwind
10 ; CHECK: mrc2 p7, #1, r{{[0-9]+}}, c1, c1, #4
11 %1 = tail call i32 @llvm.arm.mrc2(i32 7, i32 1, i32 1, i32 1, i32 4) nounwind
12 ; CHECK: mcr2 p7, #1, r{{[0-9]+}}, c1, c1, #4
13 tail call void @llvm.arm.mcr2(i32 7, i32 1, i32 %1, i32 1, i32 1, i32 4) nounwind
[all …]
/external/llvm/test/Analysis/CostModel/AMDGPU/
Dfabs.ll1 ; RUN: opt -cost-model -analyze -mtriple=amdgcn-unknown-amdhsa < %s | FileCheck %s
4 ; CHECK: estimated cost of 0 for {{.*}} call float @llvm.fabs.f32
7 %fabs = call float @llvm.fabs.f32(float %vec) #1
13 ; CHECK: estimated cost of 0 for {{.*}} call <2 x float> @llvm.fabs.v2f32
16 %fabs = call <2 x float> @llvm.fabs.v2f32(<2 x float> %vec) #1
22 ; CHECK: estimated cost of 0 for {{.*}} call <3 x float> @llvm.fabs.v3f32
23 define void @fabs_v3f32(<3 x float> addrspace(1)* %out, <3 x float> addrspace(1)* %vaddr) #0 {
24 %vec = load <3 x float>, <3 x float> addrspace(1)* %vaddr
25 %fabs = call <3 x float> @llvm.fabs.v3f32(<3 x float> %vec) #1
26 store <3 x float> %fabs, <3 x float> addrspace(1)* %out
[all …]
/external/tensorflow/tensorflow/compiler/mlir/tools/kernel_gen/tests/
Dtf_abi_knowledge.mlir1 // RUN: kernel-gen-opt %s -allow-unregistered-dialect -propagate-tf-abi-knowledge-to-kernels -split…
2 // RUN: kernel-gen-opt %s -allow-unregistered-dialect -propagate-shape-knowledge-to-kernels -split-…
7 // CHECK-LABEL: module attributes {gpu.container_module}
9 // CHECK-LABEL: func @abs
16 %14 = memref.reshape %arg0(%13) : (memref<*xf32>, memref<1xindex>) -> memref<?xf32>
25 // CHECK-LABEL: gpu.module @abs_kernel
27 // CHECK-LABEL: llvm.func @abs_kernel
28 … // ABI-SAME: %[[ARG0:.*]]: !llvm.ptr<f32>, %[[ARG1:.*]]: !llvm.ptr<f32> {llvm.align = 16 : index},
29 …-SAME: %[[ARG2:.*]]: i64, %[[ARG3:.*]]: i64, %[[ARG4:.*]]: i64, %[[ARG5:.*]]: !llvm.ptr<f32>, %[[A…
30 // ABI-SAME: %[[ARG7:.*]]: i64, %[[ARG8:.*]]: i64, %[[ARG9:.*]]: i64
[all …]
/external/llvm/test/Transforms/SampleProfile/
Dinline-combine.ll1 ; RUN: opt < %s -instcombine -sample-profile -sample-profile-file=%S/Inputs/inline-combine.prof -S …
2 ; RUN: opt < %s -passes="function(instcombine),sample-profile" -sample-profile-file=%S/Inputs/inlin…
4 %"class.llvm::FoldingSetNodeID" = type { %"class.llvm::SmallVector" }
5 %"class.llvm::SmallVector" = type { %"class.llvm::SmallVectorImpl.base", %"struct.llvm::SmallVector…
6 %"class.llvm::SmallVectorImpl.base" = type { %"class.llvm::SmallVectorTemplateBase.base" }
7 %"class.llvm::SmallVectorTemplateBase.base" = type { %"class.llvm::SmallVectorTemplateCommon.base" }
8 %"class.llvm::SmallVectorTemplateCommon.base" = type <{ %"class.llvm::SmallVectorBase", %"struct.ll…
9 %"class.llvm::SmallVectorBase" = type { i8*, i8*, i8* }
10 %"struct.llvm::AlignedCharArrayUnion" = type { %"struct.llvm::AlignedCharArray" }
11 %"struct.llvm::AlignedCharArray" = type { [4 x i8] }
[all …]
/external/llvm/test/Transforms/InstCombine/
Dx86-sse.ll2 ; RUN: opt < %s -instcombine -S | FileCheck %s
3 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
6 ; CHECK-LABEL: @test_rcp_ss_0(
7 ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x float> undef, float %a, i32 0
8 ; CHECK-NEXT: [[TMP2:%.*]] = tail call <4 x float> @llvm.x86.sse.rcp.ss(<4 x float> [[TMP1]])
9 ; CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x float> [[TMP2]], i32 0
10 ; CHECK-NEXT: ret float [[TMP3]]
14 %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2
15 %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3
16 %5 = tail call <4 x float> @llvm.x86.sse.rcp.ss(<4 x float> %4)
[all …]
Dx86-sse2.ll2 ; RUN: opt < %s -instcombine -S | FileCheck %s
3 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
6 ; CHECK-LABEL: @test_sqrt_sd_0(
7 ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> undef, double %a, i32 0
8 ; CHECK-NEXT: [[TMP2:%.*]] = tail call <2 x double> @llvm.x86.sse2.sqrt.sd(<2 x double> [[TMP1]])
9 ; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x double> [[TMP2]], i32 0
10 ; CHECK-NEXT: ret double [[TMP3]]
14 %3 = tail call <2 x double> @llvm.x86.sse2.sqrt.sd(<2 x double> %2)
15 %4 = extractelement <2 x double> %3, i32 0
20 ; CHECK-LABEL: @test_sqrt_sd_1(
[all …]
/external/llvm/test/Transforms/CodeGenPrepare/
Dstatepoint-relocate.ll1 ; RUN: opt -codegenprepare -S < %s | FileCheck %s
3 target datalayout = "e-i64:64-f80:128-n8:16:32:64-S128"
4 target triple = "x86_64-pc-linux-gnu"
8 define i32 @test_sor_basic(i32* %base) gc "statepoint-example" {
10 ; CHECK: getelementptr i32, i32* %base-new, i32 15
13 …%tok = call token (i64, i32, i1 ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_i1f(i64 0…
14 %base-new = call i32* @llvm.experimental.gc.relocate.p0i32(token %tok, i32 7, i32 7)
15 %ptr-new = call i32* @llvm.experimental.gc.relocate.p0i32(token %tok, i32 7, i32 8)
16 %ret = load i32, i32* %ptr-new
20 define i32 @test_sor_two_derived(i32* %base) gc "statepoint-example" {
[all …]
/external/llvm/test/CodeGen/PowerPC/
Dtoc-load-sched-bug.ll2 target datalayout = "e-m:e-i64:64-n32:64"
3 target triple = "powerpc64le-unknown-linux-gnu"
8 ; and the usual stack-adjust instructions that held the TOC restore in
11 …llvm::Module" = type { %"class.llvm::LLVMContext"*, %"class.llvm::iplist", %"class.llvm::iplist.0"…
12 %"class.llvm::iplist" = type { %"struct.llvm::ilist_traits", %"class.llvm::GlobalVariable"* }
13 %"struct.llvm::ilist_traits" = type { %"class.llvm::ilist_node" }
14 %"class.llvm::ilist_node" = type { %"class.llvm::ilist_half_node", %"class.llvm::GlobalVariable"* }
15 %"class.llvm::ilist_half_node" = type { %"class.llvm::GlobalVariable"* }
16 %"class.llvm::GlobalVariable" = type { %"class.llvm::GlobalObject", %"class.llvm::ilist_node", i8 }
17 %"class.llvm::GlobalObject" = type { %"class.llvm::GlobalValue", %"class.std::basic_string", %"clas…
[all …]
/external/llvm/test/CodeGen/Mips/
Ddsp-r1.ll1 ; RUN: llc -march=mipsel -mcpu=mips32 -mattr=+dsp -verify-machineinstrs < %s | \
8 %1 = tail call i32 @llvm.mips.extr.w(i64 %a0, i32 15)
12 declare i32 @llvm.mips.extr.w(i64, i32) nounwind
18 %1 = tail call i32 @llvm.mips.extr.w(i64 %a0, i32 %a1)
26 %1 = tail call i32 @llvm.mips.extr.r.w(i64 %a0, i32 15)
30 declare i32 @llvm.mips.extr.r.w(i64, i32) nounwind
36 %1 = tail call i32 @llvm.mips.extr.s.h(i64 %a0, i32 %a1)
40 declare i32 @llvm.mips.extr.s.h(i64, i32) nounwind
46 %1 = tail call i32 @llvm.mips.extr.rs.w(i64 %a0, i32 15)
50 declare i32 @llvm.mips.extr.rs.w(i64, i32) nounwind
[all …]
/external/llvm/test/CodeGen/AArch64/
Darm64-prefetch.ll1 ; RUN: llc %s -march arm64 -o - | FileCheck %s
12 call void @llvm.prefetch(i8* %tmp, i32 0, i32 0, i32 1)
14 call void @llvm.prefetch(i8* %tmp, i32 0, i32 1, i32 1)
16 call void @llvm.prefetch(i8* %tmp, i32 0, i32 2, i32 1)
18 call void @llvm.prefetch(i8* %tmp, i32 0, i32 3, i32 1)
21 call void @llvm.prefetch(i8* %tmp, i32 0, i32 0, i32 0)
23 call void @llvm.prefetch(i8* %tmp, i32 0, i32 1, i32 0)
25 call void @llvm.prefetch(i8* %tmp, i32 0, i32 2, i32 0)
27 call void @llvm.prefetch(i8* %tmp, i32 0, i32 3, i32 0)
30 call void @llvm.prefetch(i8* %tmp, i32 1, i32 0, i32 1)
[all …]
/external/llvm/include/llvm/IR/
DIntrinsicsNVVM.td1 //===- IntrinsicsNVVM.td - Defines NVVM intrinsics ---------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
8 //===----------------------------------------------------------------------===//
10 // This file defines all of the NVVM-specific intrinsics for use with NVPTX.
12 //===----------------------------------------------------------------------===//
721 // Atomic not available as an llvm intrinsic.
735 // intrinsics in this file, this one is a user-facing API.
762 "llvm.nvvm.ldu.global.i">;
766 "llvm.nvvm.ldu.global.f">;
770 "llvm.nvvm.ldu.global.p">;
[all …]

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