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/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/
DX86GenEVEX2VEXTables.inc3 |* X86 EVEX2VEX tables *|
9 // X86 EVEX encoded instructions that have a VEX 128 encoding
13 { X86::VADDPDZ128rm, X86::VADDPDrm },
14 { X86::VADDPDZ128rr, X86::VADDPDrr },
15 { X86::VADDPSZ128rm, X86::VADDPSrm },
16 { X86::VADDPSZ128rr, X86::VADDPSrr },
17 { X86::VADDSDZrm, X86::VADDSDrm },
18 { X86::VADDSDZrm_Int, X86::VADDSDrm_Int },
19 { X86::VADDSDZrr, X86::VADDSDrr },
20 { X86::VADDSDZrr_Int, X86::VADDSDrr_Int },
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DX86GenRegisterInfo.inc18 namespace X86 {
305 } // end namespace X86
309 namespace X86 {
431 } // end namespace X86
436 namespace X86 {
451 } // end namespace X86
1147 { X86::AH },
1148 { X86::AL },
1149 { X86::BH },
1150 { X86::BL },
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DX86GenAsmMatcher.inc4971 Inst.addOperand(MCOperand::createReg(X86::AX));
4974 Inst.addOperand(MCOperand::createReg(X86::EAX));
4977 Inst.addOperand(MCOperand::createReg(X86::RAX));
5043 Inst.addOperand(MCOperand::createReg(X86::ST1));
5046 Inst.addOperand(MCOperand::createReg(X86::ST0));
7090 case X86::AL: OpKind = MCK_AL; break;
7091 case X86::DL: OpKind = MCK_GR8_ABCD_L; break;
7092 case X86::CL: OpKind = MCK_CL; break;
7093 case X86::BL: OpKind = MCK_GR8_ABCD_L; break;
7094 case X86::AH: OpKind = MCK_GR8_ABCD_H; break;
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DX86GenRegisterBank.inc12 namespace X86 {
18 } // end namespace X86
35 namespace X86 {
38 (1u << (X86::GR8RegClassID - 0)) |
39 (1u << (X86::GR16RegClassID - 0)) |
40 (1u << (X86::LOW32_ADDR_ACCESS_RBPRegClassID - 0)) |
41 (1u << (X86::LOW32_ADDR_ACCESSRegClassID - 0)) |
42 (1u << (X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID - 0)) |
43 (1u << (X86::GR8_NOREXRegClassID - 0)) |
44 (1u << (X86::GR8_ABCD_HRegClassID - 0)) |
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DX86GenCallingConv.inc174 X86::ECX, X86::EDX, X86::R8D, X86::R9D
186 X86::RCX, X86::RDX, X86::R8, X86::R9
198 X86::EDI, X86::ESI, X86::EDX, X86::ECX
210 X86::RDI, X86::RSI, X86::RDX, X86::RCX
232 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
245 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3
258 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3
268 if (unsigned Reg = State.AllocateReg(X86::K1)) {
396 if (unsigned Reg = State.AllocateReg(X86::ECX)) {
406 X86::EAX, X86::EDX, X86::ECX
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86InstrFoldTables.cpp1 //===-- X86InstrFoldTables.cpp - X86 Instruction Folding Tables -----------===//
9 // This file contains the X86 memory folding tables.
31 // because as new instruction are added into holes in the X86 opcode map they
36 { X86::ADD16ri8_DB, X86::ADD16mi8, TB_NO_REVERSE },
37 { X86::ADD16ri_DB, X86::ADD16mi, TB_NO_REVERSE },
38 { X86::ADD16rr_DB, X86::ADD16mr, TB_NO_REVERSE },
39 { X86::ADD32ri8_DB, X86::ADD32mi8, TB_NO_REVERSE },
40 { X86::ADD32ri_DB, X86::ADD32mi, TB_NO_REVERSE },
41 { X86::ADD32rr_DB, X86::ADD32mr, TB_NO_REVERSE },
42 { X86::ADD64ri32_DB,X86::ADD64mi32, TB_NO_REVERSE },
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DX86InstrInfo.cpp1 //===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
9 // This file contains the X86 implementation of the TargetInstrInfo class.
14 #include "X86.h"
45 #define DEBUG_TYPE "x86-instr-info"
57 " fuse, but the X86 backend currently can't"),
80 : X86GenInstrInfo((STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64 in X86InstrInfo()
81 : X86::ADJCALLSTACKDOWN32), in X86InstrInfo()
82 (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64 in X86InstrInfo()
83 : X86::ADJCALLSTACKUP32), in X86InstrInfo()
84 X86::CATCHRET, in X86InstrInfo()
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DX86MCInstLower.cpp1 //===-- X86MCInstLower.cpp - Convert X86 MachineInstr to an MCInst --------===//
9 // This file contains code to lower X86 MachineInstrs to their corresponding
303 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX) in SimplifyShortImmForm()
321 case X86::MOVSX16rr8: // movsbw %al, %ax --> cbtw in SimplifyMOVSX()
322 if (Op0 == X86::AX && Op1 == X86::AL) in SimplifyMOVSX()
323 NewOpcode = X86::CBW; in SimplifyMOVSX()
325 case X86::MOVSX32rr16: // movswl %ax, %eax --> cwtl in SimplifyMOVSX()
326 if (Op0 == X86::EAX && Op1 == X86::AX) in SimplifyMOVSX()
327 NewOpcode = X86::CWDE; in SimplifyMOVSX()
329 case X86::MOVSX64rr32: // movslq %eax, %rax --> cltq in SimplifyMOVSX()
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DX86FloatingPoint.cpp25 #include "X86.h"
52 #define DEBUG_TYPE "x86-codegen"
84 StringRef getPassName() const override { return "X86 FP Stackifier"; } in getPassName()
131 static_assert(X86::FP6 - X86::FP0 == 6, "sequential regnums"); in calcLiveInMask()
132 if (Reg >= X86::FP0 && Reg <= X86::FP6) { in calcLiveInMask()
133 Mask |= 1 << (Reg - X86::FP0); in calcLiveInMask()
195 /// getStackEntry - Return the X86::FP<n> register in register ST(i).
202 /// getSTReg - Return the X86::ST(i) register which contains the specified
205 return StackTop - 1 - getSlot(RegNo) + X86::ST0; in getSTReg()
241 BuildMI(*MBB, I, dl, TII->get(X86::XCH_F)).addReg(STReg); in moveToTop()
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DX86AvoidStoreForwardingBlocks.cpp54 #define DEBUG_TYPE "x86-avoid-SFB"
57 "x86-disable-avoid-SFB", cl::Hidden,
58 cl::desc("X86: Disable Store Forwarding Blocks fixup."), cl::init(false));
61 "x86-sfb-inspection-limit",
62 cl::desc("X86: Number of instructions backward to "
76 return "X86 Avoid Store Forwarding Blocks"; in getPassName()
133 return Opcode == X86::MOVUPSrm || Opcode == X86::MOVAPSrm || in isXMMLoadOpcode()
134 Opcode == X86::VMOVUPSrm || Opcode == X86::VMOVAPSrm || in isXMMLoadOpcode()
135 Opcode == X86::VMOVUPDrm || Opcode == X86::VMOVAPDrm || in isXMMLoadOpcode()
136 Opcode == X86::VMOVDQUrm || Opcode == X86::VMOVDQArm || in isXMMLoadOpcode()
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/external/llvm/lib/Target/X86/
DX86InstrInfo.cpp1 //===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
10 // This file contains the X86 implementation of the TargetInstrInfo class.
15 #include "X86.h"
44 #define DEBUG_TYPE "x86-instr-info"
55 " fuse, but the X86 backend currently can't"),
116 : X86GenInstrInfo((STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64 in X86InstrInfo()
117 : X86::ADJCALLSTACKDOWN32), in X86InstrInfo()
118 (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64 in X86InstrInfo()
119 : X86::ADJCALLSTACKUP32), in X86InstrInfo()
120 X86::CATCHRET, in X86InstrInfo()
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DX86MCInstLower.cpp1 //===-- X86MCInstLower.cpp - Convert X86 MachineInstr to an MCInst --------===//
10 // This file contains code to lower X86 MachineInstrs to their corresponding
262 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX) in SimplifyShortImmForm()
280 case X86::MOVSX16rr8: // movsbw %al, %ax --> cbtw in SimplifyMOVSX()
281 if (Op0 == X86::AX && Op1 == X86::AL) in SimplifyMOVSX()
282 NewOpcode = X86::CBW; in SimplifyMOVSX()
284 case X86::MOVSX32rr16: // movswl %ax, %eax --> cwtl in SimplifyMOVSX()
285 if (Op0 == X86::EAX && Op1 == X86::AX) in SimplifyMOVSX()
286 NewOpcode = X86::CWDE; in SimplifyMOVSX()
288 case X86::MOVSX64rr32: // movslq %eax, %rax --> cltq in SimplifyMOVSX()
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DX86FloatingPoint.cpp26 #include "X86.h"
51 #define DEBUG_TYPE "x86-codegen"
84 const char *getPassName() const override { return "X86 FP Stackifier"; } in getPassName()
129 if (LI.PhysReg < X86::FP0 || LI.PhysReg > X86::FP6) in calcLiveInMask()
131 Mask |= 1 << (LI.PhysReg - X86::FP0); in calcLiveInMask()
187 /// getStackEntry - Return the X86::FP<n> register in register ST(i).
194 /// getSTReg - Return the X86::ST(i) register which contains the specified
197 return StackTop - 1 - getSlot(RegNo) + X86::ST0; in getSTReg()
226 BuildMI(*MBB, I, dl, TII->get(X86::XCH_F)).addReg(STReg); in moveToTop()
236 BuildMI(*MBB, I, dl, TII->get(X86::LD_Frr)).addReg(STReg); in duplicateToTop()
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/external/llvm/lib/Target/X86/MCTargetDesc/
DX86MCTargetDesc.cpp1 //===-- X86MCTargetDesc.cpp - X86 Target Descriptions ---------------------===//
10 // This file provides X86 specific target descriptions.
70 for (unsigned Reg = X86::NoRegister + 1; Reg < X86::NUM_TARGET_REGS; ++Reg) { in initLLVMToSEHAndCVRegMapping()
77 X86::AL, X86::CL, X86::DL, X86::BL, X86::AH, X86::CH, in initLLVMToSEHAndCVRegMapping()
78 X86::DH, X86::BH, X86::AX, X86::CX, X86::DX, X86::BX, in initLLVMToSEHAndCVRegMapping()
79 X86::SP, X86::BP, X86::SI, X86::DI, X86::EAX, X86::ECX, in initLLVMToSEHAndCVRegMapping()
80 X86::EDX, X86::EBX, X86::ESP, X86::EBP, X86::ESI, X86::EDI, in initLLVMToSEHAndCVRegMapping()
86 MRI->mapLLVMRegToCVReg(X86::EFLAGS, 34); in initLLVMToSEHAndCVRegMapping()
91 MRI->mapLLVMRegToCVReg(X86::FP0 + I, FP0Start + I); in initLLVMToSEHAndCVRegMapping()
96 MRI->mapLLVMRegToCVReg(X86::XMM0 + I, CVXMM0Start + I); in initLLVMToSEHAndCVRegMapping()
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DX86AsmBackend.cpp1 //===-- X86AsmBackend.cpp - X86 Assembler Backend -------------------------===//
45 case X86::reloc_riprel_4byte: in getFixupKindLog2Size()
46 case X86::reloc_riprel_4byte_relax: in getFixupKindLog2Size()
47 case X86::reloc_riprel_4byte_relax_rex: in getFixupKindLog2Size()
48 case X86::reloc_riprel_4byte_movq_load: in getFixupKindLog2Size()
49 case X86::reloc_signed_4byte: in getFixupKindLog2Size()
50 case X86::reloc_signed_4byte_relax: in getFixupKindLog2Size()
51 case X86::reloc_global_offset_table: in getFixupKindLog2Size()
58 case X86::reloc_global_offset_table8: in getFixupKindLog2Size()
88 return X86::NumTargetFixupKinds; in getNumFixupKinds()
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/external/swiftshader/third_party/llvm-10.0/configs/common/include/llvm/IR/
DIntrinsicsX86.h16 x86_3dnow_pavgusb = 6322, // llvm.x86.3dnow.pavgusb
17 x86_3dnow_pf2id, // llvm.x86.3dnow.pf2id
18 x86_3dnow_pfacc, // llvm.x86.3dnow.pfacc
19 x86_3dnow_pfadd, // llvm.x86.3dnow.pfadd
20 x86_3dnow_pfcmpeq, // llvm.x86.3dnow.pfcmpeq
21 x86_3dnow_pfcmpge, // llvm.x86.3dnow.pfcmpge
22 x86_3dnow_pfcmpgt, // llvm.x86.3dnow.pfcmpgt
23 x86_3dnow_pfmax, // llvm.x86.3dnow.pfmax
24 x86_3dnow_pfmin, // llvm.x86.3dnow.pfmin
25 x86_3dnow_pfmul, // llvm.x86.3dnow.pfmul
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/MCTargetDesc/
DX86MCTargetDesc.cpp1 //===-- X86MCTargetDesc.cpp - X86 Target Descriptions ---------------------===//
9 // This file provides X86 specific target descriptions.
74 return MI.getFlags() & X86::IP_HAS_LOCK; in hasLockPrefix()
79 for (unsigned Reg = X86::NoRegister + 1; Reg < X86::NUM_TARGET_REGS; ++Reg) { in initLLVMToSEHAndCVRegMapping()
89 {codeview::RegisterId::AL, X86::AL}, in initLLVMToSEHAndCVRegMapping()
90 {codeview::RegisterId::CL, X86::CL}, in initLLVMToSEHAndCVRegMapping()
91 {codeview::RegisterId::DL, X86::DL}, in initLLVMToSEHAndCVRegMapping()
92 {codeview::RegisterId::BL, X86::BL}, in initLLVMToSEHAndCVRegMapping()
93 {codeview::RegisterId::AH, X86::AH}, in initLLVMToSEHAndCVRegMapping()
94 {codeview::RegisterId::CH, X86::CH}, in initLLVMToSEHAndCVRegMapping()
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DX86InstPrinterCommon.cpp1 //===--- X86InstPrinterCommon.cpp - X86 assembly instruction printing -----===//
110 case X86::VPCOMBmi: case X86::VPCOMBri: OS << "b\t"; break; in printVPCOMMnemonic()
111 case X86::VPCOMDmi: case X86::VPCOMDri: OS << "d\t"; break; in printVPCOMMnemonic()
112 case X86::VPCOMQmi: case X86::VPCOMQri: OS << "q\t"; break; in printVPCOMMnemonic()
113 case X86::VPCOMUBmi: case X86::VPCOMUBri: OS << "ub\t"; break; in printVPCOMMnemonic()
114 case X86::VPCOMUDmi: case X86::VPCOMUDri: OS << "ud\t"; break; in printVPCOMMnemonic()
115 case X86::VPCOMUQmi: case X86::VPCOMUQri: OS << "uq\t"; break; in printVPCOMMnemonic()
116 case X86::VPCOMUWmi: case X86::VPCOMUWri: OS << "uw\t"; break; in printVPCOMMnemonic()
117 case X86::VPCOMWmi: case X86::VPCOMWri: OS << "w\t"; break; in printVPCOMMnemonic()
129 case X86::VPCMPBZ128rmi: case X86::VPCMPBZ128rri: in printVPCMPMnemonic()
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DX86IntelInstPrinter.cpp45 if (MI->getOpcode() == X86::DATA16_PREFIX && in printInst()
46 STI.getFeatureBits()[X86::Mode16Bit]) { in printInst()
72 case X86::CMPPDrmi: case X86::CMPPDrri: in printVecCompareInstr()
73 case X86::CMPPSrmi: case X86::CMPPSrri: in printVecCompareInstr()
74 case X86::CMPSDrm: case X86::CMPSDrr: in printVecCompareInstr()
75 case X86::CMPSDrm_Int: case X86::CMPSDrr_Int: in printVecCompareInstr()
76 case X86::CMPSSrm: case X86::CMPSSrr: in printVecCompareInstr()
77 case X86::CMPSSrm_Int: case X86::CMPSSrr_Int: in printVecCompareInstr()
99 case X86::VCMPPDrmi: case X86::VCMPPDrri: in printVecCompareInstr()
100 case X86::VCMPPDYrmi: case X86::VCMPPDYrri: in printVecCompareInstr()
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DX86ATTInstPrinter.cpp56 if (MI->getOpcode() == X86::CALLpcrel32 && in printInst()
57 (STI.getFeatureBits()[X86::Mode64Bit])) { in printInst()
66 else if (MI->getOpcode() == X86::DATA16_PREFIX && in printInst()
67 STI.getFeatureBits()[X86::Mode16Bit]) { in printInst()
92 case X86::CMPPDrmi: case X86::CMPPDrri: in printVecCompareInstr()
93 case X86::CMPPSrmi: case X86::CMPPSrri: in printVecCompareInstr()
94 case X86::CMPSDrm: case X86::CMPSDrr: in printVecCompareInstr()
95 case X86::CMPSDrm_Int: case X86::CMPSDrr_Int: in printVecCompareInstr()
96 case X86::CMPSSrm: case X86::CMPSSrr: in printVecCompareInstr()
97 case X86::CMPSSrm_Int: case X86::CMPSSrr_Int: in printVecCompareInstr()
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/external/clang/test/CodeGen/
Dcomplex-math.c1 … %clang_cc1 %s -O1 -emit-llvm -triple x86_64-unknown-unknown -o - | FileCheck %s --check-prefix=X86
2 // RUN: %clang_cc1 %s -O1 -emit-llvm -triple x86_64-pc-win64 -o - | FileCheck %s --check-prefix=X86
3 …N: %clang_cc1 %s -O1 -emit-llvm -triple i686-unknown-unknown -o - | FileCheck %s --check-prefix=X86
9 // X86-LABEL: @add_float_rr( in add_float_rr()
10 // X86: fadd in add_float_rr()
11 // X86-NOT: fadd in add_float_rr()
12 // X86: ret in add_float_rr()
16 // X86-LABEL: @add_float_cr( in add_float_cr()
17 // X86: fadd in add_float_cr()
18 // X86-NOT: fadd in add_float_cr()
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/external/llvm/lib/Target/X86/Disassembler/
DX86Disassembler.cpp1 //===-- X86Disassembler.cpp - Disassembler for x86 and x86_64 -------------===//
10 // This file is part of the X86 Disassembler.
15 // The X86 disassembler is a table-driven disassembler for the 16-, 32-, and
16 // 64-bit X86 instruction sets. The main decode sequence for an assembly
92 #define DEBUG_TYPE "x86-disassembler"
112 namespace X86 { namespace
131 /// Generic disassembler for all X86 platforms. All each platform class should
157 if (FB[X86::Mode16Bit]) { in X86GenericDisassembler()
160 } else if (FB[X86::Mode32Bit]) { in X86GenericDisassembler()
163 } else if (FB[X86::Mode64Bit]) { in X86GenericDisassembler()
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/external/libaom/
DAndroid.bp8 "av1/common/x86/av1_inv_txfm_avx2.c",
9 "av1/common/x86/cdef_block_avx2.c",
10 "av1/common/x86/cfl_avx2.c",
11 "av1/common/x86/convolve_2d_avx2.c",
12 "av1/common/x86/convolve_avx2.c",
13 "av1/common/x86/highbd_convolve_2d_avx2.c",
14 "av1/common/x86/highbd_inv_txfm_avx2.c",
15 "av1/common/x86/highbd_jnt_convolve_avx2.c",
16 "av1/common/x86/highbd_warp_affine_avx2.c",
17 "av1/common/x86/highbd_wiener_convolve_avx2.c",
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/external/llvm/test/Object/
Dobj2yaml.test2 RUN: obj2yaml %p/Inputs/trivial-object-test.coff-x86-64 | FileCheck %s --check-prefix COFF-X86-64
5 RUN: obj2yaml %p/Inputs/trivial-object-test.elf-x86-64 | FileCheck %s --check-prefix ELF-X86-64
7 RUN: obj2yaml %p/Inputs/unwind-section.elf-x86-64 \
8 RUN: | FileCheck %s --check-prefix ELF-X86-64-UNWIND
93 COFF-X86-64: header:
94 COFF-X86-64-NEXT: Machine: IMAGE_FILE_MACHINE_AMD64
96 COFF-X86-64: sections:
97 COFF-X86-64-NEXT: - Name: .text
98 COFF-X86-64-NEXT: Characteristics: [ IMAGE_SCN_CNT_CODE, IMAGE_SCN_MEM_EXECUTE, IMAGE_SCN_MEM_R…
99 COFF-X86-64-NEXT: Alignment: 16
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/external/libaom/aom_dsp/
Daom_dsp.cmake50 "${AOM_ROOT}/aom_dsp/x86/convolve_common_intrin.h")
53 "${AOM_ROOT}/aom_dsp/x86/aom_high_subpixel_8t_sse2.asm"
54 "${AOM_ROOT}/aom_dsp/x86/aom_high_subpixel_bilinear_sse2.asm"
55 "${AOM_ROOT}/aom_dsp/x86/aom_subpixel_8t_sse2.asm"
56 "${AOM_ROOT}/aom_dsp/x86/aom_subpixel_bilinear_sse2.asm"
57 "${AOM_ROOT}/aom_dsp/x86/highbd_intrapred_asm_sse2.asm"
58 "${AOM_ROOT}/aom_dsp/x86/intrapred_asm_sse2.asm"
59 "${AOM_ROOT}/aom_dsp/x86/inv_wht_sse2.asm")
62 "${AOM_ROOT}/aom_dsp/x86/aom_convolve_copy_sse2.c"
63 "${AOM_ROOT}/aom_dsp/x86/aom_subpixel_8t_intrin_sse2.c"
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12345678910>>...338