| /external/swiftshader/third_party/llvm-16.0/configs/common/include/llvm/IR/ |
| D | IntrinsicsARM.h | 16 arm_cde_cx1 = 2289, // llvm.arm.cde.cx1
17 arm_cde_cx1a, // llvm.arm.cde.cx1a
18 arm_cde_cx1d, // llvm.arm.cde.cx1d
19 arm_cde_cx1da, // llvm.arm.cde.cx1da
20 arm_cde_cx2, // llvm.arm.cde.cx2
21 arm_cde_cx2a, // llvm.arm.cde.cx2a
22 arm_cde_cx2d, // llvm.arm.cde.cx2d
23 arm_cde_cx2da, // llvm.arm.cde.cx2da
24 arm_cde_cx3, // llvm.arm.cde.cx3
25 arm_cde_cx3a, // llvm.arm.cde.cx3a
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/include/llvm/IR/ |
| D | IntrinsicsARM.h | 16 arm_cdp = 1498, // llvm.arm.cdp
17 arm_cdp2, // llvm.arm.cdp2
18 arm_clrex, // llvm.arm.clrex
19 arm_cls, // llvm.arm.cls
20 arm_cls64, // llvm.arm.cls64
21 arm_cmse_tt, // llvm.arm.cmse.tt
22 arm_cmse_tta, // llvm.arm.cmse.tta
23 arm_cmse_ttat, // llvm.arm.cmse.ttat
24 arm_cmse_ttt, // llvm.arm.cmse.ttt
25 arm_crc32b, // llvm.arm.crc32b
[all …]
|
| /external/swiftshader/third_party/llvm-16.0/llvm/include/llvm/TargetParser/ |
| D | ARMTargetParser.def | 1 //===- ARMTargetParser.def - ARM target parsing defines ---------*- C++ -*-===//
9 // This file provides defines to build up the ARM target parser's logic.
49 ARMBuildAttrs::CPUArch::Pre_v4, FK_NONE, ARM::AEK_NONE)
51 FK_NONE, ARM::AEK_NONE)
53 FK_NONE, ARM::AEK_NONE)
55 FK_NONE, ARM::AEK_NONE)
57 FK_NONE, ARM::AEK_DSP)
59 FK_NONE, ARM::AEK_DSP)
61 FK_VFPV2, ARM::AEK_DSP)
63 FK_VFPV2, ARM::AEK_DSP)
[all …]
|
| /external/llvm/test/CodeGen/ARM/ |
| D | segmented-stacks.ll | 1 ; RUN: llc < %s -mtriple=arm-linux-androideabi -verify-machineinstrs | FileCheck %s -check-prefix=A…
2 ; RUN: llc < %s -mtriple=arm-linux-unknown-gnueabi -verify-machineinstrs | FileCheck %s -check-pref…
5 ; RUN: llc < %s -mtriple=arm-linux-androideabi -filetype=obj
6 ; RUN: llc < %s -mtriple=arm-linux-unknown-gnueabi -filetype=obj
17 ; ARM-linux: test_basic:
19 ; ARM-linux: push {r4, r5}
20 ; ARM-linux-NEXT: mrc p15, #0, r4, c13, c0, #3
21 ; ARM-linux-NEXT: mov r5, sp
22 ; ARM-linux-NEXT: ldr r4, [r4, #4]
23 ; ARM-linux-NEXT: cmp r4, r5
[all …]
|
| D | debug-frame-large-stack.ll | 1 …: llc -filetype=asm -o - < %s -mtriple arm-arm-netbsd-eabi -disable-fp-elim| FileCheck %s --check-…
2 ; RUN: llc -filetype=asm -o - < %s -mtriple arm-arm-netbsd-eabi | FileCheck %s --check-prefix=CHECK…
9 ; CHECK-ARM-LABEL: test1:
10 ; CHECK-ARM: .cfi_startproc
11 ; CHECK-ARM: sub sp, sp, #256
12 ; CHECK-ARM: .cfi_endproc
14 ; CHECK-ARM-FP-ELIM-LABEL: test1:
15 ; CHECK-ARM-FP-ELIM: .cfi_startproc
16 ; CHECK-ARM-FP-ELIM: sub sp, sp, #256
17 ; CHECK-ARM-FP-ELIM: .cfi_endproc
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Support/ |
| D | ARMTargetParser.def | 1 //===- ARMTargetParser.def - ARM target parsing defines ---------*- C++ -*-===//
9 // This file provides defines to build up the ARM target parser's logic.
49 ARMBuildAttrs::CPUArch::Pre_v4, FK_NONE, ARM::AEK_NONE)
51 FK_NONE, ARM::AEK_NONE)
53 FK_NONE, ARM::AEK_NONE)
55 FK_NONE, ARM::AEK_NONE)
57 FK_NONE, ARM::AEK_NONE)
59 FK_NONE, ARM::AEK_NONE)
61 FK_NONE, ARM::AEK_NONE)
63 FK_NONE, ARM::AEK_NONE)
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMExpandPseudoInsts.cpp | 16 #include "ARM.h"
30 #define DEBUG_TYPE "arm-pseudo"
33 VerifyARMPseudo("verify-arm-pseudo-expand", cl::Hidden,
34 cl::desc("Verify machine code after expanding ARM pseudos"));
36 #define ARM_EXPAND_PSEUDO_NAME "ARM pseudo instruction expansion pass"
153 { ARM::VLD1LNq16Pseudo, ARM::VLD1LNd16, true, false, false, EvenDblSpc, 1, 4 ,true},
154 { ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD, true, true, true, EvenDblSpc, 1, 4 ,true},
155 { ARM::VLD1LNq32Pseudo, ARM::VLD1LNd32, true, false, false, EvenDblSpc, 1, 2 ,true},
156 { ARM::VLD1LNq32Pseudo_UPD, ARM::VLD1LNd32_UPD, true, true, true, EvenDblSpc, 1, 2 ,true},
157 { ARM::VLD1LNq8Pseudo, ARM::VLD1LNd8, true, false, false, EvenDblSpc, 1, 8 ,true},
[all …]
|
| D | ARMFeatures.h | 1 //===-- ARMFeatures.h - Checks for ARM instruction features -----*- C++ -*-===//
9 // This file contains the code shared between ARM CodeGen and ARM MC
28 case ARM::tADC: in isV8EligibleForIT()
29 case ARM::tADDi3: in isV8EligibleForIT()
30 case ARM::tADDi8: in isV8EligibleForIT()
31 case ARM::tADDrr: in isV8EligibleForIT()
32 case ARM::tAND: in isV8EligibleForIT()
33 case ARM::tASRri: in isV8EligibleForIT()
34 case ARM::tASRrr: in isV8EligibleForIT()
35 case ARM::tBIC: in isV8EligibleForIT()
[all …]
|
| D | ARMBaseInstrInfo.cpp | 1 //===-- ARMBaseInstrInfo.cpp - ARM Instruction Information ----------------===//
9 // This file contains the Base ARM implementation of the TargetInstrInfo class.
68 #define DEBUG_TYPE "arm-instrinfo"
74 EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
75 cl::desc("Enable ARM 2-addr to 3-addr conv"));
89 { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false },
90 { ARM::VMLSS, ARM::VMULS, ARM::VSUBS, false, false },
91 { ARM::VMLAD, ARM::VMULD, ARM::VADDD, false, false },
92 { ARM::VMLSD, ARM::VMULD, ARM::VSUBD, false, false },
93 { ARM::VNMLAS, ARM::VNMULS, ARM::VSUBS, true, false },
[all …]
|
| /external/llvm/include/llvm/Support/ |
| D | ARMTargetParser.def | 1 //===- ARMTargetParser.def - ARM target parsing defines ---------*- C++ -*-===//
10 // This file provides defines to build up the ARM target parser's logic.
48 ARMBuildAttrs::CPUArch::Pre_v4, FK_NONE, ARM::AEK_NONE)
50 FK_NONE, ARM::AEK_NONE)
52 FK_NONE, ARM::AEK_NONE)
54 FK_NONE, ARM::AEK_NONE)
56 FK_NONE, ARM::AEK_NONE)
58 FK_NONE, ARM::AEK_NONE)
60 FK_NONE, ARM::AEK_NONE)
62 FK_NONE, ARM::AEK_NONE)
[all …]
|
| /external/swiftshader/third_party/llvm-subzero/include/llvm/Support/ |
| D | ARMTargetParser.def | 1 //===- ARMTargetParser.def - ARM target parsing defines ---------*- C++ -*-===//
10 // This file provides defines to build up the ARM target parser's logic.
48 ARMBuildAttrs::CPUArch::Pre_v4, FK_NONE, ARM::AEK_NONE)
50 FK_NONE, ARM::AEK_NONE)
52 FK_NONE, ARM::AEK_NONE)
54 FK_NONE, ARM::AEK_NONE)
56 FK_NONE, ARM::AEK_NONE)
58 FK_NONE, ARM::AEK_NONE)
60 FK_NONE, ARM::AEK_NONE)
62 FK_NONE, ARM::AEK_NONE)
[all …]
|
| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/ARM/ |
| D | ARMExpandPseudoInsts.cpp | 16 #include "ARM.h"
31 #define DEBUG_TYPE "arm-pseudo"
34 VerifyARMPseudo("verify-arm-pseudo-expand", cl::Hidden,
35 cl::desc("Verify machine code after expanding ARM pseudos"));
37 #define ARM_EXPAND_PSEUDO_NAME "ARM pseudo instruction expansion pass"
186 { ARM::VLD1LNq16Pseudo, ARM::VLD1LNd16, true, false, false, EvenDblSpc, 1, 4 ,true},
187 { ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD, true, true, true, EvenDblSpc, 1, 4 ,true},
188 { ARM::VLD1LNq32Pseudo, ARM::VLD1LNd32, true, false, false, EvenDblSpc, 1, 2 ,true},
189 { ARM::VLD1LNq32Pseudo_UPD, ARM::VLD1LNd32_UPD, true, true, true, EvenDblSpc, 1, 2 ,true},
190 { ARM::VLD1LNq8Pseudo, ARM::VLD1LNd8, true, false, false, EvenDblSpc, 1, 8 ,true},
[all …]
|
| D | ARMFeatures.h | 1 //===-- ARMFeatures.h - Checks for ARM instruction features -----*- C++ -*-===//
9 // This file contains the code shared between ARM CodeGen and ARM MC
28 case ARM::tADC: in isV8EligibleForIT()
29 case ARM::tADDi3: in isV8EligibleForIT()
30 case ARM::tADDi8: in isV8EligibleForIT()
31 case ARM::tADDrr: in isV8EligibleForIT()
32 case ARM::tAND: in isV8EligibleForIT()
33 case ARM::tASRri: in isV8EligibleForIT()
34 case ARM::tASRrr: in isV8EligibleForIT()
35 case ARM::tBIC: in isV8EligibleForIT()
[all …]
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMExpandPseudoInsts.cpp | 17 #include "ARM.h"
35 #define DEBUG_TYPE "arm-pseudo"
38 VerifyARMPseudo("verify-arm-pseudo-expand", cl::Hidden,
39 cl::desc("Verify machine code after expanding ARM pseudos"));
60 return "ARM pseudo instruction expansion pass"; in getPassName()
150 { ARM::VLD1LNq16Pseudo, ARM::VLD1LNd16, true, false, false, EvenDblSpc, 1, 4 ,true},
151 { ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD, true, true, true, EvenDblSpc, 1, 4 ,true},
152 { ARM::VLD1LNq32Pseudo, ARM::VLD1LNd32, true, false, false, EvenDblSpc, 1, 2 ,true},
153 { ARM::VLD1LNq32Pseudo_UPD, ARM::VLD1LNd32_UPD, true, true, true, EvenDblSpc, 1, 2 ,true},
154 { ARM::VLD1LNq8Pseudo, ARM::VLD1LNd8, true, false, false, EvenDblSpc, 1, 8 ,true},
[all …]
|
| D | ARMFeatures.h | 1 //===-- ARMFeatures.h - Checks for ARM instruction features -----*- C++ -*-===//
10 // This file contains the code shared between ARM CodeGen and ARM MC
29 case ARM::tADC: in isV8EligibleForIT()
30 case ARM::tADDi3: in isV8EligibleForIT()
31 case ARM::tADDi8: in isV8EligibleForIT()
32 case ARM::tADDrr: in isV8EligibleForIT()
33 case ARM::tAND: in isV8EligibleForIT()
34 case ARM::tASRri: in isV8EligibleForIT()
35 case ARM::tASRrr: in isV8EligibleForIT()
36 case ARM::tBIC: in isV8EligibleForIT()
[all …]
|
| D | ARMBaseInstrInfo.cpp | 1 //===-- ARMBaseInstrInfo.cpp - ARM Instruction Information ----------------===//
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
14 #include "ARM.h"
45 #define DEBUG_TYPE "arm-instrinfo"
51 EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
52 cl::desc("Enable ARM 2-addr to 3-addr conv"));
66 { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false },
67 { ARM::VMLSS, ARM::VMULS, ARM::VSUBS, false, false },
68 { ARM::VMLAD, ARM::VMULD, ARM::VADDD, false, false },
69 { ARM::VMLSD, ARM::VMULD, ARM::VSUBD, false, false },
[all …]
|
| /external/swiftshader/third_party/llvm-16.0/configs/common/lib/Target/ARM/ |
| D | ARMGenCallingConv.inc | 59 if (unsigned Reg = State.AllocateReg(ARM::R12)) {
89 if (unsigned Reg = State.AllocateReg(ARM::R10)) {
98 if (unsigned Reg = State.AllocateReg(ARM::R8)) {
148 ARM::R0, ARM::R2
151 ARM::R0, ARM::R1
163 ARM::R0, ARM::R1, ARM::R2, ARM::R3
175 ARM::R0, ARM::R1, ARM::R2, ARM::R3
185 ARM::R0, ARM::R1, ARM::R2, ARM::R3
196 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3
205 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3
[all …]
|
| D | ARMGenMCCodeEmitter.inc | 4446 case ARM::CLREX:
4447 case ARM::MVE_LCTP:
4448 case ARM::MVE_VPNOT:
4449 case ARM::SB:
4450 case ARM::TRAP:
4451 case ARM::TRAPNaCl:
4452 case ARM::TSB:
4453 case ARM::VBSPd:
4454 case ARM::VBSPq:
4455 case ARM::VLD1LNq16Pseudo:
[all …]
|
| D | ARMGenRegisterBank.inc | 12 namespace ARM {
19 } // end namespace ARM
36 namespace ARM {
39 (1u << (ARM::HPRRegClassID - 0)) |
40 (1u << (ARM::SPRRegClassID - 0)) |
41 (1u << (ARM::SPR_8RegClassID - 0)) |
42 (1u << (ARM::FPWithVPRRegClassID - 0)) |
43 (1u << (ARM::FPWithVPR_with_ssub_0RegClassID - 0)) |
44 (1u << (ARM::FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8RegClassID - 0)) |
47 (1u << (ARM::DPRRegClassID - 32)) |
[all …]
|
| /external/compiler-rt/lib/builtins/ |
| D | CMakeLists.txt | 259 arm/adddf3vfp.S
260 arm/addsf3vfp.S
261 arm/aeabi_cdcmp.S
262 arm/aeabi_cdcmpeq_check_nan.c
263 arm/aeabi_cfcmp.S
264 arm/aeabi_cfcmpeq_check_nan.c
265 arm/aeabi_dcmp.S
266 arm/aeabi_div0.c
267 arm/aeabi_drsub.c
268 arm/aeabi_fcmp.S
[all …]
|
| /external/libhevc/ |
| D | Android.bp | 134 "common/arm",
136 "decoder/arm",
141 "common/arm/ihevc_intra_pred_filters_neon_intr.c",
142 "common/arm/ihevc_weighted_pred_neon_intr.c",
203 "decoder/arm/ihevcd_function_selector.c",
204 "decoder/arm/ihevcd_function_selector_noneon.c",
214 arm: {
216 "common/arm",
217 "decoder/arm",
221 "decoder/arm/ihevcd_function_selector.c",
[all …]
|
| /external/llvm/unittests/Support/ |
| D | TargetParserTest.cpp | 47 {NAME, ARM::ARCH_FPU, ARCH_BASE_EXT, AArch64::ArchKind::ID, ARCH_ATTR},
51 ArchNames<ARM::ArchKind> kARMARCHNames[] = {
54 {NAME, ARM::ARCH_FPU, ARCH_BASE_EXT, ARM::ID, ARCH_ATTR},
67 {NAME, AArch64::ArchKind::ID, ARM::DEFAULT_FPU, DEFAULT_EXT},
71 CpuNames<ARM::ArchKind> kARMCPUNames[] = {
73 {NAME, ARM::ID, ARM::DEFAULT_FPU, DEFAULT_EXT},
97 for (ARM::ArchKind AK = static_cast<ARM::ArchKind>(0); in TEST()
98 AK <= ARM::ArchKind::AK_LAST; in TEST()
99 AK = static_cast<ARM::ArchKind>(static_cast<unsigned>(AK) + 1)) in TEST()
100 EXPECT_TRUE(AK == ARM::AK_LAST ? ARM::getArchName(AK).empty() in TEST()
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/ |
| D | ARMGenRegisterInfo.inc | 18 namespace ARM {
317 } // end namespace ARM
321 namespace ARM {
447 } // end namespace ARM
452 namespace ARM {
458 } // end namespace ARM
463 namespace ARM {
524 } // end namespace ARM
1479 { ARM::APSR },
1480 { ARM::APSR_NZCV },
[all …]
|
| D | ARMGenCallingConv.inc | 57 if (unsigned Reg = State.AllocateReg(ARM::R12)) {
85 if (unsigned Reg = State.AllocateReg(ARM::R10)) {
94 if (unsigned Reg = State.AllocateReg(ARM::R8)) {
138 ARM::R0, ARM::R2
141 ARM::R0, ARM::R1
153 ARM::R0, ARM::R1, ARM::R2, ARM::R3
165 ARM::R0, ARM::R1, ARM::R2, ARM::R3
175 ARM::R0, ARM::R1, ARM::R2, ARM::R3
184 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3
193 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3
[all …]
|
| /external/llvm/lib/Target/ARM/Disassembler/ |
| D | ARMDisassembler.cpp | 1 //===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===//
29 #define DEBUG_TYPE "arm-disassembler"
87 /// ARM disassembler for all ARM platforms.
422 case ARM::HVC: { in checkDecodedInstruction()
442 assert(!STI.getFeatureBits()[ARM::ModeThumb] && in getInstruction()
443 "Asked to disassemble an ARM instruction but Subtarget is in Thumb " in getInstruction()
464 // VFP and NEON instructions, similarly, are shared between ARM in getInstruction()
579 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { in AddThumb1SBit()
581 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); in AddThumb1SBit()
586 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); in AddThumb1SBit()
[all …]
|