| /external/coreboot/src/soc/intel/denverton_ns/ |
| D | uart_debug.c | 16 PCI_BASE_ADDRESS_1) + in uart_platform_base()
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| D | uart.c | 31 res = probe_resource(dev, PCI_BASE_ADDRESS_1); in dnv_ns_uart_read_resources()
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| /external/coreboot/src/soc/intel/tigerlake/ |
| D | crashlog_lib.c | 101 base_addr = pci_read_config32(SA_DEV_TMT, PCI_BASE_ADDRESS_1) & in cl_get_cpu_bar_addr()
226 pci_write_config32(SA_DEV_TMT, PCI_BASE_ADDRESS_1, tmp_bar_addr); in cpu_cl_discovery()
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| /external/coreboot/src/soc/intel/baytrail/ |
| D | scc.c | 90 bar = probe_resource(dev, PCI_BASE_ADDRESS_1); in scc_enable_acpi_mode()
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| D | lpe.c | 59 assign_device_nvs(dev, &dev_nvs->lpe_bar1, PCI_BASE_ADDRESS_1); in lpe_enable_acpi_mode()
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| D | lpss.c | 39 bar = probe_resource(dev, PCI_BASE_ADDRESS_1); in dev_enable_acpi_mode()
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| /external/coreboot/src/soc/intel/apollolake/bootblock/ |
| D | bootblock.c | 67 pci_write_config32(pmc, PCI_BASE_ADDRESS_1, 0); /* 64-bit BAR */ in enable_pmcbar()
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| /external/coreboot/payloads/libpayload/include/pci/ |
| D | pci.h | 54 #define PCI_BASE_ADDRESS_1 0x14 macro
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| /external/coreboot/src/soc/intel/broadwell/pch/ |
| D | adsp.c | 30 bar1 = probe_resource(dev, PCI_BASE_ADDRESS_1); in adsp_init()
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| D | serialio.c | 172 bar1 = probe_resource(dev, PCI_BASE_ADDRESS_1); in serialio_init()
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| /external/flashrom/ |
| D | pcidev.c | 53 case PCI_BASE_ADDRESS_1: in pcidev_readbar()
71 case PCI_BASE_ADDRESS_1: in pcidev_readbar()
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| /external/coreboot/src/soc/intel/common/block/p2sb/ |
| D | p2sblib.c | 17 pci_write_config32(dev, PCI_BASE_ADDRESS_1, (uint32_t)(bar >> 32)); in p2sb_dev_enable_bar()
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| /external/coreboot/src/drivers/generic/bayhub/ |
| D | bh720.c | 40 u32 sdbar = pci_read_config32(dev, PCI_BASE_ADDRESS_1); in bh720_program_hs200_mode()
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| /external/coreboot/src/soc/intel/braswell/ |
| D | lpss.c | 38 bar = probe_resource(dev, PCI_BASE_ADDRESS_1); in dev_enable_acpi_mode()
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| D | southcluster.c | 409 pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0); in hda_work_around()
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| /external/coreboot/src/soc/intel/denverton_ns/bootblock/ |
| D | uart.c | 31 pci_write_config32(uart_dev, PCI_BASE_ADDRESS_1, in pci_early_hsuart_device_probe()
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| /external/coreboot/src/drivers/emulation/qemu/ |
| D | bochs.c | 94 res_fb = probe_resource(dev, PCI_BASE_ADDRESS_1); in bochs_init_linear_fb()
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| /external/coreboot/src/southbridge/intel/bd82x6x/ |
| D | sata.c | 49 res = probe_resource(dev, PCI_BASE_ADDRESS_1); in sata_read_resources()
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| /external/coreboot/src/southbridge/intel/lynxpoint/ |
| D | serialio.c | 172 bar1 = probe_resource(dev, PCI_BASE_ADDRESS_1); in serialio_init()
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| /external/coreboot/src/soc/intel/alderlake/ |
| D | crashlog.c | 129 base_addr = pci_read_config32(SA_DEV_TMT, PCI_BASE_ADDRESS_1) & in cl_get_cpu_bar_addr()
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| /external/coreboot/src/northbridge/intel/pineview/ |
| D | gma.c | 239 pio_res = find_resource(dev, PCI_BASE_ADDRESS_1); in gma_func0_init()
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| /external/coreboot/src/include/device/ |
| D | pci_def.h | 67 #define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */ macro
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| /external/pciutils/lib/ |
| D | emulated.c | 122 …if ((pos & ~3) == PCI_BASE_ADDRESS_1 && (ht == PCI_HEADER_TYPE_NORMAL || ht == PCI_HEADER_TYPE_BRI… in pci_emulated_read()
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| /external/coreboot/src/drivers/aspeed/common/ |
| D | ast_main.c | 395 res = probe_resource(dev->pdev, PCI_BASE_ADDRESS_1); in ast_driver_load()
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| /external/coreboot/src/soc/intel/meteorlake/ |
| D | crashlog.c | 249 base_addr = pci_read_config32(PCI_DEV_TELEMETRY, PCI_BASE_ADDRESS_1) & in cl_get_cpu_bar_addr()
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