| /external/coreboot/src/southbridge/intel/bd82x6x/ |
| D | lpc.c | 251 RCBA32_AND_OR(CIR30, ~0U, (1 << 6)|(1 << 0)); in cpt_pm_init()
252 RCBA32_AND_OR(CIR5, ~0U, (1 << 0)); in cpt_pm_init()
256 RCBA32_AND_OR(CIR6, ~0U, (1 << 5)|(1 << 18)); in cpt_pm_init()
257 RCBA32_AND_OR(CIR9, ~0U, (1 << 15)|(1 << 1)); in cpt_pm_init()
258 RCBA32_AND_OR(CIR7, ~0x1f, 0xf); in cpt_pm_init()
261 RCBA32_AND_OR(CIR10, ~0U, 0xfffff); in cpt_pm_init()
262 RCBA32_AND_OR(CIR11, ~0U, (1 << 1)); in cpt_pm_init()
274 RCBA32_AND_OR(CIR22, 0xf000f000, 0x00670060); in cpt_pm_init()
278 RCBA32_AND_OR(CIR28, ~0x0000ffff, 0x00001001); in cpt_pm_init()
279 RCBA32_AND_OR(CIR28, ~0UL, (1 << 24)); /* SATA 2/3 disabled */ in cpt_pm_init()
[all …]
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| D | early_thermal.c | 50 RCBA32_AND_OR(0x38b0, 0xffff8003, 0x403c); in early_thermal_init()
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| /external/coreboot/src/southbridge/intel/lynxpoint/ |
| D | lpc.c | 292 RCBA32_AND_OR(0x21a4, ~(7 << 15 | 7 << 12), reg32); in configure_dmi_pm()
294 RCBA32_AND_OR(0x2348, ~0xf, 0); in configure_dmi_pm()
297 RCBA32_AND_OR(0x2304, ~(1 << 10), 0); in configure_dmi_pm()
401 RCBA32_AND_OR(0x232c, ~1, 0); in lpt_lp_pm_init()
403 RCBA32_AND_OR(0x1100, ~0xc000, 0xc000); in lpt_lp_pm_init()
407 RCBA32_AND_OR(0x2320, ~0x60, 0x10); in lpt_lp_pm_init()
490 RCBA32_AND_OR(0x2234, ~0, 0xf); in enable_clock_gating()
515 RCBA32_AND_OR(0x2234, ~0, 0xf); in enable_lp_clock_gating()
530 RCBA32_AND_OR(0x2614, ~0x74000000, 0x0a206500); in enable_lp_clock_gating()
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| D | early_pch.c | 118 RCBA32_AND_OR(0x2340, ~(0xff << 0), 0x1b << 0); in early_pch_init()
119 RCBA32_AND_OR(0x2340, ~(0xff << 16), 0x3a << 16); in early_pch_init()
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| D | early_pch_native.c | 145 RCBA32_AND_OR(0x2340, ~0x00ff0000, 0x3a << 16); in pch_dmi_setup_physical_layer()
160 RCBA32_AND_OR(CIR0050, ~(0xf << 20), 2 << 20); in pch_dmi_tc_vc_mapping()
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| D | bootblock.c | 58 RCBA32_AND_OR(HPTC, ~3, 1 << 7); in bootblock_early_southbridge_init()
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| D | sata.c | 188 RCBA32_AND_OR(0x333c, 0xffcfffff, 0x00c00000); in sata_init()
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| /external/coreboot/src/soc/intel/broadwell/pch/ |
| D | lpc.c | 206 RCBA32_AND_OR(0x3f02, ~0xf, 0); in pch_misc_init()
227 RCBA32_AND_OR(0x232c, ~1, 0); in pch_pm_init_magic()
231 RCBA32_AND_OR(0x2320, ~0x60, 0x10); in pch_pm_init_magic()
235 RCBA32_AND_OR(0x3318, ~0x000f0330, 0x0dcf0400); in pch_pm_init_magic()
398 RCBA32_AND_OR(0x2614, ~0x64ff0000, 0x0a206500); in pch_cg_init()
429 RCBA32_AND_OR(0x3434, ~0x1f, 0x17); in pch_cg_init()
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| D | bootblock.c | 83 RCBA32_AND_OR(HPTC, ~3, 1 << 7); in pch_early_lpc()
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| D | sata.c | 242 RCBA32_AND_OR(0x333c, 0xffcfffff, 0x00c00000); in sata_init()
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| /external/coreboot/src/southbridge/intel/ibexpeak/ |
| D | early_usb.c | 25 RCBA32_AND_OR(USBIR0 + 4 * i, ~0xfff, currents[portmap[i].current]); in early_usb_init()
31 RCBA32_AND_OR(USBIRB, ~0x617f0, (3 << 17) | (1 << 12) | (1 << 10) in early_usb_init()
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| D | early_cir.c | 38 RCBA32_AND_OR(CIR6, 0xff1fff7f, 0x600000); in pch_setup_cir()
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| D | lpc.c | 356 RCBA32_AND_OR(0x2234, ~0UL, 0xf); in enable_clock_gating()
394 RCBA32_AND_OR(0x2304, ~(1 << 10), 0); in pch_fixups()
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| /external/coreboot/src/southbridge/intel/i82801gx/ |
| D | early_cir.c | 21 RCBA32_AND_OR(0x3430, ~(3 << 0), 1 << 0); in ich7_setup_cir()
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| /external/coreboot/src/southbridge/intel/common/ |
| D | rcba.h | 21 #define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or) macro
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