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Searched refs:DestReg (Results 1 – 25 of 53) sorted by relevance

123

/external/llvm/lib/Target/Blackfin/
DBlackfinInstrInfo.cpp102 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
104 if (BF::ALLRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
105 BuildMI(MBB, I, DL, get(BF::MOVE), DestReg) in copyPhysReg()
110 if (BF::D16RegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
111 BuildMI(MBB, I, DL, get(BF::SLL16i), DestReg) in copyPhysReg()
117 if (BF::DRegClass.contains(DestReg)) { in copyPhysReg()
119 BuildMI(MBB, I, DL, get(BF::MOVENCC_z), DestReg) in copyPhysReg()
121 BuildMI(MBB, I, DL, get(BF::BITTGL), DestReg).addReg(DestReg).addImm(0); in copyPhysReg()
125 BuildMI(MBB, I, DL, get(BF::MOVECC_zext), DestReg) in copyPhysReg()
132 if (DestReg == BF::NCC) { in copyPhysReg()
[all …]
DBlackfinInstrInfo.h51 unsigned DestReg, unsigned SrcReg,
69 unsigned DestReg, int FrameIndex,
73 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
/external/llvm/lib/Target/PowerPC/
DPPCInstrInfo.cpp304 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
307 if (PPC::GPRCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
309 else if (PPC::G8RCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
311 else if (PPC::F4RCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
313 else if (PPC::CRRCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
315 else if (PPC::VRRCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
317 else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
324 BuildMI(MBB, I, DL, MCID, DestReg) in copyPhysReg()
327 BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
499 unsigned DestReg, int FrameIdx, in LoadRegFromStackSlot() argument
[all …]
DPPCInstrInfo.h76 unsigned DestReg, int FrameIdx,
117 unsigned DestReg, unsigned SrcReg,
128 unsigned DestReg, int FrameIndex,
/external/llvm/lib/Target/ARM/
DThumb1RegisterInfo.cpp67 unsigned DestReg, unsigned SubIdx, in emitLoadConstPool() argument
78 .addReg(DestReg, getDefRegState(true), SubIdx) in emitLoadConstPool()
92 unsigned DestReg, unsigned BaseReg, in emitThumbRegPlusImmInReg() argument
98 bool isHigh = !isARMLowRegister(DestReg) || in emitThumbRegPlusImmInReg()
109 unsigned LdReg = DestReg; in emitThumbRegPlusImmInReg()
110 if (DestReg == ARM::SP) { in emitThumbRegPlusImmInReg()
130 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg); in emitThumbRegPlusImmInReg()
133 if (DestReg == ARM::SP || isSub) in emitThumbRegPlusImmInReg()
169 unsigned DestReg, unsigned BaseReg, in emitThumbRegPlusImmediate() argument
186 if (DestReg == BaseReg && BaseReg == ARM::SP) { in emitThumbRegPlusImmediate()
[all …]
DThumb1InstrInfo.cpp37 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
39 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg) in copyPhysReg()
41 assert(ARM::GPRRegClass.contains(DestReg, SrcReg) && in copyPhysReg()
76 unsigned DestReg, int FI, in loadRegFromStackSlot() argument
80 (TargetRegisterInfo::isPhysicalRegister(DestReg) && in loadRegFromStackSlot()
81 isARMLowRegister(DestReg))) && "Unknown regclass!"); in loadRegFromStackSlot()
84 (TargetRegisterInfo::isPhysicalRegister(DestReg) && in loadRegFromStackSlot()
85 isARMLowRegister(DestReg))) { in loadRegFromStackSlot()
97 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tLDRspi), DestReg) in loadRegFromStackSlot()
DThumb2InstrInfo.cpp109 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
112 if (!ARM::GPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
113 return ARMBaseInstrInfo::copyPhysReg(MBB, I, DL, DestReg, SrcReg, KillSrc); in copyPhysReg()
115 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg) in copyPhysReg()
148 unsigned DestReg, int FI, in loadRegFromStackSlot() argument
164 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg) in loadRegFromStackSlot()
169 ARMBaseInstrInfo::loadRegFromStackSlot(MBB, I, DestReg, FI, RC, TRI); in loadRegFromStackSlot()
174 unsigned DestReg, unsigned BaseReg, int NumBytes, in emitT2RegPlusImmediate() argument
182 if (DestReg != ARM::SP && DestReg != BaseReg && in emitT2RegPlusImmediate()
188 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), DestReg) in emitT2RegPlusImmediate()
[all …]
DThumb1InstrInfo.h42 unsigned DestReg, unsigned SrcReg,
52 unsigned DestReg, int FrameIndex,
DARMBaseInstrInfo.cpp616 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
618 bool GPRDest = ARM::GPRRegClass.contains(DestReg); in copyPhysReg()
622 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg) in copyPhysReg()
627 bool SPRDest = ARM::SPRRegClass.contains(DestReg); in copyPhysReg()
637 else if (ARM::DPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
639 else if (ARM::QPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
641 else if (ARM::QQPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
643 else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
648 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg); in copyPhysReg()
814 unsigned DestReg, int FI, in loadRegFromStackSlot() argument
[all …]
DThumb2RegisterInfo.cpp38 unsigned DestReg, unsigned SubIdx, in emitLoadConstPool() argument
49 .addReg(DestReg, getDefRegState(true), SubIdx) in emitLoadConstPool()
DARMBaseInstrInfo.h247 unsigned DestReg, unsigned SrcReg,
258 unsigned DestReg, int FrameIndex,
270 unsigned DestReg, unsigned SubIdx,
472 unsigned DestReg, unsigned BaseReg, int NumBytes,
478 unsigned DestReg, unsigned BaseReg, int NumBytes,
483 unsigned DestReg, unsigned BaseReg,
DThumb2InstrInfo.h43 unsigned DestReg, unsigned SrcReg,
54 unsigned DestReg, int FrameIndex,
/external/llvm/lib/Target/Mips/
DMipsInstrInfo.cpp95 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
97 bool DestCPU = Mips::CPURegsRegClass.contains(DestReg); in copyPhysReg()
102 BuildMI(MBB, I, DL, get(Mips::ADDu), DestReg).addReg(Mips::ZERO) in copyPhysReg()
110 BuildMI(MBB, I, DL, get(Mips::CFC1), DestReg) in copyPhysReg()
113 BuildMI(MBB, I, DL, get(Mips::MFC1), DestReg) in copyPhysReg()
116 BuildMI(MBB, I, DL, get(Mips::MFHI), DestReg); in copyPhysReg()
118 BuildMI(MBB, I, DL, get(Mips::MFLO), DestReg); in copyPhysReg()
126 if (Mips::CCRRegClass.contains(DestReg)) in copyPhysReg()
127 BuildMI(MBB, I, DL, get(Mips::CTC1), DestReg) in copyPhysReg()
129 else if (Mips::FGR32RegClass.contains(DestReg)) in copyPhysReg()
[all …]
/external/llvm/lib/CodeGen/
DStrongPHIElimination.cpp243 unsigned DestReg = BBI->getOperand(0).getReg(); in runOnMachineFunction() local
244 addReg(DestReg); in runOnMachineFunction()
251 unionRegs(DestReg, SrcReg); in runOnMachineFunction()
287 unsigned DestReg = BBI->getOperand(0).getReg(); in runOnMachineFunction() local
288 addReg(DestReg); in runOnMachineFunction()
293 unionRegs(DestReg, SrcReg); in runOnMachineFunction()
317 unsigned DestReg = PHI->getOperand(0).getReg(); in runOnMachineFunction() local
318 if (!InsertedDestCopies.count(DestReg)) in runOnMachineFunction()
319 MergeLIsAndRename(DestReg, NewReg); in runOnMachineFunction()
340 unsigned DestReg = I->first; in runOnMachineFunction() local
[all …]
DPHIElimination.cpp195 unsigned DestReg = MPhi->getOperand(0).getReg(); in LowerAtomicPHINode() local
212 TII->get(TargetOpcode::IMPLICIT_DEF), DestReg); in LowerAtomicPHINode()
224 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg); in LowerAtomicPHINode()
228 TII->get(TargetOpcode::COPY), DestReg) in LowerAtomicPHINode()
268 LV->addVirtualRegisterDead(DestReg, PHICopy); in LowerAtomicPHINode()
269 LV->removeVirtualRegisterDead(DestReg, MPhi); in LowerAtomicPHINode()
/external/llvm/lib/Target/Sparc/
DSparcInstrInfo.cpp271 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
273 if (SP::IntRegsRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
274 BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0) in copyPhysReg()
276 else if (SP::FPRegsRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
277 BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg) in copyPhysReg()
279 else if (SP::DFPRegsRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
280 BuildMI(MBB, I, DL, get(Subtarget.isV9() ? SP::FMOVD : SP::FpMOVD), DestReg) in copyPhysReg()
310 unsigned DestReg, int FI, in loadRegFromStackSlot() argument
317 BuildMI(MBB, I, DL, get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0); in loadRegFromStackSlot()
319 BuildMI(MBB, I, DL, get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0); in loadRegFromStackSlot()
[all …]
DSparcInstrInfo.h80 unsigned DestReg, unsigned SrcReg,
91 unsigned DestReg, int FrameIndex,
/external/llvm/lib/Target/Alpha/
DAlphaInstrInfo.cpp124 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
126 if (Alpha::GPRCRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
127 BuildMI(MBB, MI, DL, get(Alpha::BISr), DestReg) in copyPhysReg()
130 } else if (Alpha::F4RCRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
131 BuildMI(MBB, MI, DL, get(Alpha::CPYSS), DestReg) in copyPhysReg()
134 } else if (Alpha::F8RCRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
135 BuildMI(MBB, MI, DL, get(Alpha::CPYST), DestReg) in copyPhysReg()
175 unsigned DestReg, int FrameIdx, in loadRegFromStackSlot() argument
184 BuildMI(MBB, MI, DL, get(Alpha::LDS), DestReg) in loadRegFromStackSlot()
187 BuildMI(MBB, MI, DL, get(Alpha::LDT), DestReg) in loadRegFromStackSlot()
[all …]
DAlphaInstrInfo.h47 unsigned DestReg, unsigned SrcReg,
57 unsigned DestReg, int FrameIndex,
/external/llvm/include/llvm/CodeGen/
DMachineInstrBuilder.h193 unsigned DestReg) { in BuildMI() argument
195 .addReg(DestReg, RegState::Define); in BuildMI()
206 unsigned DestReg) { in BuildMI() argument
209 return MachineInstrBuilder(MI).addReg(DestReg, RegState::Define); in BuildMI()
242 unsigned DestReg) { in BuildMI() argument
243 return BuildMI(*BB, BB->end(), DL, MCID, DestReg); in BuildMI()
/external/llvm/lib/Target/XCore/
DXCoreInstrInfo.cpp336 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
338 bool GRDest = XCore::GRRegsRegClass.contains(DestReg); in copyPhysReg()
342 BuildMI(MBB, I, DL, get(XCore::ADD_2rus), DestReg) in copyPhysReg()
349 BuildMI(MBB, I, DL, get(XCore::LDAWSP_ru6), DestReg).addImm(0); in copyPhysReg()
353 if (DestReg == XCore::SP && GRSrc) { in copyPhysReg()
378 unsigned DestReg, int FrameIndex, in loadRegFromStackSlot() argument
384 BuildMI(MBB, I, DL, get(XCore::LDWFI), DestReg) in loadRegFromStackSlot()
DXCoreInstrInfo.h66 unsigned DestReg, unsigned SrcReg,
77 unsigned DestReg, int FrameIndex,
/external/llvm/lib/Target/MSP430/
DMSP430InstrInfo.cpp66 unsigned DestReg, int FrameIdx, in loadRegFromStackSlot() argument
83 .addReg(DestReg).addFrameIndex(FrameIdx).addImm(0).addMemOperand(MMO); in loadRegFromStackSlot()
86 .addReg(DestReg).addFrameIndex(FrameIdx).addImm(0).addMemOperand(MMO); in loadRegFromStackSlot()
93 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
96 if (MSP430::GR16RegClass.contains(DestReg, SrcReg)) in copyPhysReg()
98 else if (MSP430::GR8RegClass.contains(DestReg, SrcReg)) in copyPhysReg()
103 BuildMI(MBB, I, DL, get(Opc), DestReg) in copyPhysReg()
/external/llvm/lib/Target/SystemZ/
DSystemZInstrInfo.cpp75 unsigned DestReg, int FrameIdx, in loadRegFromStackSlot() argument
99 addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx); in loadRegFromStackSlot()
104 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
107 if (SystemZ::GR64RegClass.contains(DestReg, SrcReg)) in copyPhysReg()
109 else if (SystemZ::GR32RegClass.contains(DestReg, SrcReg)) in copyPhysReg()
111 else if (SystemZ::GR64PRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
113 else if (SystemZ::GR128RegClass.contains(DestReg, SrcReg)) in copyPhysReg()
115 else if (SystemZ::FP32RegClass.contains(DestReg, SrcReg)) in copyPhysReg()
117 else if (SystemZ::FP64RegClass.contains(DestReg, SrcReg)) in copyPhysReg()
122 BuildMI(MBB, I, DL, get(Opc), DestReg) in copyPhysReg()
/external/llvm/lib/Target/CellSPU/
DSPUInstrInfo.h49 unsigned DestReg, unsigned SrcReg,
62 unsigned DestReg, int FrameIndex,

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